From: Mark Brown <broonie@kernel.org>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>,
Jay Fang <f.fangjian@huawei.com>,
"linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
"linuxarm@huawei.com" <linuxarm@huawei.com>,
"huangdaode@huawei.com" <huangdaode@huawei.com>,
"tangzihao1@hisilicon.com" <tangzihao1@hisilicon.com>
Subject: Re: [PATCH 0/2] spi: Correct CS GPIOs polarity when using GPIO descriptors
Date: Thu, 6 May 2021 12:24:24 +0100 [thread overview]
Message-ID: <20210506112424.GA4642@sirena.org.uk> (raw)
In-Reply-To: <CACRpkdYR99SRgDJEK6e-eT86hBOxz-Ym5pf8Zn+0k4u+i=nfOA@mail.gmail.com>
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On Thu, May 06, 2021 at 01:06:23PM +0200, Linus Walleij wrote:
> Interesting that the PXA2xx XScale lives in Merrifield,
> I didn't know. Reminds med of how the Samsung
> hardware is alive and well in the recent Apple M1 laptops.
There's a lot of PXA IP blocks in modern Intel SoCs - half the audio
hardware is PXA derived (though mostly connected via DSP rather than
directly to the CPU).
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next prev parent reply other threads:[~2021-05-06 11:25 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-06 3:00 [PATCH 0/2] spi: Correct CS GPIOs polarity when using GPIO descriptors Jay Fang
2021-05-06 3:00 ` [PATCH 1/2] " Jay Fang
2021-05-06 3:00 ` [PATCH 2/2] Revert "gpio: of: Handle SPI chipselect legacy bindings" Jay Fang
[not found] ` <CAHp75Vfr8t9UVqVn6hLSN6Mi3=iNAn612eE-qKq9HfrwNhpg3Q@mail.gmail.com>
[not found] ` <CAHp75Vei0QGaKiq5Nai7Gsa=jcMSipaXV_6qZbBy=f0OrN=DHQ@mail.gmail.com>
2021-05-06 9:11 ` [PATCH 0/2] spi: Correct CS GPIOs polarity when using GPIO descriptors Jay Fang
2021-05-06 9:44 ` Andy Shevchenko
2021-05-06 9:51 ` Andy Shevchenko
2021-05-06 11:06 ` Linus Walleij
2021-05-06 11:24 ` Mark Brown [this message]
[not found] ` <CAHp75Veoqnd3Hgzq8DAz-_=QxMt-+r608dkzPp67YA5eitLJNw@mail.gmail.com>
2021-05-06 11:34 ` Mark Brown
2021-05-06 12:17 ` Andy Shevchenko
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