From: Jesse Taube <mr.bossman075@gmail.com>
To: linux-imx@nxp.com
Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
ulf.hansson@linaro.org, aisheng.dong@nxp.com, stefan@agner.ch,
linus.walleij@linaro.org, gregkh@linuxfoundation.org,
arnd@arndb.de, olof@lixom.net, soc@kernel.org,
linux@armlinux.org.uk, abel.vesa@nxp.com,
adrian.hunter@intel.com, jirislaby@kernel.org,
giulio.benetti@benettiengineering.com,
nobuhiro1.iwamatsu@toshiba.co.jp, Mr.Bossman075@gmail.com,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org
Subject: [PATCH v2 12/13] ARM: dts: imx: add i.MXRT1050-EVK support
Date: Tue, 2 Nov 2021 18:57:00 -0400 [thread overview]
Message-ID: <20211102225701.98944-13-Mr.Bossman075@gmail.com> (raw)
In-Reply-To: <20211102225701.98944-1-Mr.Bossman075@gmail.com>
From: Giulio Benetti <giulio.benetti@benettiengineering.com>
The NXP i.MXRT1050 Evaluation Kit (EVK) provides a platform for rapid
evaluation of the i.MXRT, which features NXP's implementation of the Arm
Cortex-M7 core.
The EVK provides 32 MB SDRAM, 64 MB Quad SPI flash, Micro SD card socket,
USB 2.0 OTG.
This patch aims to support the preliminary booting up features
as follows:
GPIO
LPUART
SD/MMC
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
[Jesse: Add clock-parents, edma, usdhc, anatop, remove old pinctl]
---
V1->V2:
* dtsi: Add clock parent definitions
* dtsi: Change hex values to lowercase
* dtsi: Move anatop definition from driver
* dts: Remove unused pin controll (semc)
* dts: Use moved pin controll header
* Move aliases from dtsi to dts
* Change commit description
* Change licence to "GPL-2.0+ OR MIT"
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/imxrt1050-evk.dts | 89 +++++++++++++
arch/arm/boot/dts/imxrt1050.dtsi | 187 ++++++++++++++++++++++++++++
3 files changed, 278 insertions(+)
create mode 100644 arch/arm/boot/dts/imxrt1050-evk.dts
create mode 100644 arch/arm/boot/dts/imxrt1050.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7e0934180724..f32dd34550cb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -708,6 +708,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
dtb-$(CONFIG_SOC_IMX7ULP) += \
imx7ulp-com.dtb \
imx7ulp-evk.dtb
+dtb-$(CONFIG_SOC_IMXRT) += \
+ imxrt1050-evk.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-moxa-uc-8410a.dtb \
ls1021a-qds.dtb \
diff --git a/arch/arm/boot/dts/imxrt1050-evk.dts b/arch/arm/boot/dts/imxrt1050-evk.dts
new file mode 100644
index 000000000000..e414284a1544
--- /dev/null
+++ b/arch/arm/boot/dts/imxrt1050-evk.dts
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+/dts-v1/;
+#include "imxrt1050.dtsi"
+#include "imxrt1050-pinfunc.h"
+
+/ {
+ model = "NXP IMXRT1050-evk board";
+ compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
+
+ chosen {
+ bootargs = "root=/dev/ram";
+ stdout-path = &lpuart1;
+ };
+
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ mmc0 = &usdhc1;
+ serial0 = &lpuart1;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x80000000 0x2000000>;
+ };
+
+};
+
+&lpuart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+
+ imxrt1050-evk {
+ pinctrl_lpuart1: lpuart1grp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
+ 0xf1
+ MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
+ 0xf1
+ >;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
+ 0x1B000
+ MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
+ 0xB069
+ MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD
+ 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK
+ 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
+ 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
+ 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
+ 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
+ 0x17061
+ >;
+ };
+
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc0>;
+ pinctrl-1 = <&pinctrl_usdhc0>;
+ pinctrl-2 = <&pinctrl_usdhc0>;
+ pinctrl-3 = <&pinctrl_usdhc0>;
+ status = "okay";
+
+ cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/imxrt1050.dtsi
new file mode 100644
index 000000000000..cad5d0249fea
--- /dev/null
+++ b/arch/arm/boot/dts/imxrt1050.dtsi
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include "armv7-m.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/imxrt1050-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clocks {
+ osc: osc {
+ compatible = "fsl,imx-osc", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+ };
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ cpu@0 {
+ compatible = "arm,cortex-m7";
+ device_type = "cpu";
+ reg = <0x00>;
+ };
+ };
+
+ soc {
+
+ lpuart1: serial@40184000 {
+ compatible = "fsl,imxrt-lpuart","fsl,imx8mm-uart", "fsl,imx6q-uart";
+ reg = <0x40184000 0x4000>;
+ interrupts = <20>;
+ clocks = <&clks IMXRT1050_CLK_LPUART1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ iomuxc: iomuxc@401f8000 {
+ compatible = "fsl,imxrt1050-iomuxc";
+ reg = <0x401f8000 0x4000>;
+ fsl,mux_mask = <0x7>;
+ };
+
+ anatop: anatop@400d8000 {
+ compatible = "fsl,imxrt-anatop";
+ reg = <0x400d8000 0x4000>;
+ };
+
+ clks: ccm@400fc000 {
+ compatible = "fsl,imxrt1050-ccm";
+ reg = <0x400fc000 0x4000>;
+ interrupts = <95>,
+ <96>;
+ clocks = <&osc>;
+ clock-names = "osc";
+ #clock-cells = <1>;
+ assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
+ <&clks IMXRT1050_CLK_PLL1_BYPASS>,
+ <&clks IMXRT1050_CLK_PLL2_BYPASS>,
+ <&clks IMXRT1050_CLK_PLL3_BYPASS>,
+ <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
+ <&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
+ assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
+ <&clks IMXRT1050_CLK_PLL1_ARM>,
+ <&clks IMXRT1050_CLK_PLL2_SYS>,
+ <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
+ <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
+ <&clks IMXRT1050_CLK_PLL2_SYS>;
+ };
+
+ edma1: dma-controller@400e8000 {
+ #dma-cells = <2>;
+ compatible = "fsl,imx7ulp-edma";
+ reg = <0x400e8000 0x4000>,
+ <0x400ec000 0x4000>;
+ dma-channels = <32>;
+ interrupts = <0>,
+ <1>,
+ <2>,
+ <3>,
+ <4>,
+ <5>,
+ <6>,
+ <7>,
+ <8>,
+ <9>,
+ <10>,
+ <11>,
+ <12>,
+ <13>,
+ <14>,
+ <15>,
+ <16>;
+ clock-names = "dma", "dmamux0";
+ clocks = <&clks IMXRT1050_CLK_DMA>,
+ <&clks IMXRT1050_CLK_DMA_MUX>;
+ };
+
+ usdhc1: mmc@402c0000 {
+ compatible ="fsl,imxrt-usdhc";
+ reg = <0x402c0000 0x4000>;
+ interrupts = <110>;
+ clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
+ <&clks IMXRT1050_CLK_OSC>,
+ <&clks IMXRT1050_CLK_USDHC1>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ fsl,wp-controller;
+ no-1-8-v;
+ max-frequency = <4000000>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio@401b8000 {
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ reg = <0x401b8000 0x4000>;
+ interrupts = <80>,
+ <81>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@401bc000 {
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ reg = <0x401bc000 0x4000>;
+ interrupts = <82>,
+ <83>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@401c0000 {
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ reg = <0x401c0000 0x4000>;
+ interrupts = <84>,
+ <85>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@401c4000 {
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ reg = <0x401c4000 0x4000>;
+ interrupts = <86>,
+ <87>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio@400c0000 {
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ reg = <0x400c0000 0x4000>;
+ interrupts = <88>,
+ <89>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpt: timer@401ec000 {
+ compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
+ reg = <0x401ec000 0x4000>;
+ interrupts = <100>;
+ clocks = <&clks IMXRT1050_CLK_OSC>;
+ clock-names = "per";
+ };
+ };
+};
--
2.33.1
next prev parent reply other threads:[~2021-11-02 22:58 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-02 22:56 [PATCH v2 00/13] Add initial support for the i.MXRTxxxx SoC family starting from i.IMXRT1050 SoC Jesse Taube
2021-11-02 22:56 ` [PATCH v2 01/13] ARM: imx: add initial support for i.MXRT10xx family Jesse Taube
2021-11-02 22:56 ` [PATCH v2 02/13] dt-bindings: pinctrl: add i.MXRT1050 pinctrl binding doc Jesse Taube
2021-11-03 1:20 ` Rob Herring
2021-11-03 1:38 ` Jesse Taube
2021-11-09 1:07 ` Linus Walleij
2021-11-09 2:59 ` Jesse Taube
2021-11-02 22:56 ` [PATCH v2 03/13] ARM: dts: imxrt1050-pinfunc: Add pinctrl binding header Jesse Taube
2021-11-02 22:56 ` [PATCH v2 04/13] pinctrl: freescale: Add i.MXRT1050 pinctrl driver support Jesse Taube
2021-11-02 22:56 ` [PATCH v2 05/13] dt-bindings: clock: imx: Add documentation for i.MXRT clock Jesse Taube
2021-11-03 1:20 ` Rob Herring
2021-11-02 22:56 ` [PATCH v2 06/13] dt-bindings: imx: Add clock binding for i.MXRT1050 Jesse Taube
2021-11-02 22:56 ` [PATCH v2 07/13] clk: imx: Add initial support for i.MXRT clock driver Jesse Taube
2021-11-02 23:34 ` Fabio Estevam
2021-11-02 23:38 ` Jesse Taube
2021-11-05 9:42 ` Giulio Benetti
2021-11-02 22:56 ` [PATCH v2 08/13] dt-bindings: serial: fsl-lpuart: add i.MXRT compatible Jesse Taube
2021-11-02 22:56 ` [PATCH v2 09/13] tty: serial: fsl_lpuart: add i.MXRT support Jesse Taube
2021-11-02 22:56 ` [PATCH v2 10/13] dt-bindings: mmc: fsl-imx-esdhc: add i.MXRT compatible string Jesse Taube
2021-11-02 22:56 ` [PATCH v2 11/13] mmc: sdhci-esdhc-imx: Add sdhc support for i.MXRT series Jesse Taube
2021-11-02 23:02 ` Giulio Benetti
2021-11-02 23:17 ` Fabio Estevam
2021-11-02 23:25 ` Jesse Taube
2021-11-02 23:30 ` Giulio Benetti
2021-11-03 17:51 ` Fabio Estevam
2021-11-03 19:10 ` Giulio Benetti
[not found] ` <20211102233017.bvZyNHgwkuFX2SrymY1886iySuCFjH3IP1hlSc3HduY@z>
2021-11-04 1:05 ` Rob Herring
2021-11-04 2:30 ` Giulio Benetti
2021-11-03 2:19 ` Bough Chen
2021-11-23 3:13 ` Jesse Taube
2021-11-23 4:31 ` Bough Chen
2021-11-02 22:57 ` Jesse Taube [this message]
2021-11-02 23:42 ` [PATCH v2 12/13] ARM: dts: imx: add i.MXRT1050-EVK support Fabio Estevam
2021-11-02 23:54 ` Jesse Taube
2021-11-03 2:19 ` Jesse Taube
2021-11-02 22:57 ` [PATCH v2 13/13] ARM: imxrt_defconfig: add i.MXRT family defconfig Jesse Taube
[not found] ` <20211102225653.W9X4uTuBfjTBCe44PlQdYj5pRnczkEUmvmbnCVeKkeM@z>
2021-11-08 17:06 ` [PATCH v2 05/13] dt-bindings: clock: imx: Add documentation for i.MXRT clock Rob Herring
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