* [PATCH v8 0/7] Add pin control support for lpass sc7280
@ 2022-02-21 14:59 Srinivasa Rao Mandadapu
2022-02-21 14:59 ` [PATCH v8 1/7] dt-bindings: pinctrl: qcom: Update lpass lpi file name to SoC specific Srinivasa Rao Mandadapu
` (6 more replies)
0 siblings, 7 replies; 9+ messages in thread
From: Srinivasa Rao Mandadapu @ 2022-02-21 14:59 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, quic_plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao, Linus Walleij, linux-gpio
Cc: Srinivasa Rao Mandadapu
This patch series is to split lpass variant common pin control
functions and SoC specific functions and to add lpass sc7280 pincontrol support.
It also Adds dt-bindings for lpass sc7280 lpass lpi pincontrol.
Changes Since V7:
-- Update optional clock voting with conditional check.
-- Add const to lpi_pinctrl_variant_data structure.
-- Update required headers and remove redundant.
-- Change EXPORT_SYMBOL to EXPORT_SYMBOL_GPL
-- Fix typo errors.
Changes Since V6:
-- Update conditional clock voting to optional clock voting.
-- Update Kconfig depends on field with select.
-- Fix typo errors.
Changes Since V5:
-- Create new patch by updating macro name to lpi specific.
-- Create new patch by updating lpi pin group structure with core group_desc structure.
-- Fix typo errors.
-- Sort macros in the make file and configuration file.
Changes Since V4:
-- Update commit message and description of the chip specific extraction patch.
-- Sort macros in kconfig and makefile.
-- Update optional clock voting to conditional clock voting.
-- Fix typo errors.
-- Move to quicinc domain email id's.
Changes Since V3:
-- Update separate Kconfig fields for sm8250 and sc7280.
-- Update module license and description.
-- Move static variables to corresponding .c files from header file.
Changes Since V2:
-- Add new dt-bindings for sc7280 lpi driver.
-- Make clock voting change as separate patch.
-- Split existing pincontrol driver and make common functions
as part of separate file.
-- Rename lpass pincontrol lpi dt-bindings to sm8250 specific dt-bindings
Changes Since V1:
-- Make lpi pinctrl variant data structure as constant
-- Add appropriate commit message
-- Change signedoff by sequence.
Srinivasa Rao Mandadapu (7):
dt-bindings: pinctrl: qcom: Update lpass lpi file name to SoC specific
dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl bindings
pinctrl: qcom: Update macro name to LPI specific
pinctrl: qcom: Update lpi pin group structure
pinctrl: qcom: Extract chip specific LPASS LPI code
pinctrl: qcom: Add SC7280 lpass pin configuration
pinctrl: qcom: Update clock voting as optional
Tested this on SM8250 MTP with WSA and WCD codecs.
Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
.../bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 133 -----------
.../pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml | 115 ++++++++++
.../pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml | 133 +++++++++++
drivers/pinctrl/qcom/Kconfig | 16 ++
drivers/pinctrl/qcom/Makefile | 2 +
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 255 ++-------------------
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 86 +++++++
drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 169 ++++++++++++++
drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 166 ++++++++++++++
9 files changed, 705 insertions(+), 370 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
create mode 100644 drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
--
2.7.4
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v8 1/7] dt-bindings: pinctrl: qcom: Update lpass lpi file name to SoC specific
2022-02-21 14:59 [PATCH v8 0/7] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu
@ 2022-02-21 14:59 ` Srinivasa Rao Mandadapu
2022-02-21 14:59 ` [PATCH v8 2/7] dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl bindings Srinivasa Rao Mandadapu
` (5 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Srinivasa Rao Mandadapu @ 2022-02-21 14:59 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, quic_plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao, Linus Walleij, linux-gpio
Cc: Srinivasa Rao Mandadapu, Venkata Prasad Potturu
Change generic lpass lpi pincotrol bindings file to SoC specific file,
to distinguish and accomadate other SoC specific dt bindings.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
.../bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 133 ---------------------
.../pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml | 133 +++++++++++++++++++++
2 files changed, 133 insertions(+), 133 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
deleted file mode 100644
index 5c5542f..0000000
--- a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
+++ /dev/null
@@ -1,133 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
- Low Power Island (LPI) TLMM block
-
-maintainers:
- - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
-
-description: |
- This binding describes the Top Level Mode Multiplexer block found in the
- LPASS LPI IP on most Qualcomm SoCs
-
-properties:
- compatible:
- const: qcom,sm8250-lpass-lpi-pinctrl
-
- reg:
- minItems: 2
- maxItems: 2
-
- clocks:
- items:
- - description: LPASS Core voting clock
- - description: LPASS Audio voting clock
-
- clock-names:
- items:
- - const: core
- - const: audio
-
- gpio-controller: true
-
- '#gpio-cells':
- description: Specifying the pin number and flags, as defined in
- include/dt-bindings/gpio/gpio.h
- const: 2
-
- gpio-ranges:
- maxItems: 1
-
-#PIN CONFIGURATION NODES
-patternProperties:
- '-pins$':
- type: object
- description:
- Pinctrl node's client devices use subnodes for desired pin configuration.
- Client device subnodes use below standard properties.
- $ref: "/schemas/pinctrl/pincfg-node.yaml"
-
- properties:
- pins:
- description:
- List of gpio pins affected by the properties specified in this
- subnode.
- items:
- oneOf:
- - pattern: "^gpio([0-9]|[1-9][0-9])$"
- minItems: 1
- maxItems: 14
-
- function:
- enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
- qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
- dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
- i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
- dmic3_data, i2s2_data ]
- description:
- Specify the alternative function to be configured for the specified
- pins.
-
- drive-strength:
- enum: [2, 4, 6, 8, 10, 12, 14, 16]
- default: 2
- description:
- Selects the drive strength for the specified pins, in mA.
-
- slew-rate:
- enum: [0, 1, 2, 3]
- default: 0
- description: |
- 0: No adjustments
- 1: Higher Slew rate (faster edges)
- 2: Lower Slew rate (slower edges)
- 3: Reserved (No adjustments)
-
- bias-pull-down: true
-
- bias-pull-up: true
-
- bias-disable: true
-
- output-high: true
-
- output-low: true
-
- required:
- - pins
- - function
-
- additionalProperties: false
-
-allOf:
- - $ref: "pinctrl.yaml#"
-
-required:
- - compatible
- - reg
- - clocks
- - clock-names
- - gpio-controller
- - '#gpio-cells'
- - gpio-ranges
-
-additionalProperties: false
-
-examples:
- - |
- #include <dt-bindings/sound/qcom,q6afe.h>
- lpi_tlmm: pinctrl@33c0000 {
- compatible = "qcom,sm8250-lpass-lpi-pinctrl";
- reg = <0x33c0000 0x20000>,
- <0x3550000 0x10000>;
- clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
- <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- clock-names = "core", "audio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&lpi_tlmm 0 0 14>;
- };
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
new file mode 100644
index 0000000..06efb13
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
@@ -0,0 +1,133 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
+ Low Power Island (LPI) TLMM block
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ LPASS LPI IP on most Qualcomm SoCs
+
+properties:
+ compatible:
+ const: qcom,sm8250-lpass-lpi-pinctrl
+
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ clocks:
+ items:
+ - description: LPASS Core voting clock
+ - description: LPASS Audio voting clock
+
+ clock-names:
+ items:
+ - const: core
+ - const: audio
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9])$"
+ minItems: 1
+ maxItems: 14
+
+ function:
+ enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
+ qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
+ dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
+ i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
+ dmic3_data, i2s2_data ]
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+ Selects the drive strength for the specified pins, in mA.
+
+ slew-rate:
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ 0: No adjustments
+ 1: Higher Slew rate (faster edges)
+ 2: Lower Slew rate (slower edges)
+ 3: Reserved (No adjustments)
+
+ bias-pull-down: true
+
+ bias-pull-up: true
+
+ bias-disable: true
+
+ output-high: true
+
+ output-low: true
+
+ required:
+ - pins
+ - function
+
+ additionalProperties: false
+
+allOf:
+ - $ref: "pinctrl.yaml#"
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/sound/qcom,q6afe.h>
+ lpi_tlmm: pinctrl@33c0000 {
+ compatible = "qcom,sm8250-lpass-lpi-pinctrl";
+ reg = <0x33c0000 0x20000>,
+ <0x3550000 0x10000>;
+ clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "audio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpi_tlmm 0 0 14>;
+ };
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v8 2/7] dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl bindings
2022-02-21 14:59 [PATCH v8 0/7] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu
2022-02-21 14:59 ` [PATCH v8 1/7] dt-bindings: pinctrl: qcom: Update lpass lpi file name to SoC specific Srinivasa Rao Mandadapu
@ 2022-02-21 14:59 ` Srinivasa Rao Mandadapu
2022-02-21 14:59 ` [PATCH v8 3/7] pinctrl: qcom: Update macro name to LPI specific Srinivasa Rao Mandadapu
` (4 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Srinivasa Rao Mandadapu @ 2022-02-21 14:59 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, quic_plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao, Linus Walleij, linux-gpio
Cc: Srinivasa Rao Mandadapu, Venkata Prasad Potturu
Add device tree binding Documentation details for Qualcomm SC7280
LPASS LPI pinctrl driver.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
.../pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml | 115 +++++++++++++++++++++
1 file changed, 115 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
new file mode 100644
index 0000000..d32ee32
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
+ Low Power Island (LPI) TLMM block
+
+maintainers:
+ - Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ LPASS LPI IP on most Qualcomm SoCs
+
+properties:
+ compatible:
+ const: qcom,sc7280-lpass-lpi-pinctrl
+
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9])$"
+ minItems: 1
+ maxItems: 15
+
+ function:
+ enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
+ qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
+ dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
+ i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
+ dmic3_data, i2s2_data ]
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+ Selects the drive strength for the specified pins, in mA.
+
+ slew-rate:
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ 0: No adjustments
+ 1: Higher Slew rate (faster edges)
+ 2: Lower Slew rate (slower edges)
+ 3: Reserved (No adjustments)
+
+ bias-pull-down: true
+
+ bias-pull-up: true
+
+ bias-disable: true
+
+ output-high: true
+
+ output-low: true
+
+ required:
+ - pins
+ - function
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ lpass_tlmm: pinctrl@33c0000 {
+ compatible = "qcom,sc7280-lpass-lpi-pinctrl";
+ reg = <0x33c0000 0x20000>,
+ <0x3550000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 15>;
+ };
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v8 3/7] pinctrl: qcom: Update macro name to LPI specific
2022-02-21 14:59 [PATCH v8 0/7] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu
2022-02-21 14:59 ` [PATCH v8 1/7] dt-bindings: pinctrl: qcom: Update lpass lpi file name to SoC specific Srinivasa Rao Mandadapu
2022-02-21 14:59 ` [PATCH v8 2/7] dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl bindings Srinivasa Rao Mandadapu
@ 2022-02-21 14:59 ` Srinivasa Rao Mandadapu
2022-02-21 14:59 ` [PATCH v8 4/7] pinctrl: qcom: Update lpi pin group structure Srinivasa Rao Mandadapu
` (3 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Srinivasa Rao Mandadapu @ 2022-02-21 14:59 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, quic_plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao, Linus Walleij, linux-gpio
Cc: Srinivasa Rao Mandadapu, Venkata Prasad Potturu
Update NO_SLEW macro to LPI_NO_SLEW macro as this driver lpi specific.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
index 2f19ab4..3c15f80 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -40,7 +40,7 @@
#define LPI_GPIO_KEEPER 0x2
#define LPI_GPIO_PULL_UP 0x3
#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
-#define NO_SLEW -1
+#define LPI_NO_SLEW -1
#define LPI_FUNCTION(fname) \
[LPI_MUX_##fname] = { \
@@ -193,14 +193,14 @@ static const struct lpi_pingroup sm8250_groups[] = {
LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
- LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
- LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
- LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
- LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
+ LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _),
+ LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _),
+ LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _),
+ LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _),
LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
- LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
- LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
+ LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _),
+ LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _),
};
static const struct lpi_function sm8250_functions[] = {
@@ -435,7 +435,7 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
}
slew_offset = g->slew_offset;
- if (slew_offset == NO_SLEW)
+ if (slew_offset == LPI_NO_SLEW)
break;
mutex_lock(&pctrl->slew_access_lock);
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v8 4/7] pinctrl: qcom: Update lpi pin group structure
2022-02-21 14:59 [PATCH v8 0/7] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu
` (2 preceding siblings ...)
2022-02-21 14:59 ` [PATCH v8 3/7] pinctrl: qcom: Update macro name to LPI specific Srinivasa Rao Mandadapu
@ 2022-02-21 14:59 ` Srinivasa Rao Mandadapu
2022-02-21 14:59 ` [PATCH v8 5/7] pinctrl: qcom: Extract chip specific LPASS LPI code Srinivasa Rao Mandadapu
` (2 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Srinivasa Rao Mandadapu @ 2022-02-21 14:59 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, quic_plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao, Linus Walleij, linux-gpio
Cc: Srinivasa Rao Mandadapu, Venkata Prasad Potturu
Update lpi group structure with core group_desc structure
to avoid redundant struct params.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
---
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 44 +++++++++++++++-----------------
1 file changed, 21 insertions(+), 23 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
index 3c15f80..54750ba 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -51,11 +51,11 @@
#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
{ \
- .name = "gpio" #id, \
- .pins = gpio##id##_pins, \
+ .group.name = "gpio" #id, \
+ .group.pins = gpio##id##_pins, \
.pin = id, \
.slew_offset = soff, \
- .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .group.num_pins = ARRAY_SIZE(gpio##id##_pins), \
.funcs = (int[]){ \
LPI_MUX_gpio, \
LPI_MUX_##f1, \
@@ -67,9 +67,7 @@
}
struct lpi_pingroup {
- const char *name;
- const unsigned int *pins;
- unsigned int npins;
+ struct group_desc group;
unsigned int pin;
/* Bit offset in slew register for SoundWire pins only */
int slew_offset;
@@ -150,20 +148,20 @@ enum sm8250_lpi_functions {
LPI_MUX__,
};
-static const unsigned int gpio0_pins[] = { 0 };
-static const unsigned int gpio1_pins[] = { 1 };
-static const unsigned int gpio2_pins[] = { 2 };
-static const unsigned int gpio3_pins[] = { 3 };
-static const unsigned int gpio4_pins[] = { 4 };
-static const unsigned int gpio5_pins[] = { 5 };
-static const unsigned int gpio6_pins[] = { 6 };
-static const unsigned int gpio7_pins[] = { 7 };
-static const unsigned int gpio8_pins[] = { 8 };
-static const unsigned int gpio9_pins[] = { 9 };
-static const unsigned int gpio10_pins[] = { 10 };
-static const unsigned int gpio11_pins[] = { 11 };
-static const unsigned int gpio12_pins[] = { 12 };
-static const unsigned int gpio13_pins[] = { 13 };
+static int gpio0_pins[] = { 0 };
+static int gpio1_pins[] = { 1 };
+static int gpio2_pins[] = { 2 };
+static int gpio3_pins[] = { 3 };
+static int gpio4_pins[] = { 4 };
+static int gpio5_pins[] = { 5 };
+static int gpio6_pins[] = { 6 };
+static int gpio7_pins[] = { 7 };
+static int gpio8_pins[] = { 8 };
+static int gpio9_pins[] = { 9 };
+static int gpio10_pins[] = { 10 };
+static int gpio11_pins[] = { 11 };
+static int gpio12_pins[] = { 12 };
+static int gpio13_pins[] = { 13 };
static const char * const swr_tx_clk_groups[] = { "gpio0" };
static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
static const char * const swr_rx_clk_groups[] = { "gpio3" };
@@ -262,7 +260,7 @@ static const char *lpi_gpio_get_group_name(struct pinctrl_dev *pctldev,
{
struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
- return pctrl->data->groups[group].name;
+ return pctrl->data->groups[group].group.name;
}
static int lpi_gpio_get_group_pins(struct pinctrl_dev *pctldev,
@@ -272,8 +270,8 @@ static int lpi_gpio_get_group_pins(struct pinctrl_dev *pctldev,
{
struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
- *pins = pctrl->data->groups[group].pins;
- *num_pins = pctrl->data->groups[group].npins;
+ *pins = pctrl->data->groups[group].group.pins;
+ *num_pins = pctrl->data->groups[group].group.num_pins;
return 0;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v8 5/7] pinctrl: qcom: Extract chip specific LPASS LPI code
2022-02-21 14:59 [PATCH v8 0/7] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu
` (3 preceding siblings ...)
2022-02-21 14:59 ` [PATCH v8 4/7] pinctrl: qcom: Update lpi pin group structure Srinivasa Rao Mandadapu
@ 2022-02-21 14:59 ` Srinivasa Rao Mandadapu
2022-02-22 17:54 ` kernel test robot
2022-02-21 14:59 ` [PATCH v8 6/7] pinctrl: qcom: Add SC7280 lpass pin configuration Srinivasa Rao Mandadapu
2022-02-21 14:59 ` [PATCH v8 7/7] pinctrl: qcom: Update clock voting as optional Srinivasa Rao Mandadapu
6 siblings, 1 reply; 9+ messages in thread
From: Srinivasa Rao Mandadapu @ 2022-02-21 14:59 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, quic_plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao, Linus Walleij, linux-gpio
Cc: Srinivasa Rao Mandadapu, Venkata Prasad Potturu
Extract the chip specific SM8250 data from the LPASS LPI pinctrl driver
to allow reusing the common code in the addition of subsequent
platforms.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
---
drivers/pinctrl/qcom/Kconfig | 8 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 233 +-----------------------
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 85 +++++++++
drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 166 +++++++++++++++++
5 files changed, 265 insertions(+), 228 deletions(-)
create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index ca6f68a..dc6716e 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -329,6 +329,14 @@ config PINCTRL_SM8250
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8250 platform.
+config PINCTRL_SM8250_LPASS_LPI
+ tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
+ select PINCTRL_LPASS_LPI
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.
+
config PINCTRL_SM8350
tristate "Qualcomm Technologies Inc SM8350 pin controller driver"
depends on PINCTRL_MSM
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 709882f..39650d6 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_PINCTRL_SM6350) += pinctrl-sm6350.o
obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
+obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o
obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o
obj-$(CONFIG_PINCTRL_SM8450) += pinctrl-sm8450.o
obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
index 54750ba..1ab572f 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -4,91 +4,15 @@
* Copyright (c) 2020 Linaro Ltd.
*/
-#include <linux/bitops.h>
-#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/gpio/driver.h>
-#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
-#include <linux/of.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinmux.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/types.h>
-#include "../core.h"
#include "../pinctrl-utils.h"
-
-#define LPI_SLEW_RATE_CTL_REG 0xa000
-#define LPI_TLMM_REG_OFFSET 0x1000
-#define LPI_SLEW_RATE_MAX 0x03
-#define LPI_SLEW_BITS_SIZE 0x02
-#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
-#define LPI_GPIO_CFG_REG 0x00
-#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
-#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
-#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
-#define LPI_GPIO_OE_MASK BIT(9)
-#define LPI_GPIO_VALUE_REG 0x04
-#define LPI_GPIO_VALUE_IN_MASK BIT(0)
-#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
-
-#define LPI_GPIO_BIAS_DISABLE 0x0
-#define LPI_GPIO_PULL_DOWN 0x1
-#define LPI_GPIO_KEEPER 0x2
-#define LPI_GPIO_PULL_UP 0x3
-#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
-#define LPI_NO_SLEW -1
-
-#define LPI_FUNCTION(fname) \
- [LPI_MUX_##fname] = { \
- .name = #fname, \
- .groups = fname##_groups, \
- .ngroups = ARRAY_SIZE(fname##_groups), \
- }
-
-#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
- { \
- .group.name = "gpio" #id, \
- .group.pins = gpio##id##_pins, \
- .pin = id, \
- .slew_offset = soff, \
- .group.num_pins = ARRAY_SIZE(gpio##id##_pins), \
- .funcs = (int[]){ \
- LPI_MUX_gpio, \
- LPI_MUX_##f1, \
- LPI_MUX_##f2, \
- LPI_MUX_##f3, \
- LPI_MUX_##f4, \
- }, \
- .nfuncs = 5, \
- }
-
-struct lpi_pingroup {
- struct group_desc group;
- unsigned int pin;
- /* Bit offset in slew register for SoundWire pins only */
- int slew_offset;
- unsigned int *funcs;
- unsigned int nfuncs;
-};
-
-struct lpi_function {
- const char *name;
- const char * const *groups;
- unsigned int ngroups;
-};
-
-struct lpi_pinctrl_variant_data {
- const struct pinctrl_pin_desc *pins;
- int npins;
- const struct lpi_pingroup *groups;
- int ngroups;
- const struct lpi_function *functions;
- int nfunctions;
-};
+#include "pinctrl-lpass-lpi.h"
#define MAX_LPI_NUM_CLKS 2
@@ -104,136 +28,6 @@ struct lpi_pinctrl {
const struct lpi_pinctrl_variant_data *data;
};
-/* sm8250 variant specific data */
-static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
- PINCTRL_PIN(0, "gpio0"),
- PINCTRL_PIN(1, "gpio1"),
- PINCTRL_PIN(2, "gpio2"),
- PINCTRL_PIN(3, "gpio3"),
- PINCTRL_PIN(4, "gpio4"),
- PINCTRL_PIN(5, "gpio5"),
- PINCTRL_PIN(6, "gpio6"),
- PINCTRL_PIN(7, "gpio7"),
- PINCTRL_PIN(8, "gpio8"),
- PINCTRL_PIN(9, "gpio9"),
- PINCTRL_PIN(10, "gpio10"),
- PINCTRL_PIN(11, "gpio11"),
- PINCTRL_PIN(12, "gpio12"),
- PINCTRL_PIN(13, "gpio13"),
-};
-
-enum sm8250_lpi_functions {
- LPI_MUX_dmic1_clk,
- LPI_MUX_dmic1_data,
- LPI_MUX_dmic2_clk,
- LPI_MUX_dmic2_data,
- LPI_MUX_dmic3_clk,
- LPI_MUX_dmic3_data,
- LPI_MUX_i2s1_clk,
- LPI_MUX_i2s1_data,
- LPI_MUX_i2s1_ws,
- LPI_MUX_i2s2_clk,
- LPI_MUX_i2s2_data,
- LPI_MUX_i2s2_ws,
- LPI_MUX_qua_mi2s_data,
- LPI_MUX_qua_mi2s_sclk,
- LPI_MUX_qua_mi2s_ws,
- LPI_MUX_swr_rx_clk,
- LPI_MUX_swr_rx_data,
- LPI_MUX_swr_tx_clk,
- LPI_MUX_swr_tx_data,
- LPI_MUX_wsa_swr_clk,
- LPI_MUX_wsa_swr_data,
- LPI_MUX_gpio,
- LPI_MUX__,
-};
-
-static int gpio0_pins[] = { 0 };
-static int gpio1_pins[] = { 1 };
-static int gpio2_pins[] = { 2 };
-static int gpio3_pins[] = { 3 };
-static int gpio4_pins[] = { 4 };
-static int gpio5_pins[] = { 5 };
-static int gpio6_pins[] = { 6 };
-static int gpio7_pins[] = { 7 };
-static int gpio8_pins[] = { 8 };
-static int gpio9_pins[] = { 9 };
-static int gpio10_pins[] = { 10 };
-static int gpio11_pins[] = { 11 };
-static int gpio12_pins[] = { 12 };
-static int gpio13_pins[] = { 13 };
-static const char * const swr_tx_clk_groups[] = { "gpio0" };
-static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
-static const char * const swr_rx_clk_groups[] = { "gpio3" };
-static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
-static const char * const dmic1_clk_groups[] = { "gpio6" };
-static const char * const dmic1_data_groups[] = { "gpio7" };
-static const char * const dmic2_clk_groups[] = { "gpio8" };
-static const char * const dmic2_data_groups[] = { "gpio9" };
-static const char * const i2s2_clk_groups[] = { "gpio10" };
-static const char * const i2s2_ws_groups[] = { "gpio11" };
-static const char * const dmic3_clk_groups[] = { "gpio12" };
-static const char * const dmic3_data_groups[] = { "gpio13" };
-static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
-static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
-static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
-static const char * const i2s1_clk_groups[] = { "gpio6" };
-static const char * const i2s1_ws_groups[] = { "gpio7" };
-static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
-static const char * const wsa_swr_clk_groups[] = { "gpio10" };
-static const char * const wsa_swr_data_groups[] = { "gpio11" };
-static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
-
-static const struct lpi_pingroup sm8250_groups[] = {
- LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
- LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
- LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
- LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
- LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
- LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
- LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _),
- LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _),
- LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _),
- LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _),
- LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
- LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
- LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _),
- LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _),
-};
-
-static const struct lpi_function sm8250_functions[] = {
- LPI_FUNCTION(dmic1_clk),
- LPI_FUNCTION(dmic1_data),
- LPI_FUNCTION(dmic2_clk),
- LPI_FUNCTION(dmic2_data),
- LPI_FUNCTION(dmic3_clk),
- LPI_FUNCTION(dmic3_data),
- LPI_FUNCTION(i2s1_clk),
- LPI_FUNCTION(i2s1_data),
- LPI_FUNCTION(i2s1_ws),
- LPI_FUNCTION(i2s2_clk),
- LPI_FUNCTION(i2s2_data),
- LPI_FUNCTION(i2s2_ws),
- LPI_FUNCTION(qua_mi2s_data),
- LPI_FUNCTION(qua_mi2s_sclk),
- LPI_FUNCTION(qua_mi2s_ws),
- LPI_FUNCTION(swr_rx_clk),
- LPI_FUNCTION(swr_rx_data),
- LPI_FUNCTION(swr_tx_clk),
- LPI_FUNCTION(swr_tx_data),
- LPI_FUNCTION(wsa_swr_clk),
- LPI_FUNCTION(wsa_swr_data),
-};
-
-static struct lpi_pinctrl_variant_data sm8250_lpi_data = {
- .pins = sm8250_lpi_pins,
- .npins = ARRAY_SIZE(sm8250_lpi_pins),
- .groups = sm8250_groups,
- .ngroups = ARRAY_SIZE(sm8250_groups),
- .functions = sm8250_functions,
- .nfunctions = ARRAY_SIZE(sm8250_functions),
-};
-
static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
unsigned int addr)
{
@@ -580,7 +374,7 @@ static const struct gpio_chip lpi_gpio_template = {
.dbg_show = lpi_gpio_dbg_show,
};
-static int lpi_pinctrl_probe(struct platform_device *pdev)
+int lpi_pinctrl_probe(struct platform_device *pdev)
{
const struct lpi_pinctrl_variant_data *data;
struct device *dev = &pdev->dev;
@@ -659,8 +453,9 @@ static int lpi_pinctrl_probe(struct platform_device *pdev)
return ret;
}
+EXPORT_SYMBOL_GPL(lpi_pinctrl_probe);
-static int lpi_pinctrl_remove(struct platform_device *pdev)
+int lpi_pinctrl_remove(struct platform_device *pdev)
{
struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
@@ -669,25 +464,7 @@ static int lpi_pinctrl_remove(struct platform_device *pdev)
return 0;
}
+EXPORT_SYMBOL_GPL(lpi_pinctrl_remove);
-static const struct of_device_id lpi_pinctrl_of_match[] = {
- {
- .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
- .data = &sm8250_lpi_data,
- },
- { }
-};
-MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
-
-static struct platform_driver lpi_pinctrl_driver = {
- .driver = {
- .name = "qcom-lpass-lpi-pinctrl",
- .of_match_table = lpi_pinctrl_of_match,
- },
- .probe = lpi_pinctrl_probe,
- .remove = lpi_pinctrl_remove,
-};
-
-module_platform_driver(lpi_pinctrl_driver);
MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
new file mode 100644
index 0000000..afbac2a
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020 Linaro Ltd.
+ */
+#ifndef __PINCTRL_LPASS_LPI_H__
+#define __PINCTRL_LPASS_LPI_H__
+
+#include <linux/bitops.h>
+#include <linux/bitfield.h>
+#include "../core.h"
+
+#define LPI_SLEW_RATE_CTL_REG 0xa000
+#define LPI_TLMM_REG_OFFSET 0x1000
+#define LPI_SLEW_RATE_MAX 0x03
+#define LPI_SLEW_BITS_SIZE 0x02
+#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
+#define LPI_GPIO_CFG_REG 0x00
+#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
+#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
+#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
+#define LPI_GPIO_OE_MASK BIT(9)
+#define LPI_GPIO_VALUE_REG 0x04
+#define LPI_GPIO_VALUE_IN_MASK BIT(0)
+#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
+
+#define LPI_GPIO_BIAS_DISABLE 0x0
+#define LPI_GPIO_PULL_DOWN 0x1
+#define LPI_GPIO_KEEPER 0x2
+#define LPI_GPIO_PULL_UP 0x3
+#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
+#define LPI_NO_SLEW -1
+
+#define LPI_FUNCTION(fname) \
+ [LPI_MUX_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
+ { \
+ .group.name = "gpio" #id, \
+ .group.pins = gpio##id##_pins, \
+ .pin = id, \
+ .slew_offset = soff, \
+ .group.num_pins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ LPI_MUX_gpio, \
+ LPI_MUX_##f1, \
+ LPI_MUX_##f2, \
+ LPI_MUX_##f3, \
+ LPI_MUX_##f4, \
+ }, \
+ .nfuncs = 5, \
+ }
+
+struct lpi_pingroup {
+ struct group_desc group;
+ unsigned int pin;
+ /* Bit offset in slew register for SoundWire pins only */
+ int slew_offset;
+ unsigned int *funcs;
+ unsigned int nfuncs;
+};
+
+struct lpi_function {
+ const char *name;
+ const char * const *groups;
+ unsigned int ngroups;
+};
+
+struct lpi_pinctrl_variant_data {
+ const struct pinctrl_pin_desc *pins;
+ int npins;
+ const struct lpi_pingroup *groups;
+ int ngroups;
+ const struct lpi_function *functions;
+ int nfunctions;
+};
+
+int lpi_pinctrl_probe(struct platform_device *pdev);
+int lpi_pinctrl_remove(struct platform_device *pdev);
+
+#endif /*__PINCTRL_LPASS_LPI_H__*/
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
new file mode 100644
index 0000000..33342f3
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020 Linaro Ltd.
+ */
+
+#include <linux/gpio/driver.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-lpass-lpi.h"
+#include "../core.h"
+
+enum lpass_lpi_functions {
+ LPI_MUX_dmic1_clk,
+ LPI_MUX_dmic1_data,
+ LPI_MUX_dmic2_clk,
+ LPI_MUX_dmic2_data,
+ LPI_MUX_dmic3_clk,
+ LPI_MUX_dmic3_data,
+ LPI_MUX_i2s1_clk,
+ LPI_MUX_i2s1_data,
+ LPI_MUX_i2s1_ws,
+ LPI_MUX_i2s2_clk,
+ LPI_MUX_i2s2_data,
+ LPI_MUX_i2s2_ws,
+ LPI_MUX_qua_mi2s_data,
+ LPI_MUX_qua_mi2s_sclk,
+ LPI_MUX_qua_mi2s_ws,
+ LPI_MUX_swr_rx_clk,
+ LPI_MUX_swr_rx_data,
+ LPI_MUX_swr_tx_clk,
+ LPI_MUX_swr_tx_data,
+ LPI_MUX_wsa_swr_clk,
+ LPI_MUX_wsa_swr_data,
+ LPI_MUX_gpio,
+ LPI_MUX__,
+};
+
+static int gpio0_pins[] = { 0 };
+static int gpio1_pins[] = { 1 };
+static int gpio2_pins[] = { 2 };
+static int gpio3_pins[] = { 3 };
+static int gpio4_pins[] = { 4 };
+static int gpio5_pins[] = { 5 };
+static int gpio6_pins[] = { 6 };
+static int gpio7_pins[] = { 7 };
+static int gpio8_pins[] = { 8 };
+static int gpio9_pins[] = { 9 };
+static int gpio10_pins[] = { 10 };
+static int gpio11_pins[] = { 11 };
+static int gpio12_pins[] = { 12 };
+static int gpio13_pins[] = { 13 };
+
+
+/* sm8250 variant specific data */
+static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
+ PINCTRL_PIN(0, "gpio0"),
+ PINCTRL_PIN(1, "gpio1"),
+ PINCTRL_PIN(2, "gpio2"),
+ PINCTRL_PIN(3, "gpio3"),
+ PINCTRL_PIN(4, "gpio4"),
+ PINCTRL_PIN(5, "gpio5"),
+ PINCTRL_PIN(6, "gpio6"),
+ PINCTRL_PIN(7, "gpio7"),
+ PINCTRL_PIN(8, "gpio8"),
+ PINCTRL_PIN(9, "gpio9"),
+ PINCTRL_PIN(10, "gpio10"),
+ PINCTRL_PIN(11, "gpio11"),
+ PINCTRL_PIN(12, "gpio12"),
+ PINCTRL_PIN(13, "gpio13"),
+};
+
+static const char * const swr_tx_clk_groups[] = { "gpio0" };
+static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
+static const char * const swr_rx_clk_groups[] = { "gpio3" };
+static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
+static const char * const dmic1_clk_groups[] = { "gpio6" };
+static const char * const dmic1_data_groups[] = { "gpio7" };
+static const char * const dmic2_clk_groups[] = { "gpio8" };
+static const char * const dmic2_data_groups[] = { "gpio9" };
+static const char * const i2s2_clk_groups[] = { "gpio10" };
+static const char * const i2s2_ws_groups[] = { "gpio11" };
+static const char * const dmic3_clk_groups[] = { "gpio12" };
+static const char * const dmic3_data_groups[] = { "gpio13" };
+static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
+static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
+static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
+static const char * const i2s1_clk_groups[] = { "gpio6" };
+static const char * const i2s1_ws_groups[] = { "gpio7" };
+static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
+static const char * const wsa_swr_clk_groups[] = { "gpio10" };
+static const char * const wsa_swr_data_groups[] = { "gpio11" };
+static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
+
+static const struct lpi_pingroup sm8250_groups[] = {
+ LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
+ LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
+ LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
+ LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
+ LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
+ LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
+ LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _),
+ LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _),
+ LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _),
+ LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _),
+ LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
+ LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
+ LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _),
+ LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _),
+};
+
+static const struct lpi_function sm8250_functions[] = {
+ LPI_FUNCTION(dmic1_clk),
+ LPI_FUNCTION(dmic1_data),
+ LPI_FUNCTION(dmic2_clk),
+ LPI_FUNCTION(dmic2_data),
+ LPI_FUNCTION(dmic3_clk),
+ LPI_FUNCTION(dmic3_data),
+ LPI_FUNCTION(i2s1_clk),
+ LPI_FUNCTION(i2s1_data),
+ LPI_FUNCTION(i2s1_ws),
+ LPI_FUNCTION(i2s2_clk),
+ LPI_FUNCTION(i2s2_data),
+ LPI_FUNCTION(i2s2_ws),
+ LPI_FUNCTION(qua_mi2s_data),
+ LPI_FUNCTION(qua_mi2s_sclk),
+ LPI_FUNCTION(qua_mi2s_ws),
+ LPI_FUNCTION(swr_rx_clk),
+ LPI_FUNCTION(swr_rx_data),
+ LPI_FUNCTION(swr_tx_clk),
+ LPI_FUNCTION(swr_tx_data),
+ LPI_FUNCTION(wsa_swr_clk),
+ LPI_FUNCTION(wsa_swr_data),
+};
+
+static const struct lpi_pinctrl_variant_data sm8250_lpi_data = {
+ .pins = sm8250_lpi_pins,
+ .npins = ARRAY_SIZE(sm8250_lpi_pins),
+ .groups = sm8250_groups,
+ .ngroups = ARRAY_SIZE(sm8250_groups),
+ .functions = sm8250_functions,
+ .nfunctions = ARRAY_SIZE(sm8250_functions),
+};
+
+static const struct of_device_id lpi_pinctrl_of_match[] = {
+ {
+ .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
+ .data = &sm8250_lpi_data,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
+
+static struct platform_driver lpi_pinctrl_driver = {
+ .driver = {
+ .name = "qcom-sm8250-lpass-lpi-pinctrl",
+ .of_match_table = lpi_pinctrl_of_match,
+ },
+ .probe = lpi_pinctrl_probe,
+ .remove = lpi_pinctrl_remove,
+};
+
+module_platform_driver(lpi_pinctrl_driver);
+MODULE_DESCRIPTION("QTI SM8250 LPI GPIO pin control driver");
+MODULE_LICENSE("GPL");
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v8 6/7] pinctrl: qcom: Add SC7280 lpass pin configuration
2022-02-21 14:59 [PATCH v8 0/7] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu
` (4 preceding siblings ...)
2022-02-21 14:59 ` [PATCH v8 5/7] pinctrl: qcom: Extract chip specific LPASS LPI code Srinivasa Rao Mandadapu
@ 2022-02-21 14:59 ` Srinivasa Rao Mandadapu
2022-02-21 14:59 ` [PATCH v8 7/7] pinctrl: qcom: Update clock voting as optional Srinivasa Rao Mandadapu
6 siblings, 0 replies; 9+ messages in thread
From: Srinivasa Rao Mandadapu @ 2022-02-21 14:59 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, quic_plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao, Linus Walleij, linux-gpio
Cc: Srinivasa Rao Mandadapu, Venkata Prasad Potturu
Add pin control support for SC7280 LPASS LPI.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
---
drivers/pinctrl/qcom/Kconfig | 8 ++
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 168 ++++++++++++++++++++++++
3 files changed, 177 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index dc6716e..6e92202 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -239,6 +239,14 @@ config PINCTRL_SC7280
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SC7280 platform.
+config PINCTRL_SC7280_LPASS_LPI
+ tristate "Qualcomm Technologies Inc SC7280 LPASS LPI pin controller driver"
+ select PINCTRL_LPASS_LPI
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform.
+
config PINCTRL_SC8180X
tristate "Qualcomm Technologies Inc SC8180x pin controller driver"
depends on (OF || ACPI)
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 39650d6..573e741 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o
obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o
+obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o
obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o
obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
new file mode 100644
index 0000000..3aa4dd38
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * ALSA SoC platform-machine driver for QTi LPASS
+ */
+
+#include <linux/gpio/driver.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-lpass-lpi.h"
+#include "../core.h"
+
+enum lpass_lpi_functions {
+ LPI_MUX_dmic1_clk,
+ LPI_MUX_dmic1_data,
+ LPI_MUX_dmic2_clk,
+ LPI_MUX_dmic2_data,
+ LPI_MUX_dmic3_clk,
+ LPI_MUX_dmic3_data,
+ LPI_MUX_i2s1_clk,
+ LPI_MUX_i2s1_data,
+ LPI_MUX_i2s1_ws,
+ LPI_MUX_i2s2_clk,
+ LPI_MUX_i2s2_data,
+ LPI_MUX_i2s2_ws,
+ LPI_MUX_qua_mi2s_data,
+ LPI_MUX_qua_mi2s_sclk,
+ LPI_MUX_qua_mi2s_ws,
+ LPI_MUX_swr_rx_clk,
+ LPI_MUX_swr_rx_data,
+ LPI_MUX_swr_tx_clk,
+ LPI_MUX_swr_tx_data,
+ LPI_MUX_wsa_swr_clk,
+ LPI_MUX_wsa_swr_data,
+ LPI_MUX_gpio,
+ LPI_MUX__,
+};
+
+static int gpio0_pins[] = { 0 };
+static int gpio1_pins[] = { 1 };
+static int gpio2_pins[] = { 2 };
+static int gpio3_pins[] = { 3 };
+static int gpio4_pins[] = { 4 };
+static int gpio5_pins[] = { 5 };
+static int gpio6_pins[] = { 6 };
+static int gpio7_pins[] = { 7 };
+static int gpio8_pins[] = { 8 };
+static int gpio9_pins[] = { 9 };
+static int gpio10_pins[] = { 10 };
+static int gpio11_pins[] = { 11 };
+static int gpio12_pins[] = { 12 };
+static int gpio13_pins[] = { 13 };
+static int gpio14_pins[] = { 14 };
+
+/* sc7280 variant specific data */
+static const struct pinctrl_pin_desc sc7280_lpi_pins[] = {
+ PINCTRL_PIN(0, "gpio0"),
+ PINCTRL_PIN(1, "gpio1"),
+ PINCTRL_PIN(2, "gpio2"),
+ PINCTRL_PIN(3, "gpio3"),
+ PINCTRL_PIN(4, "gpio4"),
+ PINCTRL_PIN(5, "gpio5"),
+ PINCTRL_PIN(6, "gpio6"),
+ PINCTRL_PIN(7, "gpio7"),
+ PINCTRL_PIN(8, "gpio8"),
+ PINCTRL_PIN(9, "gpio9"),
+ PINCTRL_PIN(10, "gpio10"),
+ PINCTRL_PIN(11, "gpio11"),
+ PINCTRL_PIN(12, "gpio12"),
+ PINCTRL_PIN(13, "gpio13"),
+ PINCTRL_PIN(14, "gpio14"),
+};
+
+static const char * const swr_tx_clk_groups[] = { "gpio0" };
+static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" };
+static const char * const swr_rx_clk_groups[] = { "gpio3" };
+static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
+static const char * const dmic1_clk_groups[] = { "gpio6" };
+static const char * const dmic1_data_groups[] = { "gpio7" };
+static const char * const dmic2_clk_groups[] = { "gpio8" };
+static const char * const dmic2_data_groups[] = { "gpio9" };
+static const char * const i2s2_clk_groups[] = { "gpio10" };
+static const char * const i2s2_ws_groups[] = { "gpio11" };
+static const char * const dmic3_clk_groups[] = { "gpio12" };
+static const char * const dmic3_data_groups[] = { "gpio13" };
+static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
+static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
+static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
+static const char * const i2s1_clk_groups[] = { "gpio6" };
+static const char * const i2s1_ws_groups[] = { "gpio7" };
+static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
+static const char * const wsa_swr_clk_groups[] = { "gpio10" };
+static const char * const wsa_swr_data_groups[] = { "gpio11" };
+static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" };
+
+static const struct lpi_pingroup sc7280_groups[] = {
+ LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
+ LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
+ LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
+ LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
+ LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
+ LPI_PINGROUP(5, 12, swr_rx_data, _, _, _),
+ LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _),
+ LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _),
+ LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _),
+ LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _),
+ LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
+ LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
+ LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _),
+ LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _),
+ LPI_PINGROUP(14, 6, swr_tx_data, _, _, _),
+};
+
+static const struct lpi_function sc7280_functions[] = {
+ LPI_FUNCTION(dmic1_clk),
+ LPI_FUNCTION(dmic1_data),
+ LPI_FUNCTION(dmic2_clk),
+ LPI_FUNCTION(dmic2_data),
+ LPI_FUNCTION(dmic3_clk),
+ LPI_FUNCTION(dmic3_data),
+ LPI_FUNCTION(i2s1_clk),
+ LPI_FUNCTION(i2s1_data),
+ LPI_FUNCTION(i2s1_ws),
+ LPI_FUNCTION(i2s2_clk),
+ LPI_FUNCTION(i2s2_data),
+ LPI_FUNCTION(i2s2_ws),
+ LPI_FUNCTION(qua_mi2s_data),
+ LPI_FUNCTION(qua_mi2s_sclk),
+ LPI_FUNCTION(qua_mi2s_ws),
+ LPI_FUNCTION(swr_rx_clk),
+ LPI_FUNCTION(swr_rx_data),
+ LPI_FUNCTION(swr_tx_clk),
+ LPI_FUNCTION(swr_tx_data),
+ LPI_FUNCTION(wsa_swr_clk),
+ LPI_FUNCTION(wsa_swr_data),
+};
+
+static const struct lpi_pinctrl_variant_data sc7280_lpi_data = {
+ .pins = sc7280_lpi_pins,
+ .npins = ARRAY_SIZE(sc7280_lpi_pins),
+ .groups = sc7280_groups,
+ .ngroups = ARRAY_SIZE(sc7280_groups),
+ .functions = sc7280_functions,
+ .nfunctions = ARRAY_SIZE(sc7280_functions),
+};
+
+static const struct of_device_id lpi_pinctrl_of_match[] = {
+ {
+ .compatible = "qcom,sc7280-lpass-lpi-pinctrl",
+ .data = &sc7280_lpi_data,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
+
+static struct platform_driver lpi_pinctrl_driver = {
+ .driver = {
+ .name = "qcom-sc7280-lpass-lpi-pinctrl",
+ .of_match_table = lpi_pinctrl_of_match,
+ },
+ .probe = lpi_pinctrl_probe,
+ .remove = lpi_pinctrl_remove,
+};
+
+module_platform_driver(lpi_pinctrl_driver);
+MODULE_DESCRIPTION("QTI SC7280 LPI GPIO pin control driver");
+MODULE_LICENSE("GPL");
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v8 7/7] pinctrl: qcom: Update clock voting as optional
2022-02-21 14:59 [PATCH v8 0/7] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu
` (5 preceding siblings ...)
2022-02-21 14:59 ` [PATCH v8 6/7] pinctrl: qcom: Add SC7280 lpass pin configuration Srinivasa Rao Mandadapu
@ 2022-02-21 14:59 ` Srinivasa Rao Mandadapu
6 siblings, 0 replies; 9+ messages in thread
From: Srinivasa Rao Mandadapu @ 2022-02-21 14:59 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, quic_plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao, Linus Walleij, linux-gpio
Cc: Srinivasa Rao Mandadapu, Venkata Prasad Potturu
Update bulk clock voting to optional voting as ADSP bypass platform doesn't
need macro and decodec clocks, these are maintained as power domains and
operated from lpass audio core cc.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
---
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 12 +++++++++---
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 1 +
drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 1 +
3 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
index 1ab572f..c618b74 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -407,9 +407,15 @@ int lpi_pinctrl_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
"Slew resource not provided\n");
- ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
- if (ret)
- return dev_err_probe(dev, ret, "Can't get clocks\n");
+ if (data->is_clk_optional) {
+ ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
+ if (ret)
+ return dev_err_probe(dev, ret, "Can't get clocks\n");
+ } else {
+ ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
+ if (ret)
+ return dev_err_probe(dev, ret, "Can't get clocks\n");
+ }
ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks);
if (ret)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
index afbac2a..3bcede6 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
@@ -77,6 +77,7 @@ struct lpi_pinctrl_variant_data {
int ngroups;
const struct lpi_function *functions;
int nfunctions;
+ int is_clk_optional;
};
int lpi_pinctrl_probe(struct platform_device *pdev);
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
index 3aa4dd38..7332c31 100644
--- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
@@ -143,6 +143,7 @@ static const struct lpi_pinctrl_variant_data sc7280_lpi_data = {
.ngroups = ARRAY_SIZE(sc7280_groups),
.functions = sc7280_functions,
.nfunctions = ARRAY_SIZE(sc7280_functions),
+ .is_clk_optional = 1,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v8 5/7] pinctrl: qcom: Extract chip specific LPASS LPI code
2022-02-21 14:59 ` [PATCH v8 5/7] pinctrl: qcom: Extract chip specific LPASS LPI code Srinivasa Rao Mandadapu
@ 2022-02-22 17:54 ` kernel test robot
0 siblings, 0 replies; 9+ messages in thread
From: kernel test robot @ 2022-02-22 17:54 UTC (permalink / raw)
To: Srinivasa Rao Mandadapu, agross, bjorn.andersson, lgirdwood,
broonie, robh+dt, quic_plai, bgoswami, perex, tiwai,
srinivas.kandagatla, rohitkr, linux-arm-msm, alsa-devel,
devicetree, linux-kernel, swboyd, judyhsiao, Linus Walleij,
linux-gpio
Cc: kbuild-all, Srinivasa Rao Mandadapu, Venkata Prasad Potturu
Hi Srinivasa,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on linusw-pinctrl/devel]
[also build test ERROR on v5.17-rc5 next-20220217]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Srinivasa-Rao-Mandadapu/Add-pin-control-support-for-lpass-sc7280/20220221-230159
base: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git devel
config: arm-allmodconfig (https://download.01.org/0day-ci/archive/20220223/202202230101.Hp9mOcMc-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/c6ece609364ddb2a9488aa461bfb3d082171241a
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Srinivasa-Rao-Mandadapu/Add-pin-control-support-for-lpass-sc7280/20220221-230159
git checkout c6ece609364ddb2a9488aa461bfb3d082171241a
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm SHELL=/bin/bash drivers/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:42:8: error: redefinition of 'struct pinctrl_dev'
42 | struct pinctrl_dev {
| ^~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:42:8: note: originally defined here
42 | struct pinctrl_dev {
| ^~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:77:8: error: redefinition of 'struct pinctrl'
77 | struct pinctrl {
| ^~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:77:8: note: originally defined here
77 | struct pinctrl {
| ^~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:92:8: error: redefinition of 'struct pinctrl_state'
92 | struct pinctrl_state {
| ^~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:92:8: note: originally defined here
92 | struct pinctrl_state {
| ^~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:103:8: error: redefinition of 'struct pinctrl_setting_mux'
103 | struct pinctrl_setting_mux {
| ^~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:103:8: note: originally defined here
103 | struct pinctrl_setting_mux {
| ^~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:116:8: error: redefinition of 'struct pinctrl_setting_configs'
116 | struct pinctrl_setting_configs {
| ^~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:116:8: note: originally defined here
116 | struct pinctrl_setting_configs {
| ^~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:131:8: error: redefinition of 'struct pinctrl_setting'
131 | struct pinctrl_setting {
| ^~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:131:8: note: originally defined here
131 | struct pinctrl_setting {
| ^~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:159:8: error: redefinition of 'struct pin_desc'
159 | struct pin_desc {
| ^~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:159:8: note: originally defined here
159 | struct pin_desc {
| ^~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:179:8: error: redefinition of 'struct pinctrl_maps'
179 | struct pinctrl_maps {
| ^~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:179:8: note: originally defined here
179 | struct pinctrl_maps {
| ^~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:194:8: error: redefinition of 'struct group_desc'
194 | struct group_desc {
| ^~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:194:8: note: originally defined here
194 | struct group_desc {
| ^~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:201:5: error: conflicting types for 'pinctrl_generic_get_group_count'; have 'int(struct pinctrl_dev *)'
201 | int pinctrl_generic_get_group_count(struct pinctrl_dev *pctldev);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:201:5: note: previous declaration of 'pinctrl_generic_get_group_count' with type 'int(struct pinctrl_dev *)'
201 | int pinctrl_generic_get_group_count(struct pinctrl_dev *pctldev);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:203:13: error: conflicting types for 'pinctrl_generic_get_group_name'; have 'const char *(struct pinctrl_dev *, unsigned int)'
203 | const char *pinctrl_generic_get_group_name(struct pinctrl_dev *pctldev,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:203:13: note: previous declaration of 'pinctrl_generic_get_group_name' with type 'const char *(struct pinctrl_dev *, unsigned int)'
203 | const char *pinctrl_generic_get_group_name(struct pinctrl_dev *pctldev,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:206:5: error: conflicting types for 'pinctrl_generic_get_group_pins'; have 'int(struct pinctrl_dev *, unsigned int, const unsigned int **, unsigned int *)'
206 | int pinctrl_generic_get_group_pins(struct pinctrl_dev *pctldev,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:206:5: note: previous declaration of 'pinctrl_generic_get_group_pins' with type 'int(struct pinctrl_dev *, unsigned int, const unsigned int **, unsigned int *)'
206 | int pinctrl_generic_get_group_pins(struct pinctrl_dev *pctldev,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:211:20: error: conflicting types for 'pinctrl_generic_get_group'; have 'struct group_desc *(struct pinctrl_dev *, unsigned int)'
211 | struct group_desc *pinctrl_generic_get_group(struct pinctrl_dev *pctldev,
| ^~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:211:20: note: previous declaration of 'pinctrl_generic_get_group' with type 'struct group_desc *(struct pinctrl_dev *, unsigned int)'
211 | struct group_desc *pinctrl_generic_get_group(struct pinctrl_dev *pctldev,
| ^~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:214:5: error: conflicting types for 'pinctrl_generic_add_group'; have 'int(struct pinctrl_dev *, const char *, int *, int, void *)'
214 | int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name,
| ^~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:214:5: note: previous declaration of 'pinctrl_generic_add_group' with type 'int(struct pinctrl_dev *, const char *, int *, int, void *)'
214 | int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name,
| ^~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:217:5: error: conflicting types for 'pinctrl_generic_remove_group'; have 'int(struct pinctrl_dev *, unsigned int)'
217 | int pinctrl_generic_remove_group(struct pinctrl_dev *pctldev,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:217:5: note: previous declaration of 'pinctrl_generic_remove_group' with type 'int(struct pinctrl_dev *, unsigned int)'
217 | int pinctrl_generic_remove_group(struct pinctrl_dev *pctldev,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:222:21: error: conflicting types for 'get_pinctrl_dev_from_devname'; have 'struct pinctrl_dev *(const char *)'
222 | struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:222:21: note: previous declaration of 'get_pinctrl_dev_from_devname' with type 'struct pinctrl_dev *(const char *)'
222 | struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:223:21: error: conflicting types for 'get_pinctrl_dev_from_of_node'; have 'struct pinctrl_dev *(struct device_node *)'
223 | struct pinctrl_dev *get_pinctrl_dev_from_of_node(struct device_node *np);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:223:21: note: previous declaration of 'get_pinctrl_dev_from_of_node' with type 'struct pinctrl_dev *(struct device_node *)'
223 | struct pinctrl_dev *get_pinctrl_dev_from_of_node(struct device_node *np);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:224:5: error: conflicting types for 'pin_get_from_name'; have 'int(struct pinctrl_dev *, const char *)'
224 | int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name);
| ^~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:224:5: note: previous declaration of 'pin_get_from_name' with type 'int(struct pinctrl_dev *, const char *)'
224 | int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name);
| ^~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:225:13: error: conflicting types for 'pin_get_name'; have 'const char *(struct pinctrl_dev *, const unsigned int)'
225 | const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin);
| ^~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:225:13: note: previous declaration of 'pin_get_name' with type 'const char *(struct pinctrl_dev *, const unsigned int)'
225 | const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin);
| ^~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
>> drivers/pinctrl/qcom/../core.h:226:5: error: conflicting types for 'pinctrl_get_group_selector'; have 'int(struct pinctrl_dev *, const char *)'
226 | int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:226:5: note: previous declaration of 'pinctrl_get_group_selector' with type 'int(struct pinctrl_dev *, const char *)'
226 | int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
drivers/pinctrl/qcom/../core.h:229:32: error: conflicting types for 'pin_desc_get'; have 'struct pin_desc *(struct pinctrl_dev *, unsigned int)'
229 | static inline struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev,
| ^~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:229:32: note: previous definition of 'pin_desc_get' with type 'struct pin_desc *(struct pinctrl_dev *, unsigned int)'
229 | static inline struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev,
| ^~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
drivers/pinctrl/qcom/../core.h:236:1: error: conflicting types for 'pinctrl_find_gpio_range_from_pin_nolock'; have 'struct pinctrl_gpio_range *(struct pinctrl_dev *, unsigned int)'
236 | pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:236:1: note: previous declaration of 'pinctrl_find_gpio_range_from_pin_nolock' with type 'struct pinctrl_gpio_range *(struct pinctrl_dev *, unsigned int)'
236 | pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
drivers/pinctrl/qcom/../core.h:239:12: error: conflicting types for 'pinctrl_force_sleep'; have 'int(struct pinctrl_dev *)'
239 | extern int pinctrl_force_sleep(struct pinctrl_dev *pctldev);
| ^~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:239:12: note: previous declaration of 'pinctrl_force_sleep' with type 'int(struct pinctrl_dev *)'
239 | extern int pinctrl_force_sleep(struct pinctrl_dev *pctldev);
| ^~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:12:
drivers/pinctrl/qcom/../core.h:240:12: error: conflicting types for 'pinctrl_force_default'; have 'int(struct pinctrl_dev *)'
240 | extern int pinctrl_force_default(struct pinctrl_dev *pctldev);
| ^~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/qcom/pinctrl-lpass-lpi.h:11,
from drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c:11:
drivers/pinctrl/qcom/../core.h:240:12: note: previous declaration of 'pinctrl_force_default' with type 'int(struct pinctrl_dev *)'
240 | extern int pinctrl_force_default(struct pinctrl_dev *pctldev);
| ^~~~~~~~~~~~~~~~~~~~~
vim +42 drivers/pinctrl/qcom/../core.h
ae6b4d8588f4fc Linus Walleij 2011-10-19 18
2744e8afb3b763 Linus Walleij 2011-05-02 19 /**
2744e8afb3b763 Linus Walleij 2011-05-02 20 * struct pinctrl_dev - pin control class device
2744e8afb3b763 Linus Walleij 2011-05-02 21 * @node: node to include this pin controller in the global pin controller list
2744e8afb3b763 Linus Walleij 2011-05-02 22 * @desc: the pin controller descriptor supplied when initializing this pin
2744e8afb3b763 Linus Walleij 2011-05-02 23 * controller
2744e8afb3b763 Linus Walleij 2011-05-02 24 * @pin_desc_tree: each pin descriptor for this pin controller is stored in
2744e8afb3b763 Linus Walleij 2011-05-02 25 * this radix tree
c7059c5ac70aea Tony Lindgren 2016-12-27 26 * @pin_group_tree: optionally each pin group can be stored in this radix tree
c7059c5ac70aea Tony Lindgren 2016-12-27 27 * @num_groups: optionally number of groups can be kept here
a76edc89b100e4 Tony Lindgren 2016-12-27 28 * @pin_function_tree: optionally each function can be stored in this radix tree
a76edc89b100e4 Tony Lindgren 2016-12-27 29 * @num_functions: optionally number of functions can be kept here
2744e8afb3b763 Linus Walleij 2011-05-02 30 * @gpio_ranges: a list of GPIO ranges that is handled by this pin controller,
2744e8afb3b763 Linus Walleij 2011-05-02 31 * ranges are added to this list at runtime
2744e8afb3b763 Linus Walleij 2011-05-02 32 * @dev: the device entry for this pin controller
2744e8afb3b763 Linus Walleij 2011-05-02 33 * @owner: module providing the pin controller, used for refcounting
2744e8afb3b763 Linus Walleij 2011-05-02 34 * @driver_data: driver data for drivers registering to the pin controller
2744e8afb3b763 Linus Walleij 2011-05-02 35 * subsystem
46919ae63d4820 Stephen Warren 2012-03-01 36 * @p: result of pinctrl_get() for this device
840a47ba43a2ae Julien Delacou 2012-12-10 37 * @hog_default: default state for pins hogged by this device
840a47ba43a2ae Julien Delacou 2012-12-10 38 * @hog_sleep: sleep state for pins hogged by this device
42fed7ba44e4e8 Patrice Chotard 2013-04-11 39 * @mutex: mutex taken on each pin controller specific action
befe5bdfbb698b Linus Walleij 2012-02-09 40 * @device_root: debugfs root for this device
2744e8afb3b763 Linus Walleij 2011-05-02 41 */
2744e8afb3b763 Linus Walleij 2011-05-02 @42 struct pinctrl_dev {
2744e8afb3b763 Linus Walleij 2011-05-02 43 struct list_head node;
2744e8afb3b763 Linus Walleij 2011-05-02 44 struct pinctrl_desc *desc;
2744e8afb3b763 Linus Walleij 2011-05-02 45 struct radix_tree_root pin_desc_tree;
c033a718f615b6 Linus Walleij 2016-12-30 46 #ifdef CONFIG_GENERIC_PINCTRL_GROUPS
c7059c5ac70aea Tony Lindgren 2016-12-27 47 struct radix_tree_root pin_group_tree;
c7059c5ac70aea Tony Lindgren 2016-12-27 48 unsigned int num_groups;
a76edc89b100e4 Tony Lindgren 2016-12-27 49 #endif
a76edc89b100e4 Tony Lindgren 2016-12-27 50 #ifdef CONFIG_GENERIC_PINMUX_FUNCTIONS
a76edc89b100e4 Tony Lindgren 2016-12-27 51 struct radix_tree_root pin_function_tree;
a76edc89b100e4 Tony Lindgren 2016-12-27 52 unsigned int num_functions;
c033a718f615b6 Linus Walleij 2016-12-30 53 #endif
2744e8afb3b763 Linus Walleij 2011-05-02 54 struct list_head gpio_ranges;
51cd24ee625c34 Stephen Warren 2011-12-09 55 struct device *dev;
2744e8afb3b763 Linus Walleij 2011-05-02 56 struct module *owner;
2744e8afb3b763 Linus Walleij 2011-05-02 57 void *driver_data;
46919ae63d4820 Stephen Warren 2012-03-01 58 struct pinctrl *p;
840a47ba43a2ae Julien Delacou 2012-12-10 59 struct pinctrl_state *hog_default;
840a47ba43a2ae Julien Delacou 2012-12-10 60 struct pinctrl_state *hog_sleep;
42fed7ba44e4e8 Patrice Chotard 2013-04-11 61 struct mutex mutex;
0215716083cac6 Tony Lindgren 2012-01-20 62 #ifdef CONFIG_DEBUG_FS
0215716083cac6 Tony Lindgren 2012-01-20 63 struct dentry *device_root;
0215716083cac6 Tony Lindgren 2012-01-20 64 #endif
befe5bdfbb698b Linus Walleij 2012-02-09 65 };
befe5bdfbb698b Linus Walleij 2012-02-09 66
befe5bdfbb698b Linus Walleij 2012-02-09 67 /**
befe5bdfbb698b Linus Walleij 2012-02-09 68 * struct pinctrl - per-device pin control state holder
befe5bdfbb698b Linus Walleij 2012-02-09 69 * @node: global list node
befe5bdfbb698b Linus Walleij 2012-02-09 70 * @dev: the device using this pin control handle
6e5e959dde0d92 Stephen Warren 2012-03-02 71 * @states: a list of states for this device
6e5e959dde0d92 Stephen Warren 2012-03-02 72 * @state: the current state
57291ce295c0ac Stephen Warren 2012-03-23 73 * @dt_maps: the mapping table chunks dynamically parsed from device tree for
57291ce295c0ac Stephen Warren 2012-03-23 74 * this device, if any
ab78029ecc347d Linus Walleij 2013-01-22 75 * @users: reference count
befe5bdfbb698b Linus Walleij 2012-02-09 76 */
befe5bdfbb698b Linus Walleij 2012-02-09 @77 struct pinctrl {
befe5bdfbb698b Linus Walleij 2012-02-09 78 struct list_head node;
befe5bdfbb698b Linus Walleij 2012-02-09 79 struct device *dev;
6e5e959dde0d92 Stephen Warren 2012-03-02 80 struct list_head states;
6e5e959dde0d92 Stephen Warren 2012-03-02 81 struct pinctrl_state *state;
57291ce295c0ac Stephen Warren 2012-03-23 82 struct list_head dt_maps;
ab78029ecc347d Linus Walleij 2013-01-22 83 struct kref users;
6e5e959dde0d92 Stephen Warren 2012-03-02 84 };
6e5e959dde0d92 Stephen Warren 2012-03-02 85
6e5e959dde0d92 Stephen Warren 2012-03-02 86 /**
6e5e959dde0d92 Stephen Warren 2012-03-02 87 * struct pinctrl_state - a pinctrl state for a device
2c9abf808a81e2 Richard Genoud 2013-03-25 88 * @node: list node for struct pinctrl's @states field
6e5e959dde0d92 Stephen Warren 2012-03-02 89 * @name: the name of this state
6e5e959dde0d92 Stephen Warren 2012-03-02 90 * @settings: a list of settings for this state
6e5e959dde0d92 Stephen Warren 2012-03-02 91 */
6e5e959dde0d92 Stephen Warren 2012-03-02 @92 struct pinctrl_state {
6e5e959dde0d92 Stephen Warren 2012-03-02 93 struct list_head node;
6e5e959dde0d92 Stephen Warren 2012-03-02 94 const char *name;
7ecdb16fe63e5b Stephen Warren 2012-03-02 95 struct list_head settings;
7ecdb16fe63e5b Stephen Warren 2012-03-02 96 };
7ecdb16fe63e5b Stephen Warren 2012-03-02 97
1e2082b5207217 Stephen Warren 2012-03-02 98 /**
1e2082b5207217 Stephen Warren 2012-03-02 99 * struct pinctrl_setting_mux - setting data for MAP_TYPE_MUX_GROUP
1e2082b5207217 Stephen Warren 2012-03-02 100 * @group: the group selector to program
1e2082b5207217 Stephen Warren 2012-03-02 101 * @func: the function selector to program
1e2082b5207217 Stephen Warren 2012-03-02 102 */
1e2082b5207217 Stephen Warren 2012-03-02 @103 struct pinctrl_setting_mux {
1e2082b5207217 Stephen Warren 2012-03-02 104 unsigned group;
1e2082b5207217 Stephen Warren 2012-03-02 105 unsigned func;
1e2082b5207217 Stephen Warren 2012-03-02 106 };
1e2082b5207217 Stephen Warren 2012-03-02 107
1e2082b5207217 Stephen Warren 2012-03-02 108 /**
1e2082b5207217 Stephen Warren 2012-03-02 109 * struct pinctrl_setting_configs - setting data for MAP_TYPE_CONFIGS_*
1e2082b5207217 Stephen Warren 2012-03-02 110 * @group_or_pin: the group selector or pin ID to program
1e2082b5207217 Stephen Warren 2012-03-02 111 * @configs: a pointer to an array of config parameters/values to program into
1e2082b5207217 Stephen Warren 2012-03-02 112 * hardware. Each individual pin controller defines the format and meaning
1e2082b5207217 Stephen Warren 2012-03-02 113 * of config parameters.
1e2082b5207217 Stephen Warren 2012-03-02 114 * @num_configs: the number of entries in array @configs
1e2082b5207217 Stephen Warren 2012-03-02 115 */
1e2082b5207217 Stephen Warren 2012-03-02 @116 struct pinctrl_setting_configs {
1e2082b5207217 Stephen Warren 2012-03-02 117 unsigned group_or_pin;
1e2082b5207217 Stephen Warren 2012-03-02 118 unsigned long *configs;
1e2082b5207217 Stephen Warren 2012-03-02 119 unsigned num_configs;
1e2082b5207217 Stephen Warren 2012-03-02 120 };
1e2082b5207217 Stephen Warren 2012-03-02 121
7ecdb16fe63e5b Stephen Warren 2012-03-02 122 /**
872acc322c74bb Linus Walleij 2012-03-06 123 * struct pinctrl_setting - an individual mux or config setting
6e5e959dde0d92 Stephen Warren 2012-03-02 124 * @node: list node for struct pinctrl_settings's @settings field
1e2082b5207217 Stephen Warren 2012-03-02 125 * @type: the type of setting
57291ce295c0ac Stephen Warren 2012-03-23 126 * @pctldev: pin control device handling to be programmed. Not used for
57291ce295c0ac Stephen Warren 2012-03-23 127 * PIN_MAP_TYPE_DUMMY_STATE.
1a78958dc212f3 Linus Walleij 2012-10-17 128 * @dev_name: the name of the device using this state
1e2082b5207217 Stephen Warren 2012-03-02 129 * @data: Data specific to the setting type
7ecdb16fe63e5b Stephen Warren 2012-03-02 130 */
7ecdb16fe63e5b Stephen Warren 2012-03-02 @131 struct pinctrl_setting {
7ecdb16fe63e5b Stephen Warren 2012-03-02 132 struct list_head node;
1e2082b5207217 Stephen Warren 2012-03-02 133 enum pinctrl_map_type type;
befe5bdfbb698b Linus Walleij 2012-02-09 134 struct pinctrl_dev *pctldev;
1a78958dc212f3 Linus Walleij 2012-10-17 135 const char *dev_name;
1e2082b5207217 Stephen Warren 2012-03-02 136 union {
1e2082b5207217 Stephen Warren 2012-03-02 137 struct pinctrl_setting_mux mux;
1e2082b5207217 Stephen Warren 2012-03-02 138 struct pinctrl_setting_configs configs;
1e2082b5207217 Stephen Warren 2012-03-02 139 } data;
2744e8afb3b763 Linus Walleij 2011-05-02 140 };
2744e8afb3b763 Linus Walleij 2011-05-02 141
2744e8afb3b763 Linus Walleij 2011-05-02 142 /**
2744e8afb3b763 Linus Walleij 2011-05-02 143 * struct pin_desc - pin descriptor for each physical pin in the arch
2744e8afb3b763 Linus Walleij 2011-05-02 144 * @pctldev: corresponding pin control device
2744e8afb3b763 Linus Walleij 2011-05-02 145 * @name: a name for the pin, e.g. the name of the pin/pad/finger on a
2744e8afb3b763 Linus Walleij 2011-05-02 146 * datasheet or such
ca53c5f1ca5c93 Linus Walleij 2011-12-14 147 * @dynamic_name: if the name of this pin was dynamically allocated
cd8f61f1e52b33 Masahiro Yamada 2016-05-25 148 * @drv_data: driver-defined per-pin data. pinctrl core does not touch this
652162d469a734 Stephen Warren 2012-03-05 149 * @mux_usecount: If zero, the pin is not claimed, and @owner should be NULL.
0e3db173e2b9fd Stephen Warren 2012-03-02 150 * If non-zero, this pin is claimed by @owner. This field is an integer
0e3db173e2b9fd Stephen Warren 2012-03-02 151 * rather than a boolean, since pinctrl_get() might process multiple
0e3db173e2b9fd Stephen Warren 2012-03-02 152 * mapping table entries that refer to, and hence claim, the same group
0e3db173e2b9fd Stephen Warren 2012-03-02 153 * or pin, and each of these will increment the @usecount.
652162d469a734 Stephen Warren 2012-03-05 154 * @mux_owner: The name of device that called pinctrl_get().
ba110d90c08d96 Stephen Warren 2012-03-02 155 * @mux_setting: The most recent selected mux setting for this pin, if any.
a9a1d2a7827c9c Linus Walleij 2017-09-22 156 * @gpio_owner: If pinctrl_gpio_request() was called for this pin, this is
652162d469a734 Stephen Warren 2012-03-05 157 * the name of the GPIO that "owns" this pin.
2744e8afb3b763 Linus Walleij 2011-05-02 158 */
2744e8afb3b763 Linus Walleij 2011-05-02 @159 struct pin_desc {
2744e8afb3b763 Linus Walleij 2011-05-02 160 struct pinctrl_dev *pctldev;
9af1e44fb4a4c6 Stephen Warren 2011-10-19 161 const char *name;
ca53c5f1ca5c93 Linus Walleij 2011-12-14 162 bool dynamic_name;
cd8f61f1e52b33 Masahiro Yamada 2016-05-25 163 void *drv_data;
2744e8afb3b763 Linus Walleij 2011-05-02 164 /* These fields only added when supporting pinmux drivers */
2744e8afb3b763 Linus Walleij 2011-05-02 165 #ifdef CONFIG_PINMUX
652162d469a734 Stephen Warren 2012-03-05 166 unsigned mux_usecount;
652162d469a734 Stephen Warren 2012-03-05 167 const char *mux_owner;
ba110d90c08d96 Stephen Warren 2012-03-02 168 const struct pinctrl_setting_mux *mux_setting;
652162d469a734 Stephen Warren 2012-03-05 169 const char *gpio_owner;
2744e8afb3b763 Linus Walleij 2011-05-02 170 #endif
2744e8afb3b763 Linus Walleij 2011-05-02 171 };
2744e8afb3b763 Linus Walleij 2011-05-02 172
c033a718f615b6 Linus Walleij 2016-12-30 173 /**
c033a718f615b6 Linus Walleij 2016-12-30 174 * struct pinctrl_maps - a list item containing part of the mapping table
c033a718f615b6 Linus Walleij 2016-12-30 175 * @node: mapping table list node
c033a718f615b6 Linus Walleij 2016-12-30 176 * @maps: array of mapping table entries
c033a718f615b6 Linus Walleij 2016-12-30 177 * @num_maps: the number of entries in @maps
c033a718f615b6 Linus Walleij 2016-12-30 178 */
c033a718f615b6 Linus Walleij 2016-12-30 @179 struct pinctrl_maps {
c033a718f615b6 Linus Walleij 2016-12-30 180 struct list_head node;
3f713b7c223ebe Masahiro Yamada 2017-08-04 181 const struct pinctrl_map *maps;
c033a718f615b6 Linus Walleij 2016-12-30 182 unsigned num_maps;
c033a718f615b6 Linus Walleij 2016-12-30 183 };
c033a718f615b6 Linus Walleij 2016-12-30 184
c033a718f615b6 Linus Walleij 2016-12-30 185 #ifdef CONFIG_GENERIC_PINCTRL_GROUPS
c033a718f615b6 Linus Walleij 2016-12-30 186
c7059c5ac70aea Tony Lindgren 2016-12-27 187 /**
c7059c5ac70aea Tony Lindgren 2016-12-27 188 * struct group_desc - generic pin group descriptor
c7059c5ac70aea Tony Lindgren 2016-12-27 189 * @name: name of the pin group
c7059c5ac70aea Tony Lindgren 2016-12-27 190 * @pins: array of pins that belong to the group
c7059c5ac70aea Tony Lindgren 2016-12-27 191 * @num_pins: number of pins in the group
c7059c5ac70aea Tony Lindgren 2016-12-27 192 * @data: pin controller driver specific data
c7059c5ac70aea Tony Lindgren 2016-12-27 193 */
c7059c5ac70aea Tony Lindgren 2016-12-27 @194 struct group_desc {
c7059c5ac70aea Tony Lindgren 2016-12-27 195 const char *name;
c7059c5ac70aea Tony Lindgren 2016-12-27 196 int *pins;
c7059c5ac70aea Tony Lindgren 2016-12-27 197 int num_pins;
c7059c5ac70aea Tony Lindgren 2016-12-27 198 void *data;
c7059c5ac70aea Tony Lindgren 2016-12-27 199 };
c7059c5ac70aea Tony Lindgren 2016-12-27 200
c7059c5ac70aea Tony Lindgren 2016-12-27 @201 int pinctrl_generic_get_group_count(struct pinctrl_dev *pctldev);
c7059c5ac70aea Tony Lindgren 2016-12-27 202
c7059c5ac70aea Tony Lindgren 2016-12-27 @203 const char *pinctrl_generic_get_group_name(struct pinctrl_dev *pctldev,
c7059c5ac70aea Tony Lindgren 2016-12-27 204 unsigned int group_selector);
c7059c5ac70aea Tony Lindgren 2016-12-27 205
c7059c5ac70aea Tony Lindgren 2016-12-27 @206 int pinctrl_generic_get_group_pins(struct pinctrl_dev *pctldev,
c7059c5ac70aea Tony Lindgren 2016-12-27 207 unsigned int group_selector,
c7059c5ac70aea Tony Lindgren 2016-12-27 208 const unsigned int **pins,
c7059c5ac70aea Tony Lindgren 2016-12-27 209 unsigned int *npins);
c7059c5ac70aea Tony Lindgren 2016-12-27 210
c7059c5ac70aea Tony Lindgren 2016-12-27 @211 struct group_desc *pinctrl_generic_get_group(struct pinctrl_dev *pctldev,
c7059c5ac70aea Tony Lindgren 2016-12-27 212 unsigned int group_selector);
c7059c5ac70aea Tony Lindgren 2016-12-27 213
c7059c5ac70aea Tony Lindgren 2016-12-27 @214 int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name,
c7059c5ac70aea Tony Lindgren 2016-12-27 215 int *gpins, int ngpins, void *data);
c7059c5ac70aea Tony Lindgren 2016-12-27 216
c7059c5ac70aea Tony Lindgren 2016-12-27 @217 int pinctrl_generic_remove_group(struct pinctrl_dev *pctldev,
c7059c5ac70aea Tony Lindgren 2016-12-27 218 unsigned int group_selector);
c7059c5ac70aea Tony Lindgren 2016-12-27 219
c033a718f615b6 Linus Walleij 2016-12-30 220 #endif /* CONFIG_GENERIC_PINCTRL_GROUPS */
c7059c5ac70aea Tony Lindgren 2016-12-27 221
9dfac4fd7f8cdc Linus Walleij 2012-02-01 @222 struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name);
42fed7ba44e4e8 Patrice Chotard 2013-04-11 @223 struct pinctrl_dev *get_pinctrl_dev_from_of_node(struct device_node *np);
ae6b4d8588f4fc Linus Walleij 2011-10-19 @224 int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name);
dcb5dbc305b975 Dong Aisheng 2012-04-17 @225 const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin);
7afde8baa83b9a Linus Walleij 2011-10-19 @226 int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
7afde8baa83b9a Linus Walleij 2011-10-19 227 const char *pin_group);
2304b4737f492b Stephen Warren 2012-02-22 228
2304b4737f492b Stephen Warren 2012-02-22 @229 static inline struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev,
2304b4737f492b Stephen Warren 2012-02-22 230 unsigned int pin)
2304b4737f492b Stephen Warren 2012-02-22 231 {
2304b4737f492b Stephen Warren 2012-02-22 232 return radix_tree_lookup(&pctldev->pin_desc_tree, pin);
2304b4737f492b Stephen Warren 2012-02-22 233 }
57b676f9c1b7cd Stephen Warren 2012-03-02 234
b18537cd8ec2e5 Joachim Eastwood 2016-02-25 235 extern struct pinctrl_gpio_range *
b18537cd8ec2e5 Joachim Eastwood 2016-02-25 @236 pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev,
b18537cd8ec2e5 Joachim Eastwood 2016-02-25 237 unsigned int pin);
b18537cd8ec2e5 Joachim Eastwood 2016-02-25 238
840a47ba43a2ae Julien Delacou 2012-12-10 @239 extern int pinctrl_force_sleep(struct pinctrl_dev *pctldev);
840a47ba43a2ae Julien Delacou 2012-12-10 @240 extern int pinctrl_force_default(struct pinctrl_dev *pctldev);
840a47ba43a2ae Julien Delacou 2012-12-10 241
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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2022-02-21 14:59 [PATCH v8 0/7] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu
2022-02-21 14:59 ` [PATCH v8 1/7] dt-bindings: pinctrl: qcom: Update lpass lpi file name to SoC specific Srinivasa Rao Mandadapu
2022-02-21 14:59 ` [PATCH v8 2/7] dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl bindings Srinivasa Rao Mandadapu
2022-02-21 14:59 ` [PATCH v8 3/7] pinctrl: qcom: Update macro name to LPI specific Srinivasa Rao Mandadapu
2022-02-21 14:59 ` [PATCH v8 4/7] pinctrl: qcom: Update lpi pin group structure Srinivasa Rao Mandadapu
2022-02-21 14:59 ` [PATCH v8 5/7] pinctrl: qcom: Extract chip specific LPASS LPI code Srinivasa Rao Mandadapu
2022-02-22 17:54 ` kernel test robot
2022-02-21 14:59 ` [PATCH v8 6/7] pinctrl: qcom: Add SC7280 lpass pin configuration Srinivasa Rao Mandadapu
2022-02-21 14:59 ` [PATCH v8 7/7] pinctrl: qcom: Update clock voting as optional Srinivasa Rao Mandadapu
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