* [PATCH v2 0/2] pinctrl: renesas: r8a77990: add drive-strength @ 2022-03-20 9:25 Wolfram Sang 2022-03-20 9:25 ` [PATCH v2 1/2] pinctrl: renesas: allow up to 10 fields for drive_regs Wolfram Sang 2022-03-20 9:25 ` [PATCH v2 2/2] pinctrl: renesas: r8a77990: add drive-strength Wolfram Sang 0 siblings, 2 replies; 5+ messages in thread From: Wolfram Sang @ 2022-03-20 9:25 UTC (permalink / raw) To: linux-renesas-soc; +Cc: linux-gpio, Wolfram Sang This series upports a BSP patch. Please check the notes on the patches. Changes since V1: * support RZ/G2E as well Wolfram Sang (2): pinctrl: renesas: allow up to 10 fields for drive_regs pinctrl: renesas: r8a77990: add drive-strength drivers/pinctrl/renesas/pfc-r8a77990.c | 39 ++++++++++++++++++++++++-- drivers/pinctrl/renesas/sh_pfc.h | 2 +- 2 files changed, 38 insertions(+), 3 deletions(-) -- 2.30.2 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/2] pinctrl: renesas: allow up to 10 fields for drive_regs 2022-03-20 9:25 [PATCH v2 0/2] pinctrl: renesas: r8a77990: add drive-strength Wolfram Sang @ 2022-03-20 9:25 ` Wolfram Sang 2022-04-01 16:20 ` Geert Uytterhoeven 2022-03-20 9:25 ` [PATCH v2 2/2] pinctrl: renesas: r8a77990: add drive-strength Wolfram Sang 1 sibling, 1 reply; 5+ messages in thread From: Wolfram Sang @ 2022-03-20 9:25 UTC (permalink / raw) To: linux-renesas-soc; +Cc: linux-gpio, Wolfram Sang Needed to support E3 and G2E drive regs. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- drivers/pinctrl/renesas/sh_pfc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 2479b4fb9cf9..86cdcb292e23 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -181,7 +181,7 @@ struct pinmux_drive_reg_field { struct pinmux_drive_reg { u32 reg; - const struct pinmux_drive_reg_field fields[8]; + const struct pinmux_drive_reg_field fields[10]; }; #define PINMUX_DRIVE_REG(name, r) \ -- 2.30.2 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] pinctrl: renesas: allow up to 10 fields for drive_regs 2022-03-20 9:25 ` [PATCH v2 1/2] pinctrl: renesas: allow up to 10 fields for drive_regs Wolfram Sang @ 2022-04-01 16:20 ` Geert Uytterhoeven 0 siblings, 0 replies; 5+ messages in thread From: Geert Uytterhoeven @ 2022-04-01 16:20 UTC (permalink / raw) To: Wolfram Sang; +Cc: Linux-Renesas, open list:GPIO SUBSYSTEM On Mon, Mar 21, 2022 at 12:41 AM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > Needed to support E3 and G2E drive regs. > > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-pinctrl-for-v5.19. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] pinctrl: renesas: r8a77990: add drive-strength 2022-03-20 9:25 [PATCH v2 0/2] pinctrl: renesas: r8a77990: add drive-strength Wolfram Sang 2022-03-20 9:25 ` [PATCH v2 1/2] pinctrl: renesas: allow up to 10 fields for drive_regs Wolfram Sang @ 2022-03-20 9:25 ` Wolfram Sang 2022-04-01 16:21 ` Geert Uytterhoeven 1 sibling, 1 reply; 5+ messages in thread From: Wolfram Sang @ 2022-03-20 9:25 UTC (permalink / raw) To: linux-renesas-soc; +Cc: linux-gpio, Wolfram Sang, LUU HOAI According to R-Car Gen3 HW documentation 2.20 onwards, drive-strength is introduced to r8a77990. It is also documented for r8a774c0. Add it to the pinctrl driver. Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- Changes since V1: * support RZ/G2E as well Original BSP commit: f479c5a4e5e5 ("pinctrl: renesas: r8a77990: Add driver-strength for R8A77990") However, this was incomplete and missed 6 pins of table 6D.6 which were on a separate page. Adding them simplifies PORT_GP updates a lot. However, a preparational patch is needed then which is patch 1 of this series. drivers/pinctrl/renesas/pfc-r8a77990.c | 39 ++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index f44c7da3ec16..bbd1cdada522 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -22,12 +22,12 @@ PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ @@ -5104,6 +5104,39 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; +static const struct pinmux_drive_reg pinmux_drive_regs[] = { + { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { + { RCAR_GP_PIN(3, 0), 18, 2 }, /* SD0_CLK */ + { RCAR_GP_PIN(3, 1), 15, 2 }, /* SD0_CMD */ + { RCAR_GP_PIN(3, 2), 12, 2 }, /* SD0_DAT0 */ + { RCAR_GP_PIN(3, 3), 9, 2 }, /* SD0_DAT1 */ + { RCAR_GP_PIN(3, 4), 6, 2 }, /* SD0_DAT2 */ + { RCAR_GP_PIN(3, 5), 3, 2 }, /* SD0_DAT3 */ + { RCAR_GP_PIN(3, 6), 0, 2 }, /* SD1_CLK */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { + { RCAR_GP_PIN(3, 7), 29, 2 }, /* SD1_CMD */ + { RCAR_GP_PIN(3, 8), 26, 2 }, /* SD1_DAT0 */ + { RCAR_GP_PIN(3, 9), 23, 2 }, /* SD1_DAT1 */ + { RCAR_GP_PIN(3, 10), 20, 2 }, /* SD1_DAT2 */ + { RCAR_GP_PIN(3, 11), 17, 2 }, /* SD1_DAT3 */ + { RCAR_GP_PIN(4, 0), 14, 2 }, /* SD3_CLK */ + { RCAR_GP_PIN(4, 1), 11, 2 }, /* SD3_CMD */ + { RCAR_GP_PIN(4, 2), 8, 2 }, /* SD3_DAT0 */ + { RCAR_GP_PIN(4, 3), 5, 2 }, /* SD3_DAT1 */ + { RCAR_GP_PIN(4, 4), 2, 2 }, /* SD3_DAT2 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { + { RCAR_GP_PIN(4, 5), 29, 2 }, /* SD3_DAT3 */ + { RCAR_GP_PIN(4, 6), 26, 2 }, /* SD3_DAT4 */ + { RCAR_GP_PIN(4, 7), 23, 2 }, /* SD3_DAT5 */ + { RCAR_GP_PIN(4, 8), 20, 2 }, /* SD3_DAT6 */ + { RCAR_GP_PIN(4, 9), 17, 2 }, /* SD3_DAT7 */ + { RCAR_GP_PIN(4, 10), 14, 2 }, /* SD3_DS */ + } }, + { }, +}; + enum ioctrl_regs { POCCTRL0, TDSELCTRL, @@ -5361,6 +5394,7 @@ const struct sh_pfc_soc_info r8a774c0_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions.common), .cfg_regs = pinmux_config_regs, + .drive_regs = pinmux_drive_regs, .bias_regs = pinmux_bias_regs, .ioctrl_regs = pinmux_ioctrl_regs, @@ -5387,6 +5421,7 @@ const struct sh_pfc_soc_info r8a77990_pinmux_info = { ARRAY_SIZE(pinmux_functions.automotive), .cfg_regs = pinmux_config_regs, + .drive_regs = pinmux_drive_regs, .bias_regs = pinmux_bias_regs, .ioctrl_regs = pinmux_ioctrl_regs, -- 2.30.2 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/2] pinctrl: renesas: r8a77990: add drive-strength 2022-03-20 9:25 ` [PATCH v2 2/2] pinctrl: renesas: r8a77990: add drive-strength Wolfram Sang @ 2022-04-01 16:21 ` Geert Uytterhoeven 0 siblings, 0 replies; 5+ messages in thread From: Geert Uytterhoeven @ 2022-04-01 16:21 UTC (permalink / raw) To: Wolfram Sang; +Cc: Linux-Renesas, open list:GPIO SUBSYSTEM, LUU HOAI On Mon, Mar 21, 2022 at 2:43 AM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > According to R-Car Gen3 HW documentation 2.20 onwards, drive-strength is > introduced to r8a77990. It is also documented for r8a774c0. Add it to > the pinctrl driver. > > Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com> > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-pinctrl-for-v5.19. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-04-01 16:39 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-03-20 9:25 [PATCH v2 0/2] pinctrl: renesas: r8a77990: add drive-strength Wolfram Sang 2022-03-20 9:25 ` [PATCH v2 1/2] pinctrl: renesas: allow up to 10 fields for drive_regs Wolfram Sang 2022-04-01 16:20 ` Geert Uytterhoeven 2022-03-20 9:25 ` [PATCH v2 2/2] pinctrl: renesas: r8a77990: add drive-strength Wolfram Sang 2022-04-01 16:21 ` Geert Uytterhoeven
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