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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id 97-20020a9d0eea000000b00605da994088sm4420874otj.2.2022.05.16.17.01.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 May 2022 17:01:54 -0700 (PDT) Received: (nullmailer pid 3601836 invoked by uid 1000); Tue, 17 May 2022 00:01:53 -0000 Date: Mon, 16 May 2022 19:01:53 -0500 From: Rob Herring To: Sebastian Reichel Cc: Heiko Stuebner , Krzysztof Kozlowski , Linus Walleij , Bartosz Golaszewski , Adrian Hunter , Ulf Hansson , Philipp Zabel , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@lists.collabora.co.uk, Elaine Zhang , kernel@collabora.com Subject: Re: [PATCHv2 03/21] dt-binding: clock: Document rockchip,rk3588-cru bindings Message-ID: <20220517000153.GA3593598-robh@kernel.org> References: <20220504213251.264819-1-sebastian.reichel@collabora.com> <20220504213251.264819-4-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220504213251.264819-4-sebastian.reichel@collabora.com> Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Wed, May 04, 2022 at 11:32:33PM +0200, Sebastian Reichel wrote: > From: Elaine Zhang > > Document the device tree bindings of the rockchip Rk3588 SoC > clock driver. > > Signed-off-by: Elaine Zhang > Signed-off-by: Sebastian Reichel > --- > .../bindings/clock/rockchip,rk3588-cru.yaml | 63 +++++++++++++++++++ > 1 file changed, 63 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml > > diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml > new file mode 100644 > index 000000000000..6e65ee7b0092 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml > @@ -0,0 +1,63 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/rockchip,rk3588-cru.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip rk3588 Family Clock Control Module > + > +maintainers: > + - Elaine Zhang > + - Heiko Stuebner > + > +description: | > + The RK3588 clock controller generates the clock and also implements a > + reset controller for SoC peripherals. > + (examples: provide SCLK_UART2\PCLK_UART2 and SRST_P_UART2\SRST_S_UART2 for UART module) > + Each clock is assigned an identifier and client nodes can use this identifier > + to specify the clock which they consume. All available clocks are defined as > + preprocessor macros in the dt-bindings/clock/rk3588-cru.h headers and can be > + used in device tree sources. > + > +properties: > + compatible: > + enum: > + - rockchip,rk3588-cru > + > + reg: > + maxItems: 1 > + > + "#clock-cells": > + const: 1 > + > + "#reset-cells": > + const: 1 > + > + rockchip,grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > > + phandle to the syscon managing the "general register files". It is used > + for GRF muxes, if missing any muxes present in the GRF will not be > + available. > + > + clocks: true You have to define how many clocks and what they are. > + assigned-clocks: true > + assigned-clock-rates: true You don't need these. They are allowed in any node with 'clocks' or now '#clock-cells'. > + > +required: > + - compatible > + - reg > + - "#clock-cells" > + - "#reset-cells" > + > +additionalProperties: false > + > +examples: > + # Clock Control Module node: > + - | > + cru: clock-controller@fd7c0000 { > + compatible = "rockchip,rk3588-cru"; > + reg = <0xfd7c0000 0x5c000>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > -- > 2.35.1 > >