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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id n10-20020a0568301e8a00b0060b1e040014sm1570001otr.51.2022.05.24.11.47.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 11:47:21 -0700 (PDT) Received: (nullmailer pid 4157335 invoked by uid 1000); Tue, 24 May 2022 18:47:20 -0000 Date: Tue, 24 May 2022 13:47:20 -0500 From: Rob Herring To: Phil Edworthy Cc: Geert Uytterhoeven , Linus Walleij , Krzysztof Kozlowski , Lad Prabhakar , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add DT bindings for RZ/V2M pinctrl Message-ID: <20220524184720.GA4138401-robh@kernel.org> References: <20220520154051.29088-1-phil.edworthy@renesas.com> <20220520154051.29088-2-phil.edworthy@renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220520154051.29088-2-phil.edworthy@renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Fri, May 20, 2022 at 04:40:50PM +0100, Phil Edworthy wrote: > Add device tree binding documentation and header file for Renesas > RZ/V2M pinctrl. > > Signed-off-by: Phil Edworthy > Reviewed-by: Lad Prabhakar > --- > .../pinctrl/renesas,rzv2m-pinctrl.yaml | 174 ++++++++++++++++++ > include/dt-bindings/pinctrl/rzv2m-pinctrl.h | 23 +++ > 2 files changed, 197 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml > create mode 100644 include/dt-bindings/pinctrl/rzv2m-pinctrl.h > > diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml > new file mode 100644 > index 000000000000..305e836cf0a3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml > @@ -0,0 +1,174 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/renesas,rzv2m-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/V2M combined Pin and GPIO controller > + > +maintainers: > + - Geert Uytterhoeven > + - Phil Edworthy > + > +description: > + The Renesas RZ/V2M SoC features a combined Pin and GPIO controller. > + Pin multiplexing and GPIO configuration is performed on a per-pin basis. > + Each port features up to 16 pins, each of them configurable for GPIO function > + (port mode) or in alternate function mode. > + Up to 8 different alternate function modes exist for each single pin. > + > +properties: > + compatible: > + oneOf: > + - items: > + - const: renesas,r9a09g011-pinctrl # RZ/V2M With only 1, you can drop 'oneOf' and 'items'. > + > + reg: > + maxItems: 1 > + > + gpio-controller: true > + > + '#gpio-cells': > + const: 2 > + description: > + The first cell contains the global GPIO port index, constructed using the > + RZV2M_GPIO() helper macro in and the > + second cell represents consumer flag as mentioned in ../gpio/gpio.txt > + E.g. "RZV2M_GPIO(8, 1)" for P8_1. > + > + gpio-ranges: > + maxItems: 1 > + > + interrupts: > + maxItems: 39 Needs some description as to what all these are. If it is not all the same kind of interrupt, then each one has to be listed. Rob