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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id b2-20020a9d7542000000b00637032a39a3sm560382otl.6.2022.09.30.05.51.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 05:51:05 -0700 (PDT) Received: (nullmailer pid 95617 invoked by uid 1000); Fri, 30 Sep 2022 12:51:05 -0000 Date: Fri, 30 Sep 2022 07:51:05 -0500 From: Rob Herring To: Hal Feng Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Marc Zyngier , Philipp Zabel , Stephen Boyd , Michael Turquette , Linus Walleij , Emil Renner Berthing , linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 20/30] dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings Message-ID: <20220930125105.GA93753-robh@kernel.org> References: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> <20220930055632.5136-1-hal.feng@linux.starfivetech.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220930055632.5136-1-hal.feng@linux.starfivetech.com> Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Fri, Sep 30, 2022 at 01:56:32PM +0800, Hal Feng wrote: > From: Emil Renner Berthing > > Add bindings for the always-on clock generator on the JH7110 > RISC-V SoC by StarFive Technology Ltd. > > Signed-off-by: Emil Renner Berthing > Signed-off-by: Hal Feng > --- > .../clock/starfive,jh7110-clkgen-aon.yaml | 62 +++++++++++++++++++ > 1 file changed, 62 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml > > diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml > new file mode 100644 > index 000000000000..029ff57b9e3e > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml > @@ -0,0 +1,62 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/starfive,jh7110-clkgen-aon.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive JH7110 Always-On Clock Generator > + > +maintainers: > + - Emil Renner Berthing > + - Xingyu Wu > + > +properties: > + compatible: > + const: starfive,jh7110-clkgen-aon > + > + clocks: > + items: > + - description: Main Oscillator > + - description: RTC clock > + - description: RMII reference clock > + - description: RGMII RX clock > + - description: STG AXI/AHB clock > + - description: APB Bus clock > + > + clock-names: > + items: > + - const: osc > + - const: clk_rtc > + - const: gmac0_rmii_refin > + - const: gmac0_rgmii_rxin > + - const: stg_axiahb > + - const: apb_bus_func > + > + '#clock-cells': > + const: 1 > + description: > + See for valid indices. No 'reg'? How do you access this h/w then? If it is part of some block, we need to see the full picture. Rob