* [PATCH] pinctrl: sunxi: d1: Add CAN bus pinmuxes
@ 2022-11-26 19:16 Samuel Holland
2022-11-26 21:59 ` Linus Walleij
0 siblings, 1 reply; 2+ messages in thread
From: Samuel Holland @ 2022-11-26 19:16 UTC (permalink / raw)
To: Chen-Yu Tsai, Jernej Skrabec, Linus Walleij
Cc: Fabien Poussin, Samuel Holland, linux-arm-kernel, linux-gpio,
linux-kernel, linux-sunxi
From: Fabien Poussin <fabien.poussin@gmail.com>
The D1 pin controller contains muxes for two CAN buses. While the CAN
bus controllers are only documented for the T113 SoC, the pin controller
is the same across all SoC variants.
Signed-off-by: Fabien Poussin <fabien.poussin@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c b/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c
index 40858b881298..9cc94be1046d 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c
@@ -47,6 +47,7 @@ static const struct sunxi_desc_pin d1_pins[] = {
SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN2 */
SUNXI_FUNCTION(0x6, "lcd0"), /* D18 */
SUNXI_FUNCTION(0x7, "uart4"), /* TX */
+ SUNXI_FUNCTION(0x8, "can0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -57,6 +58,7 @@ static const struct sunxi_desc_pin d1_pins[] = {
SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN0 */
SUNXI_FUNCTION(0x6, "lcd0"), /* D19 */
SUNXI_FUNCTION(0x7, "uart4"), /* RX */
+ SUNXI_FUNCTION(0x8, "can0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -67,6 +69,7 @@ static const struct sunxi_desc_pin d1_pins[] = {
SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN1 */
SUNXI_FUNCTION(0x6, "lcd0"), /* D20 */
SUNXI_FUNCTION(0x7, "uart5"), /* TX */
+ SUNXI_FUNCTION(0x8, "can1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -77,6 +80,7 @@ static const struct sunxi_desc_pin d1_pins[] = {
SUNXI_FUNCTION(0x5, "pwm0"),
SUNXI_FUNCTION(0x6, "lcd0"), /* D21 */
SUNXI_FUNCTION(0x7, "uart5"), /* RX */
+ SUNXI_FUNCTION(0x8, "can1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
--
2.37.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] pinctrl: sunxi: d1: Add CAN bus pinmuxes
2022-11-26 19:16 [PATCH] pinctrl: sunxi: d1: Add CAN bus pinmuxes Samuel Holland
@ 2022-11-26 21:59 ` Linus Walleij
0 siblings, 0 replies; 2+ messages in thread
From: Linus Walleij @ 2022-11-26 21:59 UTC (permalink / raw)
To: Samuel Holland
Cc: Chen-Yu Tsai, Jernej Skrabec, Fabien Poussin, linux-arm-kernel,
linux-gpio, linux-kernel, linux-sunxi
On Sat, Nov 26, 2022 at 8:16 PM Samuel Holland <samuel@sholland.org> wrote:
> From: Fabien Poussin <fabien.poussin@gmail.com>
>
> The D1 pin controller contains muxes for two CAN buses. While the CAN
> bus controllers are only documented for the T113 SoC, the pin controller
> is the same across all SoC variants.
>
> Signed-off-by: Fabien Poussin <fabien.poussin@gmail.com>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
Patch applied so we get some linux-next rotation on this before
the merge window. If someone protests, I can always pull it out.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 2+ messages in thread
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