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From: Chester Lin <clin@suse.com>
To: Linus Walleij <linus.walleij@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Dong Aisheng <aisheng.dong@nxp.com>,
	Fabio Estevam <festevam@gmail.com>,
	Shawn Guo <shawnguo@kernel.org>, Jacky Bai <ping.bai@nxp.com>
Cc: "Chester Lin" <clin@suse.com>,
	s32@nxp.com, linux-gpio@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	"Pengutronix Kernel Team" <kernel@pengutronix.de>,
	"Larisa Grigore" <larisa.grigore@nxp.com>,
	"Ghennadi Procopciuc" <Ghennadi.Procopciuc@nxp.com>,
	"Andrei Stefanescu" <andrei.stefanescu@nxp.com>,
	"Radu Pirea" <radu-nicolae.pirea@nxp.com>,
	"Andreas Färber" <afaerber@suse.de>,
	"Matthias Brugger" <mbrugger@suse.com>
Subject: [PATCH v2 0/2] Add pinctrl support for S32 SoC family
Date: Mon, 28 Nov 2022 13:48:18 +0800	[thread overview]
Message-ID: <20221128054820.1771-1-clin@suse.com> (raw)

Hello,

Here I want to introduce a new patch series, which aims to support IOMUX
functions provided by SIUL2 [System Integration Unit Lite2] on S32 SoCs,
such as S32G2. This series is originally from NXP's implementation on
CodeAurora[1] and it will be required by upstream kernel for supporting
a variety of devices on S32 SoCs which need to config PINMUXs, such as
PHYs and MAC controllers.

Currently, the whole architecture relies on FDTs offered by ATF[3] on
CodeAurora to keep the flexibility of handling multiple S32 platforms since
now S32 clks can be triggered via the ARM SCMI clock protocol and clk IDs/
settings can vary according to different board designs. To ensure that the
driver can work properly, the dt-binding schemas in this patchset are still
required as references.

Thanks,
Chester

Changes in v2:
- Move the "nxp,pins" ID range information from DT to the driver.
- dt-bindings:
  - Fix schema issues.
  - Add descriptions for reg entries.
  - Revise the example.
- Refine the compatible name from "nxp,s32g-..." to "nxp,s32g2-...".
- Fix the copyright format suggested by NXP.

[1] https://source.codeaurora.org/external/autobsps32/linux/tree/drivers/pinctrl/freescale?h=bsp34.0-5.10.120-rt
[2] https://source.codeaurora.org/external/autobsps32/arm-trusted-firmware/tag/?h=bsp34.0-2.5

Chester Lin (2):
  dt-bindings: pinctrl: add schema for NXP S32 SoCs
  pinctrl: add NXP S32 SoC family support

 .../pinctrl/nxp,s32cc-siul2-pinctrl.yaml      |  125 ++
 drivers/pinctrl/freescale/Kconfig             |   16 +
 drivers/pinctrl/freescale/Makefile            |    2 +
 drivers/pinctrl/freescale/pinctrl-s32.h       |   77 ++
 drivers/pinctrl/freescale/pinctrl-s32cc.c     | 1003 +++++++++++++++++
 drivers/pinctrl/freescale/pinctrl-s32g.c      |  773 +++++++++++++
 6 files changed, 1996 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nxp,s32cc-siul2-pinctrl.yaml
 create mode 100644 drivers/pinctrl/freescale/pinctrl-s32.h
 create mode 100644 drivers/pinctrl/freescale/pinctrl-s32cc.c
 create mode 100644 drivers/pinctrl/freescale/pinctrl-s32g.c

-- 
2.37.3


             reply	other threads:[~2022-11-28  5:48 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-28  5:48 Chester Lin [this message]
2022-11-28  5:48 ` [PATCH v2 1/2] dt-bindings: pinctrl: add schema for NXP S32 SoCs Chester Lin
2022-11-29 14:00   ` Andreas Färber
2022-11-29 14:52     ` Chester Lin
2022-11-30 14:58   ` Krzysztof Kozlowski
2022-12-05  6:16     ` Chester Lin
2022-12-05  9:02       ` Krzysztof Kozlowski
2022-12-05 11:05         ` Chester Lin
2022-12-05 13:26           ` Krzysztof Kozlowski
2022-11-28  5:48 ` [PATCH v2 2/2] pinctrl: add NXP S32 SoC family support Chester Lin
2022-11-29 13:40   ` Andreas Färber
2022-12-05  7:06     ` Chester Lin
2022-12-07 22:52   ` Linus Walleij
2022-12-07 23:04   ` Fabio Estevam
2022-12-08 21:37     ` Linus Walleij
2022-12-09  4:38       ` Chester Lin
2022-12-09 11:27         ` Linus Walleij
2022-12-14 23:08           ` Saravana Kannan

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