* Re: [PATCH RESEND v13 char-misc-next 0/2] Add OTP/EEPROM functionality to the PCI1XXXX switch
[not found] <20230620143520.858-1-vaibhaavram.tl@microchip.com>
@ 2023-06-23 8:31 ` Greg KH
2023-07-01 7:08 ` VaibhaavRam.TL
0 siblings, 1 reply; 6+ messages in thread
From: Greg KH @ 2023-06-23 8:31 UTC (permalink / raw)
To: Vaibhaav Ram T.L
Cc: linux-kernel, linux-gpio, arnd, kumaravel.thiagarajan,
tharunkumar.pasumarthi, UNGLinuxDriver, michael
On Tue, Jun 20, 2023 at 08:05:18PM +0530, Vaibhaav Ram T.L wrote:
> Microchip's pci1xxxx is an unmanaged PCIe3.1a switch for consumer,
> industrial, and automotive applications. This switch integrates OTP and
> EEPROM to enable customization of the part in the field. This patch adds
> OTP/EEPROM functionality to the pci1xxxx switch.
> ---
> v12 -> v13:
> - Moved release_sys_lock() from patch#2 to patch#1
This series is not showing up on lore.kernel.org at all, are you sure it
is getting to the mailing lists properly?
thanks,
greg k-h
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH RESEND v13 char-misc-next 0/2] Add OTP/EEPROM functionality to the PCI1XXXX switch
@ 2023-07-01 7:08 Kumaravel Thiagarajan
2023-07-01 7:08 ` [PATCH RESEND v13 char-misc-next 1/2] misc: microchip: pci1xxxx: Add support to read and write into PCI1XXXX OTP via NVMEM sysfs Kumaravel Thiagarajan
2023-07-01 7:08 ` [PATCH RESEND v13 char-misc-next 2/2] misc: microchip: pci1xxxx: Add support to read and write into PCI1XXXX EEPROM " Kumaravel Thiagarajan
0 siblings, 2 replies; 6+ messages in thread
From: Kumaravel Thiagarajan @ 2023-07-01 7:08 UTC (permalink / raw)
To: linux-kernel, linux-gpio
Cc: arnd, gregkh, kumaravel.thiagarajan, tharunkumar.pasumarthi,
UNGLinuxDriver, michael
From: "Vaibhaav Ram T.L" <vaibhaavram.tl@microchip.com>
Microchip's pci1xxxx is an unmanaged PCIe3.1a switch for consumer,
industrial, and automotive applications. This switch integrates OTP and
EEPROM to enable customization of the part in the field. This patch adds
OTP/EEPROM functionality to the pci1xxxx switch.
---
v12 -> v13:
- Moved release_sys_lock() from patch#2 to patch#1
v11 -> v12:
- EEPROM is registered for NVMEM only if EEPROM is responsive
v10 -> v11:
- Fixed error handling during timouts by releasing sys_locks
v9 -> v10:
- Removed unused include header files
- Removed null check for priv pointer
- Removed debug messages
- Returned error during timeouts
- Added corner case checks for offset and count values
v8 -> v9:
- Changed architecture from sysfs bin interface to NVMEM interface
v7 -> v8:
- Fixed error handling in probe function of mchp_pci1xxxx_gp driver
- Added bin attribute groups to eliminate userspace from racing
- Implemented short read and write for OTP/EEPROM
v6 -> v7:
- Handled corner cases such as failure of sysfs bin creation and removal
- Added function to check whether device is responsive
- Removed un-necessary parenthesis
- Added function for repetitive tasks
v5 -> v6:
- Changed architecture from Block interface to sysfs interface
- Replaced busy loops with read_poll_timeout()
v4 -> v5:
- Used proper errno
- Removed un-necessary prints
v3 -> v4:
- Remove extra space, tab, un-necessary casting, paranthesis,
do while(false) loops
- Used read_poll_timeout for polling BUSY_BIT
v2 -> v3:
- Modified commit description to include build issues reported by Kernel
test robot <lkp@intel.com> which are fixed in this patch
v1 -> v2:
- Resolve build issue reported by kernel test robot <lkp@intel.com>
Kumaravel Thiagarajan (2):
misc: microchip: pci1xxxx: Add support to read and write into PCI1XXXX
OTP via NVMEM sysfs
misc: microchip: pci1xxxx: Add support to read and write into PCI1XXXX
EEPROM via NVMEM sysfs
MAINTAINERS | 2 +
drivers/misc/mchp_pci1xxxx/Kconfig | 1 +
drivers/misc/mchp_pci1xxxx/Makefile | 2 +-
.../misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c | 443 ++++++++++++++++++
4 files changed, 447 insertions(+), 1 deletion(-)
create mode 100644 drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH RESEND v13 char-misc-next 1/2] misc: microchip: pci1xxxx: Add support to read and write into PCI1XXXX OTP via NVMEM sysfs
2023-07-01 7:08 [PATCH RESEND v13 char-misc-next 0/2] Add OTP/EEPROM functionality to the PCI1XXXX switch Kumaravel Thiagarajan
@ 2023-07-01 7:08 ` Kumaravel Thiagarajan
2023-07-01 7:08 ` [PATCH RESEND v13 char-misc-next 2/2] misc: microchip: pci1xxxx: Add support to read and write into PCI1XXXX EEPROM " Kumaravel Thiagarajan
1 sibling, 0 replies; 6+ messages in thread
From: Kumaravel Thiagarajan @ 2023-07-01 7:08 UTC (permalink / raw)
To: linux-kernel, linux-gpio
Cc: arnd, gregkh, kumaravel.thiagarajan, tharunkumar.pasumarthi,
UNGLinuxDriver, michael, Vaibhaav Ram T . L
Microchip's pci1xxxx is an unmanaged PCIe3.1a switch for consumer,
industrial, and automotive applications. This switch integrates OTP
and EEPROM to enable customization of the part in the field. This
patch adds support to read and write into PCI1XXXX OTP via NVMEM sysfs.
Co-developed-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
Signed-off-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
Co-developed-by: Vaibhaav Ram T.L <vaibhaavram.tl@microchip.com>
Signed-off-by: Vaibhaav Ram T.L <vaibhaavram.tl@microchip.com>
Signed-off-by: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>
---
MAINTAINERS | 2 +
drivers/misc/mchp_pci1xxxx/Kconfig | 1 +
drivers/misc/mchp_pci1xxxx/Makefile | 2 +-
.../misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c | 303 ++++++++++++++++++
4 files changed, 307 insertions(+), 1 deletion(-)
create mode 100644 drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 250518fc70ff..fd15229569a7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13812,12 +13812,14 @@ F: drivers/nvmem/microchip-otpc.c
F: include/dt-bindings/nvmem/microchip,sama7g5-otpc.h
MICROCHIP PCI1XXXX GP DRIVER
+M: Vaibhaav Ram T.L <vaibhaavram.tl@microchip.com>
M: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>
L: linux-gpio@vger.kernel.org
S: Supported
F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gp.c
F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gp.h
F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c
+F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
MICROCHIP PCI1XXXX I2C DRIVER
M: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
diff --git a/drivers/misc/mchp_pci1xxxx/Kconfig b/drivers/misc/mchp_pci1xxxx/Kconfig
index 4abb47de7219..64e457581fb4 100644
--- a/drivers/misc/mchp_pci1xxxx/Kconfig
+++ b/drivers/misc/mchp_pci1xxxx/Kconfig
@@ -2,6 +2,7 @@ config GP_PCI1XXXX
tristate "Microchip PCI1XXXX PCIe to GPIO Expander + OTP/EEPROM manager"
depends on PCI
depends on GPIOLIB
+ depends on NVMEM_SYSFS
select GPIOLIB_IRQCHIP
select AUXILIARY_BUS
help
diff --git a/drivers/misc/mchp_pci1xxxx/Makefile b/drivers/misc/mchp_pci1xxxx/Makefile
index fc4615cfe28b..ae31251dab37 100644
--- a/drivers/misc/mchp_pci1xxxx/Makefile
+++ b/drivers/misc/mchp_pci1xxxx/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_GP_PCI1XXXX) := mchp_pci1xxxx_gp.o mchp_pci1xxxx_gpio.o
+obj-$(CONFIG_GP_PCI1XXXX) := mchp_pci1xxxx_gp.o mchp_pci1xxxx_gpio.o mchp_pci1xxxx_otpe2p.o
diff --git a/drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c b/drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
new file mode 100644
index 000000000000..d3aa5664f0b0
--- /dev/null
+++ b/drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2022-2023 Microchip Technology Inc.
+// PCI1xxxx OTP/EEPROM driver
+
+#include <linux/auxiliary_bus.h>
+#include <linux/device.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/nvmem-provider.h>
+
+#include "mchp_pci1xxxx_gp.h"
+
+#define AUX_DRIVER_NAME "PCI1xxxxOTPE2P"
+#define OTP_NAME "pci1xxxx_otp"
+
+#define PERI_PF3_SYSTEM_REG_ADDR_BASE 0x2000
+#define PERI_PF3_SYSTEM_REG_LENGTH 0x4000
+
+#define OTP_SIZE_BYTES 8192
+
+#define CONFIG_REG_ADDR_BASE 0
+#define OTP_REG_ADDR_BASE 0x1000
+
+#define MMAP_OTP_OFFSET(x) (OTP_REG_ADDR_BASE + (x))
+#define MMAP_CFG_OFFSET(x) (CONFIG_REG_ADDR_BASE + (x))
+
+#define STATUS_READ_DELAY_US 1
+#define STATUS_READ_TIMEOUT_US 20000
+
+#define OTP_ADDR_HIGH_OFFSET 0x04
+#define OTP_ADDR_LOW_OFFSET 0x08
+#define OTP_PRGM_DATA_OFFSET 0x10
+#define OTP_PRGM_MODE_OFFSET 0x14
+#define OTP_RD_DATA_OFFSET 0x18
+#define OTP_FUNC_CMD_OFFSET 0x20
+#define OTP_CMD_GO_OFFSET 0x28
+#define OTP_PASS_FAIL_OFFSET 0x2C
+#define OTP_STATUS_OFFSET 0x30
+
+#define OTP_FUNC_RD_BIT BIT(0)
+#define OTP_FUNC_PGM_BIT BIT(1)
+#define OTP_CMD_GO_BIT BIT(0)
+#define OTP_STATUS_BUSY_BIT BIT(0)
+#define OTP_PGM_MODE_BYTE_BIT BIT(0)
+#define OTP_FAIL_BIT BIT(0)
+
+#define OTP_PWR_DN_BIT BIT(0)
+#define OTP_PWR_DN_OFFSET 0x00
+
+#define CFG_SYS_LOCK_OFFSET 0xA0
+#define CFG_SYS_LOCK_PF3 BIT(5)
+
+#define BYTE_LOW (GENMASK(7, 0))
+#define BYTE_HIGH (GENMASK(12, 8))
+
+struct pci1xxxx_otp_eeprom_device {
+ struct auxiliary_device *pdev;
+ void __iomem *reg_base;
+ struct nvmem_config nvmem_config_otp;
+ struct nvmem_device *nvmem_otp;
+};
+
+static int set_sys_lock(struct pci1xxxx_otp_eeprom_device *priv)
+{
+ void __iomem *sys_lock = priv->reg_base +
+ MMAP_CFG_OFFSET(CFG_SYS_LOCK_OFFSET);
+ u8 data;
+
+ writel(CFG_SYS_LOCK_PF3, sys_lock);
+ data = readl(sys_lock);
+ if (data != CFG_SYS_LOCK_PF3)
+ return -EPERM;
+
+ return 0;
+}
+
+static void release_sys_lock(struct pci1xxxx_otp_eeprom_device *priv)
+{
+ void __iomem *sys_lock = priv->reg_base +
+ MMAP_CFG_OFFSET(CFG_SYS_LOCK_OFFSET);
+ writel(0, sys_lock);
+}
+
+static void otp_device_set_address(struct pci1xxxx_otp_eeprom_device *priv,
+ u16 address)
+{
+ u16 lo, hi;
+
+ lo = address & BYTE_LOW;
+ hi = (address & BYTE_HIGH) >> 8;
+ writew(lo, priv->reg_base + MMAP_OTP_OFFSET(OTP_ADDR_LOW_OFFSET));
+ writew(hi, priv->reg_base + MMAP_OTP_OFFSET(OTP_ADDR_HIGH_OFFSET));
+}
+
+static int pci1xxxx_otp_read(void *priv_t, unsigned int off,
+ void *buf_t, size_t count)
+{
+ struct pci1xxxx_otp_eeprom_device *priv = priv_t;
+ void __iomem *rb = priv->reg_base;
+ char *buf = buf_t;
+ u32 regval;
+ u32 byte;
+ int ret;
+ u8 data;
+
+ if (off >= priv->nvmem_config_otp.size)
+ return -EFAULT;
+
+ if ((off + count) > priv->nvmem_config_otp.size)
+ count = priv->nvmem_config_otp.size - off;
+
+ ret = set_sys_lock(priv);
+ if (ret)
+ return ret;
+
+ for (byte = 0; byte < count; byte++) {
+ otp_device_set_address(priv, (u16)(off + byte));
+ data = readl(rb + MMAP_OTP_OFFSET(OTP_FUNC_CMD_OFFSET));
+ writel(data | OTP_FUNC_RD_BIT,
+ rb + MMAP_OTP_OFFSET(OTP_FUNC_CMD_OFFSET));
+ data = readl(rb + MMAP_OTP_OFFSET(OTP_CMD_GO_OFFSET));
+ writel(data | OTP_CMD_GO_BIT,
+ rb + MMAP_OTP_OFFSET(OTP_CMD_GO_OFFSET));
+
+ ret = read_poll_timeout(readl, regval,
+ !(regval & OTP_STATUS_BUSY_BIT),
+ STATUS_READ_DELAY_US,
+ STATUS_READ_TIMEOUT_US, true,
+ rb + MMAP_OTP_OFFSET(OTP_STATUS_OFFSET));
+
+ data = readl(rb + MMAP_OTP_OFFSET(OTP_PASS_FAIL_OFFSET));
+ if (ret < 0 || data & OTP_FAIL_BIT) {
+ ret = -EIO;
+ goto error;
+ }
+
+ buf[byte] = readl(rb + MMAP_OTP_OFFSET(OTP_RD_DATA_OFFSET));
+ }
+ ret = byte;
+error:
+ release_sys_lock(priv);
+ return ret;
+}
+
+static int pci1xxxx_otp_write(void *priv_t, unsigned int off,
+ void *value_t, size_t count)
+{
+ struct pci1xxxx_otp_eeprom_device *priv = priv_t;
+ void __iomem *rb = priv->reg_base;
+ char *value = value_t;
+ u32 regval;
+ u32 byte;
+ int ret;
+ u8 data;
+
+ if (off >= priv->nvmem_config_otp.size)
+ return -EFAULT;
+
+ if ((off + count) > priv->nvmem_config_otp.size)
+ count = priv->nvmem_config_otp.size - off;
+
+ ret = set_sys_lock(priv);
+ if (ret)
+ return ret;
+
+ for (byte = 0; byte < count; byte++) {
+ otp_device_set_address(priv, (u16)(off + byte));
+
+ /*
+ * Set OTP_PGM_MODE_BYTE command bit in OTP_PRGM_MODE register
+ * to enable Byte programming
+ */
+ data = readl(rb + MMAP_OTP_OFFSET(OTP_PRGM_MODE_OFFSET));
+ writel(data | OTP_PGM_MODE_BYTE_BIT,
+ rb + MMAP_OTP_OFFSET(OTP_PRGM_MODE_OFFSET));
+ writel(*(value + byte), rb + MMAP_OTP_OFFSET(OTP_PRGM_DATA_OFFSET));
+ data = readl(rb + MMAP_OTP_OFFSET(OTP_FUNC_CMD_OFFSET));
+ writel(data | OTP_FUNC_PGM_BIT,
+ rb + MMAP_OTP_OFFSET(OTP_FUNC_CMD_OFFSET));
+ data = readl(rb + MMAP_OTP_OFFSET(OTP_CMD_GO_OFFSET));
+ writel(data | OTP_CMD_GO_BIT,
+ rb + MMAP_OTP_OFFSET(OTP_CMD_GO_OFFSET));
+
+ ret = read_poll_timeout(readl, regval,
+ !(regval & OTP_STATUS_BUSY_BIT),
+ STATUS_READ_DELAY_US,
+ STATUS_READ_TIMEOUT_US, true,
+ rb + MMAP_OTP_OFFSET(OTP_STATUS_OFFSET));
+
+ data = readl(rb + MMAP_OTP_OFFSET(OTP_PASS_FAIL_OFFSET));
+ if (ret < 0 || data & OTP_FAIL_BIT) {
+ ret = -EIO;
+ goto error;
+ }
+ }
+ ret = byte;
+error:
+ release_sys_lock(priv);
+ return ret;
+}
+
+static int pci1xxxx_otp_eeprom_probe(struct auxiliary_device *aux_dev,
+ const struct auxiliary_device_id *id)
+{
+ struct auxiliary_device_wrapper *aux_dev_wrapper;
+ struct pci1xxxx_otp_eeprom_device *priv;
+ struct gp_aux_data_type *pdata;
+ int ret;
+ u8 data;
+
+ aux_dev_wrapper = container_of(aux_dev, struct auxiliary_device_wrapper,
+ aux_dev);
+ pdata = &aux_dev_wrapper->gp_aux_data;
+ if (!pdata)
+ return -EINVAL;
+
+ priv = devm_kzalloc(&aux_dev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->pdev = aux_dev;
+
+ if (!devm_request_mem_region(&aux_dev->dev, pdata->region_start +
+ PERI_PF3_SYSTEM_REG_ADDR_BASE,
+ PERI_PF3_SYSTEM_REG_LENGTH,
+ aux_dev->name))
+ return -ENOMEM;
+
+ priv->reg_base = devm_ioremap(&aux_dev->dev, pdata->region_start +
+ PERI_PF3_SYSTEM_REG_ADDR_BASE,
+ PERI_PF3_SYSTEM_REG_LENGTH);
+ if (!priv->reg_base)
+ return -ENOMEM;
+
+ ret = set_sys_lock(priv);
+ if (ret)
+ return ret;
+
+ /* Set OTP_PWR_DN to 0 to make OTP Operational */
+ data = readl(priv->reg_base + MMAP_OTP_OFFSET(OTP_PWR_DN_OFFSET));
+ writel(data & ~OTP_PWR_DN_BIT,
+ priv->reg_base + MMAP_OTP_OFFSET(OTP_PWR_DN_OFFSET));
+
+ dev_set_drvdata(&aux_dev->dev, priv);
+
+ release_sys_lock(priv);
+
+ priv->nvmem_config_otp.type = NVMEM_TYPE_OTP;
+ priv->nvmem_config_otp.name = OTP_NAME;
+ priv->nvmem_config_otp.dev = &aux_dev->dev;
+ priv->nvmem_config_otp.owner = THIS_MODULE;
+ priv->nvmem_config_otp.reg_read = pci1xxxx_otp_read;
+ priv->nvmem_config_otp.reg_write = pci1xxxx_otp_write;
+ priv->nvmem_config_otp.priv = priv;
+ priv->nvmem_config_otp.stride = 1;
+ priv->nvmem_config_otp.word_size = 1;
+ priv->nvmem_config_otp.size = OTP_SIZE_BYTES;
+
+ priv->nvmem_otp = devm_nvmem_register(&aux_dev->dev,
+ &priv->nvmem_config_otp);
+ if (!priv->nvmem_otp)
+ return -ENOMEM;
+
+ return ret;
+}
+
+static void pci1xxxx_otp_eeprom_remove(struct auxiliary_device *aux_dev)
+{
+ struct pci1xxxx_otp_eeprom_device *priv;
+ void __iomem *sys_lock;
+
+ priv = dev_get_drvdata(&aux_dev->dev);
+ sys_lock = priv->reg_base + MMAP_CFG_OFFSET(CFG_SYS_LOCK_OFFSET);
+ writel(CFG_SYS_LOCK_PF3, sys_lock);
+
+ /* Shut down OTP */
+ writel(OTP_PWR_DN_BIT,
+ priv->reg_base + MMAP_OTP_OFFSET(OTP_PWR_DN_OFFSET));
+
+ writel(0, sys_lock);
+}
+
+static const struct auxiliary_device_id pci1xxxx_otp_eeprom_auxiliary_id_table[] = {
+ {.name = "mchp_pci1xxxx_gp.gp_otp_e2p"},
+ {},
+};
+MODULE_DEVICE_TABLE(auxiliary, pci1xxxx_otp_eeprom_auxiliary_id_table);
+
+static struct auxiliary_driver pci1xxxx_otp_eeprom_driver = {
+ .driver = {
+ .name = AUX_DRIVER_NAME,
+ },
+ .probe = pci1xxxx_otp_eeprom_probe,
+ .remove = pci1xxxx_otp_eeprom_remove,
+ .id_table = pci1xxxx_otp_eeprom_auxiliary_id_table
+};
+module_auxiliary_driver(pci1xxxx_otp_eeprom_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>");
+MODULE_AUTHOR("Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>");
+MODULE_AUTHOR("Vaibhaav Ram T.L <vaibhaavram.tl@microchip.com>");
+MODULE_DESCRIPTION("Microchip Technology Inc. PCI1xxxx OTP EEPROM Programmer");
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH RESEND v13 char-misc-next 2/2] misc: microchip: pci1xxxx: Add support to read and write into PCI1XXXX EEPROM via NVMEM sysfs
2023-07-01 7:08 [PATCH RESEND v13 char-misc-next 0/2] Add OTP/EEPROM functionality to the PCI1XXXX switch Kumaravel Thiagarajan
2023-07-01 7:08 ` [PATCH RESEND v13 char-misc-next 1/2] misc: microchip: pci1xxxx: Add support to read and write into PCI1XXXX OTP via NVMEM sysfs Kumaravel Thiagarajan
@ 2023-07-01 7:08 ` Kumaravel Thiagarajan
1 sibling, 0 replies; 6+ messages in thread
From: Kumaravel Thiagarajan @ 2023-07-01 7:08 UTC (permalink / raw)
To: linux-kernel, linux-gpio
Cc: arnd, gregkh, kumaravel.thiagarajan, tharunkumar.pasumarthi,
UNGLinuxDriver, michael, Vaibhaav Ram T . L
Microchip's pci1xxxx is an unmanaged PCIe3.1a switch for consumer,
industrial, and automotive applications. This switch integrates OTP
and EEPROM to enable customization of the part in the field.
This patch adds support to read and write into PCI1XXXX EEPROM
via NVMEM sysfs.
Co-developed-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
Signed-off-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
Co-developed-by: Vaibhaav Ram T.L <vaibhaavram.tl@microchip.com>
Signed-off-by: Vaibhaav Ram T.L <vaibhaavram.tl@microchip.com>
Signed-off-by: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>
---
.../misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c | 140 ++++++++++++++++++
1 file changed, 140 insertions(+)
diff --git a/drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c b/drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
index d3aa5664f0b0..3d3d1578119a 100644
--- a/drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
+++ b/drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
@@ -11,19 +11,30 @@
#include "mchp_pci1xxxx_gp.h"
#define AUX_DRIVER_NAME "PCI1xxxxOTPE2P"
+#define EEPROM_NAME "pci1xxxx_eeprom"
#define OTP_NAME "pci1xxxx_otp"
#define PERI_PF3_SYSTEM_REG_ADDR_BASE 0x2000
#define PERI_PF3_SYSTEM_REG_LENGTH 0x4000
+#define EEPROM_SIZE_BYTES 8192
#define OTP_SIZE_BYTES 8192
#define CONFIG_REG_ADDR_BASE 0
+#define EEPROM_REG_ADDR_BASE 0x0E00
#define OTP_REG_ADDR_BASE 0x1000
#define MMAP_OTP_OFFSET(x) (OTP_REG_ADDR_BASE + (x))
+#define MMAP_EEPROM_OFFSET(x) (EEPROM_REG_ADDR_BASE + (x))
#define MMAP_CFG_OFFSET(x) (CONFIG_REG_ADDR_BASE + (x))
+#define EEPROM_CMD_REG 0x00
+#define EEPROM_DATA_REG 0x04
+
+#define EEPROM_CMD_EPC_WRITE (BIT(29) | BIT(28))
+#define EEPROM_CMD_EPC_TIMEOUT_BIT BIT(17)
+#define EEPROM_CMD_EPC_BUSY_BIT BIT(31)
+
#define STATUS_READ_DELAY_US 1
#define STATUS_READ_TIMEOUT_US 20000
@@ -56,6 +67,8 @@
struct pci1xxxx_otp_eeprom_device {
struct auxiliary_device *pdev;
void __iomem *reg_base;
+ struct nvmem_config nvmem_config_eeprom;
+ struct nvmem_device *nvmem_eeprom;
struct nvmem_config nvmem_config_otp;
struct nvmem_device *nvmem_otp;
};
@@ -81,6 +94,115 @@ static void release_sys_lock(struct pci1xxxx_otp_eeprom_device *priv)
writel(0, sys_lock);
}
+static bool is_eeprom_responsive(struct pci1xxxx_otp_eeprom_device *priv)
+{
+ void __iomem *rb = priv->reg_base;
+ u32 regval;
+ int ret;
+
+ writel(EEPROM_CMD_EPC_TIMEOUT_BIT,
+ rb + MMAP_EEPROM_OFFSET(EEPROM_CMD_REG));
+ writel(EEPROM_CMD_EPC_BUSY_BIT,
+ rb + MMAP_EEPROM_OFFSET(EEPROM_CMD_REG));
+
+ /* Wait for the EPC_BUSY bit to get cleared or timeout bit to get set*/
+ ret = read_poll_timeout(readl, regval, !(regval & EEPROM_CMD_EPC_BUSY_BIT),
+ STATUS_READ_DELAY_US, STATUS_READ_TIMEOUT_US,
+ true, rb + MMAP_EEPROM_OFFSET(EEPROM_CMD_REG));
+
+ /* Return failure if either of software or hardware timeouts happen */
+ if (ret < 0 || (!ret && (regval & EEPROM_CMD_EPC_TIMEOUT_BIT)))
+ return false;
+
+ return true;
+}
+
+static int pci1xxxx_eeprom_read(void *priv_t, unsigned int off,
+ void *buf_t, size_t count)
+{
+ struct pci1xxxx_otp_eeprom_device *priv = priv_t;
+ void __iomem *rb = priv->reg_base;
+ char *buf = buf_t;
+ u32 regval;
+ u32 byte;
+ int ret;
+
+ if (off >= priv->nvmem_config_eeprom.size)
+ return -EFAULT;
+
+ if ((off + count) > priv->nvmem_config_eeprom.size)
+ count = priv->nvmem_config_eeprom.size - off;
+
+ ret = set_sys_lock(priv);
+ if (ret)
+ return ret;
+
+ for (byte = 0; byte < count; byte++) {
+ writel(EEPROM_CMD_EPC_BUSY_BIT | (off + byte), rb +
+ MMAP_EEPROM_OFFSET(EEPROM_CMD_REG));
+
+ ret = read_poll_timeout(readl, regval,
+ !(regval & EEPROM_CMD_EPC_BUSY_BIT),
+ STATUS_READ_DELAY_US,
+ STATUS_READ_TIMEOUT_US, true,
+ rb + MMAP_EEPROM_OFFSET(EEPROM_CMD_REG));
+ if (ret < 0 || (!ret && (regval & EEPROM_CMD_EPC_TIMEOUT_BIT))) {
+ ret = -EIO;
+ goto error;
+ }
+
+ buf[byte] = readl(rb + MMAP_EEPROM_OFFSET(EEPROM_DATA_REG));
+ }
+ ret = byte;
+error:
+ release_sys_lock(priv);
+ return ret;
+}
+
+static int pci1xxxx_eeprom_write(void *priv_t, unsigned int off,
+ void *value_t, size_t count)
+{
+ struct pci1xxxx_otp_eeprom_device *priv = priv_t;
+ void __iomem *rb = priv->reg_base;
+ char *value = value_t;
+ u32 regval;
+ u32 byte;
+ int ret;
+
+ if (off >= priv->nvmem_config_eeprom.size)
+ return -EFAULT;
+
+ if ((off + count) > priv->nvmem_config_eeprom.size)
+ count = priv->nvmem_config_eeprom.size - off;
+
+ ret = set_sys_lock(priv);
+ if (ret)
+ return ret;
+
+ for (byte = 0; byte < count; byte++) {
+ writel(*(value + byte), rb + MMAP_EEPROM_OFFSET(EEPROM_DATA_REG));
+ regval = EEPROM_CMD_EPC_TIMEOUT_BIT | EEPROM_CMD_EPC_WRITE |
+ (off + byte);
+ writel(regval, rb + MMAP_EEPROM_OFFSET(EEPROM_CMD_REG));
+ writel(EEPROM_CMD_EPC_BUSY_BIT | regval,
+ rb + MMAP_EEPROM_OFFSET(EEPROM_CMD_REG));
+
+ ret = read_poll_timeout(readl, regval,
+ !(regval & EEPROM_CMD_EPC_BUSY_BIT),
+ STATUS_READ_DELAY_US,
+ STATUS_READ_TIMEOUT_US, true,
+ rb + MMAP_EEPROM_OFFSET(EEPROM_CMD_REG));
+ if (ret < 0 || (!ret && (regval & EEPROM_CMD_EPC_TIMEOUT_BIT))) {
+ ret = -EIO;
+ goto error;
+ }
+ }
+ ret = byte;
+error:
+ release_sys_lock(priv);
+ return ret;
+}
+
static void otp_device_set_address(struct pci1xxxx_otp_eeprom_device *priv,
u16 address)
{
@@ -243,6 +365,24 @@ static int pci1xxxx_otp_eeprom_probe(struct auxiliary_device *aux_dev,
dev_set_drvdata(&aux_dev->dev, priv);
+ if (is_eeprom_responsive(priv)) {
+ priv->nvmem_config_eeprom.type = NVMEM_TYPE_EEPROM;
+ priv->nvmem_config_eeprom.name = EEPROM_NAME;
+ priv->nvmem_config_eeprom.dev = &aux_dev->dev;
+ priv->nvmem_config_eeprom.owner = THIS_MODULE;
+ priv->nvmem_config_eeprom.reg_read = pci1xxxx_eeprom_read;
+ priv->nvmem_config_eeprom.reg_write = pci1xxxx_eeprom_write;
+ priv->nvmem_config_eeprom.priv = priv;
+ priv->nvmem_config_eeprom.stride = 1;
+ priv->nvmem_config_eeprom.word_size = 1;
+ priv->nvmem_config_eeprom.size = EEPROM_SIZE_BYTES;
+
+ priv->nvmem_eeprom = devm_nvmem_register(&aux_dev->dev,
+ &priv->nvmem_config_eeprom);
+ if (!priv->nvmem_eeprom)
+ return -ENOMEM;
+ }
+
release_sys_lock(priv);
priv->nvmem_config_otp.type = NVMEM_TYPE_OTP;
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* RE: [PATCH RESEND v13 char-misc-next 0/2] Add OTP/EEPROM functionality to the PCI1XXXX switch
2023-06-23 8:31 ` [PATCH RESEND v13 char-misc-next 0/2] Add OTP/EEPROM functionality to the PCI1XXXX switch Greg KH
@ 2023-07-01 7:08 ` VaibhaavRam.TL
2023-07-01 7:18 ` Greg KH
0 siblings, 1 reply; 6+ messages in thread
From: VaibhaavRam.TL @ 2023-07-01 7:08 UTC (permalink / raw)
To: gregkh
Cc: linux-kernel, linux-gpio, arnd, Kumaravel.Thiagarajan,
Tharunkumar.Pasumarthi, UNGLinuxDriver, michael
On Tue, Jun 20, 2023 at 08:05:18PM +0530, Vaibhaav Ram T.L wrote:
>> Microchip's pci1xxxx is an unmanaged PCIe3.1a switch for consumer,
>> industrial, and automotive applications. This switch integrates OTP
>> and EEPROM to enable customization of the part in the field. This
>> patch adds OTP/EEPROM functionality to the pci1xxxx switch.
>> ---
>> v12 -> v13:
>> - Moved release_sys_lock() from patch#2 to patch#1
>
>This series is not showing up on lore.kernel.org at all, are you sure it is getting to >the mailing lists properly?
>
>thanks,
>
>greg k-h
Hi Greg. I too can't find the root cause for this issue.
I have used get_maintainer.pl script to get the Maintainers list and it looks like this:
Arnd Bergmann <arnd@arndb.de> (supporter:CHAR and MISC DRIVERS) Greg Kroah-Hartman <gregkh@linuxfoundation.org> (supporter:CHAR and MISC DRIVERS,commit_signer:2/3=67%) "Vaibhaav Ram T.L" <vaibhaavram.tl@microchip.com> (supporter:MICROCHIP PCI1XXXX GP DRIVER,commit_signer:1/3=33%) Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com> (supporter:MICROCHIP PCI1XXXX GP DRIVER,commit_signer:3/3=100%,authored:3/3=100%,added_lines:15/15=100%,removed_lines:1/1=100%,added_lines:3/3=100%,removed_lines:2/2=100%)
Tharun Kumar P <tharunkumar.pasumarthi@microchip.com> (commit_signer:1/3=33%) linux-kernel@vger.kernel.org (open list) linux-gpio@vger.kernel.org (open list:MICROCHIP PCI1XXXX GP DRIVER)'
This is the command I have used:
git send-email --to "linux-kernel@vger.kernel.org" --to "linux-gpio@vger.kernel.org" --cc "arnd@arndb.de" --cc "gregkh@linuxfoundation.org" --cc "kumaravel.thiagarajan@microchip.com" --cc "tharunkumar.pasumarthi@microchip.com" --cc "UNGLinuxDriver@microchip.com" --cc "michael@walle.cc" *.patch
Is there anything am I missing?
As of now, I have sent Patch V13 from Kumar's email id. Kindly check.
Sorry for inconvenience
Thanks
Vaibhaav Ram
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH RESEND v13 char-misc-next 0/2] Add OTP/EEPROM functionality to the PCI1XXXX switch
2023-07-01 7:08 ` VaibhaavRam.TL
@ 2023-07-01 7:18 ` Greg KH
0 siblings, 0 replies; 6+ messages in thread
From: Greg KH @ 2023-07-01 7:18 UTC (permalink / raw)
To: VaibhaavRam.TL
Cc: linux-kernel, linux-gpio, arnd, Kumaravel.Thiagarajan,
Tharunkumar.Pasumarthi, UNGLinuxDriver, michael
On Sat, Jul 01, 2023 at 07:08:44AM +0000, VaibhaavRam.TL@microchip.com wrote:
> On Tue, Jun 20, 2023 at 08:05:18PM +0530, Vaibhaav Ram T.L wrote:
> >> Microchip's pci1xxxx is an unmanaged PCIe3.1a switch for consumer,
> >> industrial, and automotive applications. This switch integrates OTP
> >> and EEPROM to enable customization of the part in the field. This
> >> patch adds OTP/EEPROM functionality to the pci1xxxx switch.
> >> ---
> >> v12 -> v13:
> >> - Moved release_sys_lock() from patch#2 to patch#1
> >
> >This series is not showing up on lore.kernel.org at all, are you sure it is getting to >the mailing lists properly?
> >
> >thanks,
> >
> >greg k-h
>
> Hi Greg. I too can't find the root cause for this issue.
>
> I have used get_maintainer.pl script to get the Maintainers list and it looks like this:
>
> Arnd Bergmann <arnd@arndb.de> (supporter:CHAR and MISC DRIVERS) Greg Kroah-Hartman <gregkh@linuxfoundation.org> (supporter:CHAR and MISC DRIVERS,commit_signer:2/3=67%) "Vaibhaav Ram T.L" <vaibhaavram.tl@microchip.com> (supporter:MICROCHIP PCI1XXXX GP DRIVER,commit_signer:1/3=33%) Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com> (supporter:MICROCHIP PCI1XXXX GP DRIVER,commit_signer:3/3=100%,authored:3/3=100%,added_lines:15/15=100%,removed_lines:1/1=100%,added_lines:3/3=100%,removed_lines:2/2=100%)
> Tharun Kumar P <tharunkumar.pasumarthi@microchip.com> (commit_signer:1/3=33%) linux-kernel@vger.kernel.org (open list) linux-gpio@vger.kernel.org (open list:MICROCHIP PCI1XXXX GP DRIVER)'
>
> This is the command I have used:
> git send-email --to "linux-kernel@vger.kernel.org" --to "linux-gpio@vger.kernel.org" --cc "arnd@arndb.de" --cc "gregkh@linuxfoundation.org" --cc "kumaravel.thiagarajan@microchip.com" --cc "tharunkumar.pasumarthi@microchip.com" --cc "UNGLinuxDriver@microchip.com" --cc "michael@walle.cc" *.patch
>
> Is there anything am I missing?
>
> As of now, I have sent Patch V13 from Kumar's email id. Kindly check.
> Sorry for inconvenience
This email shows up fine, and so did your new resend, thanks!
greg k-h
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-07-01 7:18 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-07-01 7:08 [PATCH RESEND v13 char-misc-next 0/2] Add OTP/EEPROM functionality to the PCI1XXXX switch Kumaravel Thiagarajan
2023-07-01 7:08 ` [PATCH RESEND v13 char-misc-next 1/2] misc: microchip: pci1xxxx: Add support to read and write into PCI1XXXX OTP via NVMEM sysfs Kumaravel Thiagarajan
2023-07-01 7:08 ` [PATCH RESEND v13 char-misc-next 2/2] misc: microchip: pci1xxxx: Add support to read and write into PCI1XXXX EEPROM " Kumaravel Thiagarajan
[not found] <20230620143520.858-1-vaibhaavram.tl@microchip.com>
2023-06-23 8:31 ` [PATCH RESEND v13 char-misc-next 0/2] Add OTP/EEPROM functionality to the PCI1XXXX switch Greg KH
2023-07-01 7:08 ` VaibhaavRam.TL
2023-07-01 7:18 ` Greg KH
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