Re: [PATCH RESEND v13 char-misc-next 0/2] Add OTP/EEPROM functionality to the PCI1XXXX switch

Re: [PATCH RESEND v13 char-misc-next 0/2] Add OTP/EEPROM functionality to the PCI1XXXX switch

[Greg KH]

On Tue, Jun 20, 2023 at 08:05:18PM +0530, Vaibhaav Ram T.L wrote:
> Microchip's pci1xxxx is an unmanaged PCIe3.1a switch for consumer,
> industrial, and automotive applications. This switch integrates OTP and
> EEPROM to enable customization of the part in the field. This patch adds
> OTP/EEPROM functionality to the pci1xxxx switch.
> ---
> v12 -> v13:
> - Moved release_sys_lock() from patch#2 to patch#1

This series is not showing up on lore.kernel.org at all, are you sure it
is getting to the mailing lists properly?

thanks,

greg k-h

[PATCH RESEND v13 char-misc-next 0/2] Add OTP/EEPROM functionality to the PCI1XXXX switch

[Kumaravel Thiagarajan]

From: "Vaibhaav Ram T.L" <vaibhaavram.tl@microchip.com>

Microchip's pci1xxxx is an unmanaged PCIe3.1a switch for consumer,
industrial, and automotive applications. This switch integrates OTP and
EEPROM to enable customization of the part in the field. This patch adds
OTP/EEPROM functionality to the pci1xxxx switch.
---
v12 -> v13:
- Moved release_sys_lock() from patch#2 to patch#1

v11 -> v12:
- EEPROM is registered for NVMEM only if EEPROM is responsive

v10 -> v11:
- Fixed error handling during timouts by releasing sys_locks

v9 -> v10:
- Removed unused include header files
- Removed null check for priv pointer
- Removed debug messages
- Returned error during timeouts
- Added corner case checks for offset and count values

v8 -> v9:
- Changed architecture from sysfs bin interface to NVMEM interface

v7 -> v8:
- Fixed error handling in probe function of mchp_pci1xxxx_gp driver
- Added bin attribute groups to eliminate userspace from racing
- Implemented short read and write for OTP/EEPROM

v6 -> v7:
- Handled corner cases such as failure of sysfs bin creation and removal
- Added function to check whether device is responsive
- Removed un-necessary parenthesis
- Added function for repetitive tasks

v5 -> v6:
- Changed architecture from Block interface to sysfs interface
- Replaced busy loops with read_poll_timeout()

v4 -> v5:
- Used proper errno
- Removed un-necessary prints

v3 -> v4:
- Remove extra space, tab, un-necessary casting, paranthesis,
  do while(false) loops
- Used read_poll_timeout for polling BUSY_BIT

v2 -> v3:
- Modified commit description to include build issues reported by Kernel
  test robot <lkp@intel.com> which are fixed in this patch

v1 -> v2:
- Resolve build issue reported by kernel test robot <lkp@intel.com>

Kumaravel Thiagarajan (2):
  misc: microchip: pci1xxxx: Add support to read and write into PCI1XXXX
    OTP via NVMEM sysfs
  misc: microchip: pci1xxxx: Add support to read and write into PCI1XXXX
    EEPROM via NVMEM sysfs

 MAINTAINERS                                   |   2 +
 drivers/misc/mchp_pci1xxxx/Kconfig            |   1 +
 drivers/misc/mchp_pci1xxxx/Makefile           |   2 +-
 .../misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c | 443 ++++++++++++++++++
 4 files changed, 447 insertions(+), 1 deletion(-)
 create mode 100644 drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

-- 
2.34.1

RE: [PATCH RESEND v13 char-misc-next 0/2] Add OTP/EEPROM functionality to the PCI1XXXX switch

[VaibhaavRam.TL]

On Tue, Jun 20, 2023 at 08:05:18PM +0530, Vaibhaav Ram T.L wrote:
>> Microchip's pci1xxxx is an unmanaged PCIe3.1a switch for consumer, 
>> industrial, and automotive applications. This switch integrates OTP 
>> and EEPROM to enable customization of the part in the field. This 
>> patch adds OTP/EEPROM functionality to the pci1xxxx switch.
>> ---
>> v12 -> v13:
>> - Moved release_sys_lock() from patch#2 to patch#1
>
>This series is not showing up on lore.kernel.org at all, are you sure it is getting to >the mailing lists properly?
>
>thanks,
>
>greg k-h

Hi Greg. I too can't find the root cause for this issue. 

I have used get_maintainer.pl script to get the Maintainers list and it looks like this:

Arnd Bergmann <arnd@arndb.de> (supporter:CHAR and MISC DRIVERS) Greg Kroah-Hartman <gregkh@linuxfoundation.org> (supporter:CHAR and MISC DRIVERS,commit_signer:2/3=67%) "Vaibhaav Ram T.L" <vaibhaavram.tl@microchip.com> (supporter:MICROCHIP PCI1XXXX GP DRIVER,commit_signer:1/3=33%) Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com> (supporter:MICROCHIP PCI1XXXX GP DRIVER,commit_signer:3/3=100%,authored:3/3=100%,added_lines:15/15=100%,removed_lines:1/1=100%,added_lines:3/3=100%,removed_lines:2/2=100%)
Tharun Kumar P <tharunkumar.pasumarthi@microchip.com> (commit_signer:1/3=33%) linux-kernel@vger.kernel.org (open list) linux-gpio@vger.kernel.org (open list:MICROCHIP PCI1XXXX GP DRIVER)'

This is the command I have used: 
git send-email --to "linux-kernel@vger.kernel.org" --to "linux-gpio@vger.kernel.org" --cc "arnd@arndb.de" --cc "gregkh@linuxfoundation.org" --cc "kumaravel.thiagarajan@microchip.com" --cc "tharunkumar.pasumarthi@microchip.com" --cc "UNGLinuxDriver@microchip.com" --cc "michael@walle.cc" *.patch

Is there anything am I missing?

As of now, I have sent Patch V13 from Kumar's email id. Kindly check.
Sorry for inconvenience

Thanks
Vaibhaav Ram

Re: [PATCH RESEND v13 char-misc-next 0/2] Add OTP/EEPROM functionality to the PCI1XXXX switch

[Greg KH]

On Sat, Jul 01, 2023 at 07:08:44AM +0000, VaibhaavRam.TL@microchip.com wrote:
> On Tue, Jun 20, 2023 at 08:05:18PM +0530, Vaibhaav Ram T.L wrote:
> >> Microchip's pci1xxxx is an unmanaged PCIe3.1a switch for consumer, 
> >> industrial, and automotive applications. This switch integrates OTP 
> >> and EEPROM to enable customization of the part in the field. This 
> >> patch adds OTP/EEPROM functionality to the pci1xxxx switch.
> >> ---
> >> v12 -> v13:
> >> - Moved release_sys_lock() from patch#2 to patch#1
> >
> >This series is not showing up on lore.kernel.org at all, are you sure it is getting to >the mailing lists properly?
> >
> >thanks,
> >
> >greg k-h
> 
> Hi Greg. I too can't find the root cause for this issue. 
> 
> I have used get_maintainer.pl script to get the Maintainers list and it looks like this:
> 
> Arnd Bergmann <arnd@arndb.de> (supporter:CHAR and MISC DRIVERS) Greg Kroah-Hartman <gregkh@linuxfoundation.org> (supporter:CHAR and MISC DRIVERS,commit_signer:2/3=67%) "Vaibhaav Ram T.L" <vaibhaavram.tl@microchip.com> (supporter:MICROCHIP PCI1XXXX GP DRIVER,commit_signer:1/3=33%) Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com> (supporter:MICROCHIP PCI1XXXX GP DRIVER,commit_signer:3/3=100%,authored:3/3=100%,added_lines:15/15=100%,removed_lines:1/1=100%,added_lines:3/3=100%,removed_lines:2/2=100%)
> Tharun Kumar P <tharunkumar.pasumarthi@microchip.com> (commit_signer:1/3=33%) linux-kernel@vger.kernel.org (open list) linux-gpio@vger.kernel.org (open list:MICROCHIP PCI1XXXX GP DRIVER)'
> 
> This is the command I have used: 
> git send-email --to "linux-kernel@vger.kernel.org" --to "linux-gpio@vger.kernel.org" --cc "arnd@arndb.de" --cc "gregkh@linuxfoundation.org" --cc "kumaravel.thiagarajan@microchip.com" --cc "tharunkumar.pasumarthi@microchip.com" --cc "UNGLinuxDriver@microchip.com" --cc "michael@walle.cc" *.patch
> 
> Is there anything am I missing?
> 
> As of now, I have sent Patch V13 from Kumar's email id. Kindly check.
> Sorry for inconvenience

This email shows up fine, and so did your new resend, thanks!

greg k-h