From: Herve Codina <herve.codina@bootlin.com>
To: Herve Codina <herve.codina@bootlin.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Andrew Lunn <andrew@lunn.ch>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>, Lee Jones <lee@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
Qiang Zhao <qiang.zhao@nxp.com>, Li Yang <leoyang.li@nxp.com>,
Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>, Jaroslav Kysela <perex@perex.cz>,
Takashi Iwai <tiwai@suse.com>,
Shengjiu Wang <shengjiu.wang@gmail.com>,
Xiubo Li <Xiubo.Lee@gmail.com>,
Fabio Estevam <festevam@gmail.com>,
Nicolin Chen <nicoleotsuka@gmail.com>,
Christophe Leroy <christophe.leroy@csgroup.eu>
Cc: netdev@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
alsa-devel@alsa-project.org,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Subject: [PATCH 12/26] soc: fsl: cpm1: qmc: Split Tx and Rx TSA entries setup
Date: Tue, 25 Jul 2023 11:23:48 +0200 [thread overview]
Message-ID: <20230725092417.43706-13-herve.codina@bootlin.com> (raw)
In-Reply-To: <20230725092417.43706-1-herve.codina@bootlin.com>
The Tx and Rx entries for a given channel are set in one function.
In order to modify Rx entries and Tx entries independently of one other,
split this function in one for the Rx part and one for the Tx part.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
drivers/soc/fsl/qe/qmc.c | 49 ++++++++++++++++++++++++++++------------
1 file changed, 35 insertions(+), 14 deletions(-)
diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index e19782808f5b..d02acbc1d7e1 100644
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -610,14 +610,14 @@ static int qmc_chan_setup_tsa_64rxtx(struct qmc_chan *chan, const struct tsa_ser
return 0;
}
-static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struct tsa_serial_info *info,
- bool enable)
+static int qmc_chan_setup_tsa_32rx(struct qmc_chan *chan, const struct tsa_serial_info *info,
+ bool enable)
{
unsigned int i;
u16 curr;
u16 val;
- /* Use a Tx 32 entries table and a Rx 32 entries table */
+ /* Use a Rx 32 entries table */
val = QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id);
@@ -633,6 +633,30 @@ static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struct tsa_
return -EBUSY;
}
}
+
+ /* Set entries based on Rx stuff */
+ for (i = 0; i < info->nb_rx_ts; i++) {
+ if (!(chan->rx_ts_mask & (((u64)1) << i)))
+ continue;
+
+ qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2),
+ ~QMC_TSA_WRAP, enable ? val : 0x0000);
+ }
+
+ return 0;
+}
+
+static int qmc_chan_setup_tsa_32tx(struct qmc_chan *chan, const struct tsa_serial_info *info,
+ bool enable)
+{
+ unsigned int i;
+ u16 curr;
+ u16 val;
+
+ /* Use a Tx 32 entries table */
+
+ val = QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id);
+
/* Check entries based on Tx stuff */
for (i = 0; i < info->nb_tx_ts; i++) {
if (!(chan->tx_ts_mask & (((u64)1) << i)))
@@ -646,14 +670,6 @@ static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struct tsa_
}
}
- /* Set entries based on Rx stuff */
- for (i = 0; i < info->nb_rx_ts; i++) {
- if (!(chan->rx_ts_mask & (((u64)1) << i)))
- continue;
-
- qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2),
- ~QMC_TSA_WRAP, enable ? val : 0x0000);
- }
/* Set entries based on Tx stuff */
for (i = 0; i < info->nb_tx_ts; i++) {
if (!(chan->tx_ts_mask & (((u64)1) << i)))
@@ -680,9 +696,14 @@ static int qmc_chan_setup_tsa(struct qmc_chan *chan, bool enable)
* Setup one common 64 entries table or two 32 entries (one for Tx
* and one for Tx) according to assigned TS numbers.
*/
- return ((info.nb_tx_ts > 32) || (info.nb_rx_ts > 32)) ?
- qmc_chan_setup_tsa_64rxtx(chan, &info, enable) :
- qmc_chan_setup_tsa_32rx_32tx(chan, &info, enable);
+ if (info.nb_tx_ts > 32 || info.nb_rx_ts > 32)
+ return qmc_chan_setup_tsa_64rxtx(chan, &info, enable);
+
+ ret = qmc_chan_setup_tsa_32rx(chan, &info, enable);
+ if (ret)
+ return ret;
+
+ return qmc_chan_setup_tsa_32tx(chan, &info, enable);
}
static int qmc_chan_command(struct qmc_chan *chan, u8 qmc_opcode)
--
2.41.0
next prev parent reply other threads:[~2023-07-25 9:27 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-25 9:23 [PATCH 00/26] Add support for QMC HDLC, framer infrastruture and PEF2256 framer Herve Codina
2023-07-25 9:23 ` [PATCH 01/26] soc: fsl: cpm1: qmc: Fix rx channel reset Herve Codina
2023-07-25 9:23 ` [PATCH 02/26] soc: fsl: cpm1: qmc: Extend the API to provide Rx status Herve Codina
2023-07-25 9:23 ` [PATCH 03/26] dt-bindings: net: Add support for QMC HDLC Herve Codina
2023-07-25 9:23 ` [PATCH 04/26] net: wan: " Herve Codina
2023-07-25 9:23 ` [PATCH 05/26] MAINTAINERS: Add the Freescale QMC HDLC driver entry Herve Codina
2023-07-25 9:23 ` [PATCH 06/26] soc: fsl: cpm1: qmc: Introduce available timeslots masks Herve Codina
2023-07-25 9:23 ` [PATCH 07/26] soc: fsl: cpm1: qmc: Rename qmc_setup_tsa* to qmc_init_tsa* Herve Codina
2023-07-25 9:23 ` [PATCH 08/26] soc: fsl: cpm1: qmc: Introduce qmc_chan_setup_tsa* Herve Codina
2023-07-25 9:23 ` [PATCH 09/26] soc: fsl: cpm1: qmc: Remove no more needed checks from qmc_check_chans() Herve Codina
2023-07-25 9:23 ` [PATCH 10/26] soc: fsl: cpm1: qmc: Check available timeslots in qmc_check_chans() Herve Codina
2023-07-25 9:23 ` [PATCH 11/26] soc: fsl: cpm1: qmc: Add support for disabling channel TSA entries Herve Codina
2023-07-25 9:23 ` Herve Codina [this message]
2023-07-25 9:23 ` [PATCH 13/26] soc: fsl: cpm1: qmc: Introduce is_tsa_64rxtx flag Herve Codina
2023-07-25 9:23 ` [PATCH 14/26] soc: fsl: cpm1: qmc: Handle timeslot entries at channel start() and stop() Herve Codina
2023-07-25 9:23 ` [PATCH 15/26] soc: fsl: cpm1: qmc: Remove timeslots handling from setup_chan() Herve Codina
2023-07-25 9:23 ` [PATCH 16/26] soc: fsl: cpm1: qmc: Introduce functions to change timeslots at runtime Herve Codina
2023-07-25 9:23 ` [PATCH 17/26] wan: qmc_hdlc: Add runtime timeslots changes support Herve Codina
2023-07-25 9:23 ` [PATCH 18/26] net: wan: Add framer framework support Herve Codina
2023-07-25 9:23 ` [PATCH 19/26] dt-bindings: net: Add the Lantiq PEF2256 E1/T1/J1 framer Herve Codina
2023-07-25 9:23 ` [PATCH 20/26] mfd: core: Ensure disabled devices are skiped without aborting Herve Codina
2023-07-25 9:23 ` [PATCH 21/26] net: wan: framer: Add support for the Lantiq PEF2256 framer Herve Codina
2023-07-25 9:23 ` [PATCH 22/26] pinctrl: Add support for the Lantic PEF2256 pinmux Herve Codina
2023-07-25 9:23 ` [PATCH 23/26] MAINTAINERS: Add the Lantiq PEF2256 driver entry Herve Codina
2023-07-25 9:24 ` [PATCH 24/26] ASoC: codecs: Add support for the framer codec Herve Codina
2023-07-25 16:41 ` Randy Dunlap
2023-07-25 9:24 ` [PATCH 25/26] dt-bindings: net: fsl,qmc-hdlc: Add framer support Herve Codina
2023-07-25 9:24 ` [PATCH 26/26] net: wan: fsl_qmc_hdlc: " Herve Codina
2023-07-26 4:14 ` [PATCH 00/26] Add support for QMC HDLC, framer infrastruture and PEF2256 framer Jakub Kicinski
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