From: Herve Codina <herve.codina@bootlin.com>
To: Herve Codina <herve.codina@bootlin.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Andrew Lunn <andrew@lunn.ch>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>, Lee Jones <lee@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
Qiang Zhao <qiang.zhao@nxp.com>, Li Yang <leoyang.li@nxp.com>,
Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>, Jaroslav Kysela <perex@perex.cz>,
Takashi Iwai <tiwai@suse.com>,
Shengjiu Wang <shengjiu.wang@gmail.com>,
Xiubo Li <Xiubo.Lee@gmail.com>,
Fabio Estevam <festevam@gmail.com>,
Nicolin Chen <nicoleotsuka@gmail.com>,
Christophe Leroy <christophe.leroy@csgroup.eu>
Cc: netdev@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
alsa-devel@alsa-project.org,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Subject: [PATCH 02/26] soc: fsl: cpm1: qmc: Extend the API to provide Rx status
Date: Tue, 25 Jul 2023 11:23:38 +0200 [thread overview]
Message-ID: <20230725092417.43706-3-herve.codina@bootlin.com> (raw)
In-Reply-To: <20230725092417.43706-1-herve.codina@bootlin.com>
In HDLC mode, some status flags related to the data read transfer can be
set by the hardware and need to be known by a QMC consumer for further
analysis.
Extend the API in order to provide these transfer status flags at the
read complete() call.
In TRANSPARENT mode, these flags have no meaning. Keep only one read
complete() API and update the consumers working in transparent mode.
In this case, the newly introduced flags parameter is simply unused.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
drivers/soc/fsl/qe/qmc.c | 29 +++++++++++++++++++++++++----
include/soc/fsl/qe/qmc.h | 15 ++++++++++++++-
sound/soc/fsl/fsl_qmc_audio.c | 2 +-
3 files changed, 40 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index a45e40776b45..1c7853a20ef9 100644
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -166,7 +166,7 @@
struct qmc_xfer_desc {
union {
void (*tx_complete)(void *context);
- void (*rx_complete)(void *context, size_t length);
+ void (*rx_complete)(void *context, size_t length, unsigned int flags);
};
void *context;
};
@@ -421,7 +421,8 @@ static void qmc_chan_write_done(struct qmc_chan *chan)
}
int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
- void (*complete)(void *context, size_t length), void *context)
+ void (*complete)(void *context, size_t length, unsigned int flags),
+ void *context)
{
struct qmc_xfer_desc *xfer_desc;
unsigned long flags;
@@ -454,6 +455,10 @@ int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
xfer_desc->rx_complete = complete;
xfer_desc->context = context;
+ /* Clear previous status flags */
+ ctrl &= ~(QMC_BD_RX_L | QMC_BD_RX_F | QMC_BD_RX_LG | QMC_BD_RX_NO |
+ QMC_BD_RX_AB | QMC_BD_RX_CR);
+
/* Activate the descriptor */
ctrl |= (QMC_BD_RX_E | QMC_BD_RX_UB);
wmb(); /* Be sure to flush data before descriptor activation */
@@ -485,7 +490,7 @@ EXPORT_SYMBOL(qmc_chan_read_submit);
static void qmc_chan_read_done(struct qmc_chan *chan)
{
- void (*complete)(void *context, size_t size);
+ void (*complete)(void *context, size_t size, unsigned int flags);
struct qmc_xfer_desc *xfer_desc;
unsigned long flags;
cbd_t *__iomem bd;
@@ -527,7 +532,23 @@ static void qmc_chan_read_done(struct qmc_chan *chan)
if (complete) {
spin_unlock_irqrestore(&chan->rx_lock, flags);
- complete(context, datalen);
+
+ /*
+ * Avoid conversion between internal hardware flags and
+ * the software API flags.
+ * -> Be sure that the software API flags are consistent
+ * with the hardware flags
+ */
+ BUILD_BUG_ON(QMC_RX_FLAG_HDLC_LAST != QMC_BD_RX_L);
+ BUILD_BUG_ON(QMC_RX_FLAG_HDLC_FIRST != QMC_BD_RX_F);
+ BUILD_BUG_ON(QMC_RX_FLAG_HDLC_OVF != QMC_BD_RX_LG);
+ BUILD_BUG_ON(QMC_RX_FLAG_HDLC_UNA != QMC_BD_RX_NO);
+ BUILD_BUG_ON(QMC_RX_FLAG_HDLC_ABORT != QMC_BD_RX_AB);
+ BUILD_BUG_ON(QMC_RX_FLAG_HDLC_CRC != QMC_BD_RX_CR);
+
+ complete(context, datalen,
+ ctrl & (QMC_BD_RX_L | QMC_BD_RX_F | QMC_BD_RX_LG |
+ QMC_BD_RX_NO | QMC_BD_RX_AB | QMC_BD_RX_CR));
spin_lock_irqsave(&chan->rx_lock, flags);
}
diff --git a/include/soc/fsl/qe/qmc.h b/include/soc/fsl/qe/qmc.h
index 3c61a50d2ae2..6f1d6cebc9fe 100644
--- a/include/soc/fsl/qe/qmc.h
+++ b/include/soc/fsl/qe/qmc.h
@@ -9,6 +9,7 @@
#ifndef __SOC_FSL_QMC_H__
#define __SOC_FSL_QMC_H__
+#include <linux/bits.h>
#include <linux/types.h>
struct device_node;
@@ -56,8 +57,20 @@ int qmc_chan_set_param(struct qmc_chan *chan, const struct qmc_chan_param *param
int qmc_chan_write_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
void (*complete)(void *context), void *context);
+/* Flags available (ORed) for read complete() flags parameter in HDLC mode.
+ * No flags are available in transparent mode and the read complete() flags
+ * parameter has no meaning in transparent mode.
+ */
+#define QMC_RX_FLAG_HDLC_LAST BIT(11) /* Last in frame */
+#define QMC_RX_FLAG_HDLC_FIRST BIT(10) /* First in frame */
+#define QMC_RX_FLAG_HDLC_OVF BIT(5) /* Data overflow */
+#define QMC_RX_FLAG_HDLC_UNA BIT(4) /* Unaligned (ie. bits received not multiple of 8) */
+#define QMC_RX_FLAG_HDLC_ABORT BIT(3) /* Received an abort sequence (seven consecutive ones) */
+#define QMC_RX_FLAG_HDLC_CRC BIT(2) /* CRC error */
+
int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
- void (*complete)(void *context, size_t length),
+ void (*complete)(void *context, size_t length,
+ unsigned int flags),
void *context);
#define QMC_CHAN_READ (1<<0)
diff --git a/sound/soc/fsl/fsl_qmc_audio.c b/sound/soc/fsl/fsl_qmc_audio.c
index 7cbb8e4758cc..5d745aae17a8 100644
--- a/sound/soc/fsl/fsl_qmc_audio.c
+++ b/sound/soc/fsl/fsl_qmc_audio.c
@@ -99,7 +99,7 @@ static void qmc_audio_pcm_write_complete(void *context)
snd_pcm_period_elapsed(prtd->substream);
}
-static void qmc_audio_pcm_read_complete(void *context, size_t length)
+static void qmc_audio_pcm_read_complete(void *context, size_t length, unsigned int flags)
{
struct qmc_dai_prtd *prtd = context;
int ret;
--
2.41.0
next prev parent reply other threads:[~2023-07-25 9:25 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-25 9:23 [PATCH 00/26] Add support for QMC HDLC, framer infrastruture and PEF2256 framer Herve Codina
2023-07-25 9:23 ` [PATCH 01/26] soc: fsl: cpm1: qmc: Fix rx channel reset Herve Codina
2023-07-25 9:23 ` Herve Codina [this message]
2023-07-25 9:23 ` [PATCH 03/26] dt-bindings: net: Add support for QMC HDLC Herve Codina
2023-07-25 9:23 ` [PATCH 04/26] net: wan: " Herve Codina
2023-07-25 9:23 ` [PATCH 05/26] MAINTAINERS: Add the Freescale QMC HDLC driver entry Herve Codina
2023-07-25 9:23 ` [PATCH 06/26] soc: fsl: cpm1: qmc: Introduce available timeslots masks Herve Codina
2023-07-25 9:23 ` [PATCH 07/26] soc: fsl: cpm1: qmc: Rename qmc_setup_tsa* to qmc_init_tsa* Herve Codina
2023-07-25 9:23 ` [PATCH 08/26] soc: fsl: cpm1: qmc: Introduce qmc_chan_setup_tsa* Herve Codina
2023-07-25 9:23 ` [PATCH 09/26] soc: fsl: cpm1: qmc: Remove no more needed checks from qmc_check_chans() Herve Codina
2023-07-25 9:23 ` [PATCH 10/26] soc: fsl: cpm1: qmc: Check available timeslots in qmc_check_chans() Herve Codina
2023-07-25 9:23 ` [PATCH 11/26] soc: fsl: cpm1: qmc: Add support for disabling channel TSA entries Herve Codina
2023-07-25 9:23 ` [PATCH 12/26] soc: fsl: cpm1: qmc: Split Tx and Rx TSA entries setup Herve Codina
2023-07-25 9:23 ` [PATCH 13/26] soc: fsl: cpm1: qmc: Introduce is_tsa_64rxtx flag Herve Codina
2023-07-25 9:23 ` [PATCH 14/26] soc: fsl: cpm1: qmc: Handle timeslot entries at channel start() and stop() Herve Codina
2023-07-25 9:23 ` [PATCH 15/26] soc: fsl: cpm1: qmc: Remove timeslots handling from setup_chan() Herve Codina
2023-07-25 9:23 ` [PATCH 16/26] soc: fsl: cpm1: qmc: Introduce functions to change timeslots at runtime Herve Codina
2023-07-25 9:23 ` [PATCH 17/26] wan: qmc_hdlc: Add runtime timeslots changes support Herve Codina
2023-07-25 9:23 ` [PATCH 18/26] net: wan: Add framer framework support Herve Codina
2023-07-25 9:23 ` [PATCH 19/26] dt-bindings: net: Add the Lantiq PEF2256 E1/T1/J1 framer Herve Codina
2023-07-25 9:23 ` [PATCH 20/26] mfd: core: Ensure disabled devices are skiped without aborting Herve Codina
2023-07-25 9:23 ` [PATCH 21/26] net: wan: framer: Add support for the Lantiq PEF2256 framer Herve Codina
2023-07-25 9:23 ` [PATCH 22/26] pinctrl: Add support for the Lantic PEF2256 pinmux Herve Codina
2023-07-25 9:23 ` [PATCH 23/26] MAINTAINERS: Add the Lantiq PEF2256 driver entry Herve Codina
2023-07-25 9:24 ` [PATCH 24/26] ASoC: codecs: Add support for the framer codec Herve Codina
2023-07-25 16:41 ` Randy Dunlap
2023-07-25 9:24 ` [PATCH 25/26] dt-bindings: net: fsl,qmc-hdlc: Add framer support Herve Codina
2023-07-25 9:24 ` [PATCH 26/26] net: wan: fsl_qmc_hdlc: " Herve Codina
2023-07-26 4:14 ` [PATCH 00/26] Add support for QMC HDLC, framer infrastruture and PEF2256 framer Jakub Kicinski
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