* [PATCH 0/2] Add blsp1_i2c6 and blsp1_uart2 to MSM8226 SoC
@ 2023-09-02 17:32 Luca Weiss
2023-09-02 17:32 ` [PATCH 1/2] pinctrl: qcom: msm8226: Add blsp_i2c6 function Luca Weiss
2023-09-02 17:32 ` [PATCH 2/2] ARM: dts: qcom: msm8226: Add blsp1_i2c6 and blsp1_uart2 Luca Weiss
0 siblings, 2 replies; 5+ messages in thread
From: Luca Weiss @ 2023-09-02 17:32 UTC (permalink / raw)
To: ~postmarketos/upstreaming, phone-devel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, linux-gpio, linux-kernel, devicetree, Luca Weiss
Add the I2C bus and UART interface found on the MSM8226. For the I2C bus
we also first need to add the pinctrl function in the driver.
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
---
Luca Weiss (2):
pinctrl: qcom: msm8226: Add blsp_i2c6 function
ARM: dts: qcom: msm8226: Add blsp1_i2c6 and blsp1_uart2
arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 29 +++++++++++++++++++++++++++++
drivers/pinctrl/qcom/pinctrl-msm8226.c | 8 ++++++--
2 files changed, 35 insertions(+), 2 deletions(-)
---
base-commit: 7c2878be573282a9961c359b806ccf70afe1a6b6
change-id: 20230902-msm8226-i2c6-0f7d74dafa8b
Best regards,
--
Luca Weiss <luca@z3ntu.xyz>
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 1/2] pinctrl: qcom: msm8226: Add blsp_i2c6 function 2023-09-02 17:32 [PATCH 0/2] Add blsp1_i2c6 and blsp1_uart2 to MSM8226 SoC Luca Weiss @ 2023-09-02 17:32 ` Luca Weiss 2023-09-02 20:30 ` Konrad Dybcio 2023-09-02 17:32 ` [PATCH 2/2] ARM: dts: qcom: msm8226: Add blsp1_i2c6 and blsp1_uart2 Luca Weiss 1 sibling, 1 reply; 5+ messages in thread From: Luca Weiss @ 2023-09-02 17:32 UTC (permalink / raw) To: ~postmarketos/upstreaming, phone-devel, Andy Gross, Bjorn Andersson, Konrad Dybcio, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, linux-gpio, linux-kernel, devicetree, Luca Weiss On GPIO22 and GPIO23 there is another I2C bus. Add the function for it. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> --- drivers/pinctrl/qcom/pinctrl-msm8226.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8226.c b/drivers/pinctrl/qcom/pinctrl-msm8226.c index 994619840a70..da964eebd313 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8226.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8226.c @@ -336,6 +336,7 @@ enum msm8226_functions { msm_mux_blsp_i2c3, msm_mux_blsp_i2c4, msm_mux_blsp_i2c5, + msm_mux_blsp_i2c6, msm_mux_blsp_spi1, msm_mux_blsp_spi2, msm_mux_blsp_spi3, @@ -436,6 +437,8 @@ static const char * const blsp_spi5_groups[] = { "gpio16", "gpio17", "gpio18", "gpio19" }; +static const char * const blsp_i2c6_groups[] = { "gpio22", "gpio23" }; + static const char * const cci_i2c0_groups[] = { "gpio29", "gpio30" }; static const char * const cam_mclk0_groups[] = { "gpio26" }; @@ -459,6 +462,7 @@ static const struct pinfunction msm8226_functions[] = { MSM_PIN_FUNCTION(blsp_i2c3), MSM_PIN_FUNCTION(blsp_i2c4), MSM_PIN_FUNCTION(blsp_i2c5), + MSM_PIN_FUNCTION(blsp_i2c6), MSM_PIN_FUNCTION(blsp_spi1), MSM_PIN_FUNCTION(blsp_spi2), MSM_PIN_FUNCTION(blsp_spi3), @@ -507,8 +511,8 @@ static const struct msm_pingroup msm8226_groups[] = { PINGROUP(19, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA), PINGROUP(20, NA, NA, NA, NA, NA, NA, NA), PINGROUP(21, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(22, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(23, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, NA, NA, blsp_i2c6, NA, NA, NA, NA), + PINGROUP(23, NA, NA, blsp_i2c6, NA, NA, NA, NA), PINGROUP(24, NA, NA, NA, NA, NA, NA, NA), PINGROUP(25, NA, NA, NA, NA, NA, NA, NA), PINGROUP(26, cam_mclk0, NA, NA, NA, NA, NA, NA), -- 2.42.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] pinctrl: qcom: msm8226: Add blsp_i2c6 function 2023-09-02 17:32 ` [PATCH 1/2] pinctrl: qcom: msm8226: Add blsp_i2c6 function Luca Weiss @ 2023-09-02 20:30 ` Konrad Dybcio 0 siblings, 0 replies; 5+ messages in thread From: Konrad Dybcio @ 2023-09-02 20:30 UTC (permalink / raw) To: Luca Weiss, ~postmarketos/upstreaming, phone-devel, Andy Gross, Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, linux-gpio, linux-kernel, devicetree On 2.09.2023 19:32, Luca Weiss wrote: > On GPIO22 and GPIO23 there is another I2C bus. Add the function for it. > > Signed-off-by: Luca Weiss <luca@z3ntu.xyz> > --- Need to also update the bindings Konrad ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] ARM: dts: qcom: msm8226: Add blsp1_i2c6 and blsp1_uart2 2023-09-02 17:32 [PATCH 0/2] Add blsp1_i2c6 and blsp1_uart2 to MSM8226 SoC Luca Weiss 2023-09-02 17:32 ` [PATCH 1/2] pinctrl: qcom: msm8226: Add blsp_i2c6 function Luca Weiss @ 2023-09-02 17:32 ` Luca Weiss 2023-09-02 20:33 ` Konrad Dybcio 1 sibling, 1 reply; 5+ messages in thread From: Luca Weiss @ 2023-09-02 17:32 UTC (permalink / raw) To: ~postmarketos/upstreaming, phone-devel, Andy Gross, Bjorn Andersson, Konrad Dybcio, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, linux-gpio, linux-kernel, devicetree, Luca Weiss Add more busses found on msm8226 SoC. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> --- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index b6ae4b7936e3..3b6114049e61 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -230,6 +230,15 @@ blsp1_uart1: serial@f991d000 { status = "disabled"; }; + blsp1_uart2: serial@f991e000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991e000 0x1000>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + blsp1_uart3: serial@f991f000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf991f000 0x1000>; @@ -313,6 +322,19 @@ blsp1_i2c5: i2c@f9927000 { #size-cells = <0>; }; + blsp1_i2c6: i2c@f9928000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9928000 0x1000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c6_pins>; + #address-cells = <1>; + #size-cells = <0>; + }; + cci: cci@fda0c000 { compatible = "qcom,msm8226-cci"; #address-cells = <1>; @@ -460,6 +482,13 @@ blsp1_i2c5_pins: blsp1-i2c5-state { bias-disable; }; + blsp1_i2c6_pins: blsp1-i2c6-state { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + cci_default: cci-default-state { pins = "gpio29", "gpio30"; function = "cci_i2c0"; -- 2.42.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] ARM: dts: qcom: msm8226: Add blsp1_i2c6 and blsp1_uart2 2023-09-02 17:32 ` [PATCH 2/2] ARM: dts: qcom: msm8226: Add blsp1_i2c6 and blsp1_uart2 Luca Weiss @ 2023-09-02 20:33 ` Konrad Dybcio 0 siblings, 0 replies; 5+ messages in thread From: Konrad Dybcio @ 2023-09-02 20:33 UTC (permalink / raw) To: Luca Weiss, ~postmarketos/upstreaming, phone-devel, Andy Gross, Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, linux-gpio, linux-kernel, devicetree On 2.09.2023 19:32, Luca Weiss wrote: > Add more busses found on msm8226 SoC. > > Signed-off-by: Luca Weiss <luca@z3ntu.xyz> > --- > arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 29 +++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi > index b6ae4b7936e3..3b6114049e61 100644 > --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi > +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi > @@ -230,6 +230,15 @@ blsp1_uart1: serial@f991d000 { > status = "disabled"; > }; > > + blsp1_uart2: serial@f991e000 { > + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; > + reg = <0xf991e000 0x1000>; > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; One per line, please > + clock-names = "core", "iface"; > + status = "disabled"; > + }; > + > blsp1_uart3: serial@f991f000 { > compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; > reg = <0xf991f000 0x1000>; > @@ -313,6 +322,19 @@ blsp1_i2c5: i2c@f9927000 { > #size-cells = <0>; > }; > > + blsp1_i2c6: i2c@f9928000 { > + status = "disabled"; > + compatible = "qcom,i2c-qup-v2.1.1"; > + reg = <0xf9928000 0x1000>; > + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; > + clock-names = "core", "iface"; > + pinctrl-names = "default"; > + pinctrl-0 = <&blsp1_i2c6_pins>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; compatible reg interrupts clocks clock-names pinctrl-0 pinctrl-names addrsizecells status to make it coherent ish with new nodes being added today I know it's rather incoherent with what's in the file, but I guess my wunderwaffe dt sorter script is still on the back burner.. Konrad ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-09-02 20:33 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-09-02 17:32 [PATCH 0/2] Add blsp1_i2c6 and blsp1_uart2 to MSM8226 SoC Luca Weiss 2023-09-02 17:32 ` [PATCH 1/2] pinctrl: qcom: msm8226: Add blsp_i2c6 function Luca Weiss 2023-09-02 20:30 ` Konrad Dybcio 2023-09-02 17:32 ` [PATCH 2/2] ARM: dts: qcom: msm8226: Add blsp1_i2c6 and blsp1_uart2 Luca Weiss 2023-09-02 20:33 ` Konrad Dybcio
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