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From: Herve Codina <herve.codina@bootlin.com>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: "David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Andrew Lunn <andrew@lunn.ch>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>, Lee Jones <lee@kernel.org>,
	Qiang Zhao <qiang.zhao@nxp.com>, Li Yang <leoyang.li@nxp.com>,
	Liam Girdwood <lgirdwood@gmail.com>,
	Mark Brown <broonie@kernel.org>, Jaroslav Kysela <perex@perex.cz>,
	Takashi Iwai <tiwai@suse.com>,
	Shengjiu Wang <shengjiu.wang@gmail.com>,
	Xiubo Li <Xiubo.Lee@gmail.com>,
	Fabio Estevam <festevam@gmail.com>,
	Nicolin Chen <nicoleotsuka@gmail.com>,
	Christophe Leroy <christophe.leroy@csgroup.eu>,
	Randy Dunlap <rdunlap@infradead.org>,
	netdev@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	alsa-devel@alsa-project.org, Simon Horman <horms@kernel.org>,
	Christophe JAILLET <christophe.jaillet@wanadoo.fr>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Subject: Re: [PATCH v5 28/31] pinctrl: Add support for the Lantic PEF2256 pinmux
Date: Mon, 18 Sep 2023 10:35:40 +0200	[thread overview]
Message-ID: <20230918103540.5902af4c@bootlin.com> (raw)
In-Reply-To: <CACRpkdbxdMZt4E1SF1v9as-jw=TpvS1mk2TQqAgywMBLbKaNoA@mail.gmail.com>

On Tue, 12 Sep 2023 13:04:56 +0200
Linus Walleij <linus.walleij@linaro.org> wrote:

> Hi Herve,
> 
> thanks for your patch!
> 
> On Tue, Sep 12, 2023 at 12:15 PM Herve Codina <herve.codina@bootlin.com> wrote:
> 
> > The Lantiq PEF2256 is a framer and line interface component designed to
> > fulfill all required interfacing between an analog E1/T1/J1 line and the
> > digital PCM system highway/H.100 bus.
> >
> > This kind of component can be found in old telecommunication system.
> > It was used to digital transmission of many simultaneous telephone calls
> > by time-division multiplexing. Also using HDLC protocol, WAN networks
> > can be reached through the framer.
> >
> > This pinmux support handles the pin muxing part (pins RP(A..D) and pins
> > XP(A..D)) of the PEF2256.
> >
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> > Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> > Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>  
> 
> Nice to see this as a proper pin control driver!
> 
> >  drivers/pinctrl/pinctrl-pef2256-regs.h |  65 ++++++
> >  drivers/pinctrl/pinctrl-pef2256.c      | 308 +++++++++++++++++++++++++  
> 
> Do you really need a separate header just for some registers?
> But it's a matter of taste so I'm not gonna complain if you want
> it this way.

Will be move to the .c file in the next iteration.

> 
> > +config PINCTRL_PEF2256
> > +       tristate "Lantiq PEF2256 (FALC56) pin controller driver"
> > +       depends on OF && FRAMER_PEF2256
> > +       select PINMUX  
> 
> select PINCONF

Will be added in the next iteration.

> 
> > +       select GENERIC_PINCONF  
> 
> This brings it in implicitly but I prefer that you just select it.
> 
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*  
> 
> I think SPDX mandates that you start the tag with C99 comments

Already replied by Mark, C style comment is correct -> No change.

> 
> // SPDX-License-Identifier: GPL-2.0-only
> 
> > +       /* We map 1 group <-> 1 pin */  
> 
> Also known as "the qualcomm trick", but hey: it's fine.
> 
> > +static int pef2256_register_pinctrl(struct pef2256_pinctrl *pef2256)
> > +{
> > +       struct pinctrl_dev      *pctrl;
> > +
> > +       pef2256->pctrl_desc.name    = dev_name(pef2256->dev);
> > +       pef2256->pctrl_desc.owner   = THIS_MODULE;
> > +       pef2256->pctrl_desc.pctlops = &pef2256_pctlops;
> > +       pef2256->pctrl_desc.pmxops  = &pef2256_pmxops;
> > +       if (pef2256->version == PEF2256_VERSION_1_2) {
> > +               pef2256->pctrl_desc.pins  = pef2256_v12_pins;
> > +               pef2256->pctrl_desc.npins = ARRAY_SIZE(pef2256_v12_pins);
> > +               pef2256->functions  = pef2256_v12_functions;
> > +               pef2256->nfunctions = ARRAY_SIZE(pef2256_v12_functions);
> > +       } else {
> > +               pef2256->pctrl_desc.pins  = pef2256_v2x_pins;
> > +               pef2256->pctrl_desc.npins = ARRAY_SIZE(pef2256_v2x_pins);
> > +               pef2256->functions  = pef2256_v2x_functions;
> > +               pef2256->nfunctions = ARRAY_SIZE(pef2256_v2x_functions);
> > +       }
> > +
> > +       pctrl = devm_pinctrl_register(pef2256->dev, &pef2256->pctrl_desc, pef2256);
> > +       if (IS_ERR(pctrl)) {
> > +               dev_err(pef2256->dev, "pinctrl driver registration failed\n");
> > +               return PTR_ERR(pctrl);
> > +       }
> > +
> > +       return 0;  
> 
> You could use
> return dev_err_probe(...);

Indeed, I will change.

> 
> > +       pef2256_reset_pinmux(pef2256_pinctrl);
> > +       ret = pef2256_register_pinctrl(pef2256_pinctrl);
> > +       if (ret)
> > +               return ret;  
> 
> Or you could use it down here.
> 
> With or without these changes (because they are nitpicks)
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
> 
> Yours,
> Linus Walleij

Thanks for your comment.

Best regards,
Hervé

  parent reply	other threads:[~2023-09-18  8:36 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-12  8:14 [PATCH v5 00/31] Add support for QMC HDLC, framer infrastructure and PEF2256 framer Herve Codina
2023-09-12  8:14 ` [PATCH v5 01/31] soc: fsl: cpm1: tsa: Fix __iomem addresses declaration Herve Codina
2023-09-12  8:14 ` [PATCH v5 02/31] soc: fsl: cpm1: qmc: " Herve Codina
2023-09-12  8:14 ` [PATCH v5 03/31] soc: fsl: cpm1: qmc: Fix rx channel reset Herve Codina
2023-09-12  8:14 ` [PATCH v5 04/31] soc: fsl: cpm1: qmc: Extend the API to provide Rx status Herve Codina
2023-09-12  8:14 ` [PATCH v5 05/31] soc: fsl: cpm1: qmc: Remove inline function specifiers Herve Codina
2023-09-12  8:14 ` [PATCH v5 06/31] dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc: Fix example property name Herve Codina
2023-09-12 16:36   ` Conor Dooley
2023-09-12  8:14 ` [PATCH v5 07/31] dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc: Add 'additionalProperties: false' in child nodes Herve Codina
2023-09-12 16:37   ` Conor Dooley
2023-09-12 18:23   ` Rob Herring
2023-09-12 10:10 ` [PATCH v5 08/31] dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc: Add support for QMC HDLC Herve Codina
2023-09-12 17:21   ` Conor Dooley
2023-09-13  7:26     ` Herve Codina
2023-09-13 14:42       ` Conor Dooley
2023-09-13 14:52         ` Herve Codina
2023-09-13 14:56           ` Conor Dooley
2023-09-13 14:59             ` Conor Dooley
2023-09-18  7:42               ` Herve Codina
2023-09-12 10:11 ` [PATCH v5 09/31] soc: fsl: cpm1: qmc: Add support for child devices Herve Codina
2023-09-12 10:12 ` [PATCH v5 10/31] net: wan: Add support for QMC HDLC Herve Codina
2023-09-12 10:12 ` [PATCH v5 11/31] MAINTAINERS: Add the Freescale QMC HDLC driver entry Herve Codina
2023-09-12 10:13 ` [PATCH v5 12/31] soc: fsl: cpm1: qmc: Introduce available timeslots masks Herve Codina
2023-09-12 10:13 ` [PATCH v5 13/31] soc: fsl: cpm1: qmc: Rename qmc_setup_tsa* to qmc_init_tsa* Herve Codina
2023-09-12 10:13 ` [PATCH v5 14/31] soc: fsl: cpm1: qmc: Introduce qmc_chan_setup_tsa* Herve Codina
2023-09-12 10:13 ` [PATCH v5 15/31] soc: fsl: cpm1: qmc: Remove no more needed checks from qmc_check_chans() Herve Codina
2023-09-12 10:13 ` [PATCH v5 16/31] soc: fsl: cpm1: qmc: Check available timeslots in qmc_check_chans() Herve Codina
2023-09-12 10:13 ` [PATCH v5 17/31] soc: fsl: cpm1: qmc: Add support for disabling channel TSA entries Herve Codina
2023-09-12 10:13 ` [PATCH v5 18/31] soc: fsl: cpm1: qmc: Split Tx and Rx TSA entries setup Herve Codina
2023-09-12 10:14 ` [PATCH v5 19/31] soc: fsl: cpm1: qmc: Introduce is_tsa_64rxtx flag Herve Codina
2023-09-12 10:14 ` [PATCH v5 20/31] soc: fsl: cpm1: qmc: Handle timeslot entries at channel start() and stop() Herve Codina
2023-09-12 10:14 ` [PATCH v5 21/31] soc: fsl: cpm1: qmc: Remove timeslots handling from setup_chan() Herve Codina
2023-09-12 10:14 ` [PATCH v5 22/31] soc: fsl: cpm1: qmc: Introduce functions to change timeslots at runtime Herve Codina
2023-09-12 10:14 ` [PATCH v5 23/31] wan: qmc_hdlc: Add runtime timeslots changes support Herve Codina
2023-09-12 10:14 ` [PATCH v5 24/31] net: wan: Add framer framework support Herve Codina
2023-09-13 16:59   ` Mark Brown
2023-09-12 10:14 ` [PATCH v5 25/31] dt-bindings: net: Add the Lantiq PEF2256 E1/T1/J1 framer Herve Codina
2023-09-12 18:13   ` Conor Dooley
2023-09-12 18:49     ` Christophe Leroy
2023-09-18  7:49       ` Herve Codina
2023-09-18  8:02         ` Herve Codina
2023-09-21  8:45         ` Christophe Leroy
     [not found]     ` <20230912185405.GA1165807-robh@kernel.org>
2023-09-13 14:39       ` Conor Dooley
2023-09-12 10:14 ` [PATCH v5 26/31] mfd: core: Ensure disabled devices are skipped without aborting Herve Codina
2023-09-12 10:14 ` [PATCH v5 27/31] net: wan: framer: Add support for the Lantiq PEF2256 framer Herve Codina
2023-09-12 10:50   ` Linus Walleij
2023-09-12 10:15 ` [PATCH v5 28/31] pinctrl: Add support for the Lantic PEF2256 pinmux Herve Codina
2023-09-12 11:04   ` Linus Walleij
2023-09-12 14:31     ` Mark Brown
2023-09-12 21:04       ` Linus Walleij
2023-09-18  8:35     ` Herve Codina [this message]
2023-09-12 10:15 ` [PATCH v5 29/31] MAINTAINERS: Add the Lantiq PEF2256 driver entry Herve Codina
2023-09-12 11:05   ` Linus Walleij
2023-09-12 10:15 ` [PATCH v5 30/31] ASoC: codecs: Add support for the framer codec Herve Codina
2023-09-12 10:15 ` [PATCH v5 31/31] net: wan: fsl_qmc_hdlc: Add framer support Herve Codina

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