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Date:   Tue, 10 Oct 2023 09:44:00 +0800
From:   Shawn Guo <shawnguo@kernel.org>
To:     "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
Cc:     Linus Walleij <linus.walleij@linaro.org>,
        Bartosz Golaszewski <brgl@bgdev.pl>,
        Andy Shevchenko <andy@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Stefan Agner <stefan@agner.ch>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        Marco Felsch <m.felsch@pengutronix.de>,
        linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        Peng Fan <peng.fan@nxp.com>
Subject: Re: [PATCH v5 6/7] arm64: dts: imx8ulp: update gpio node
Message-ID: <20231010014400.GD819755@dragon>
References: <20231001-vf610-gpio-v5-0-8d873a8f224a@nxp.com>
 <20231001-vf610-gpio-v5-6-8d873a8f224a@nxp.com>
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On Sun, Oct 01, 2023 at 04:27:57PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> The i.MX8ULP GPIO supports two interrupts and one register base,
> the current fsl,imx7ulp-gpio compatible could work for i.MX8ULP in
> gpio-vf610.c driver, it is based on the base address are splited
> into two with offset added in device tree node. Now following
> hardware design, using one register base in device tree node.
> 
> This may break users who use compatible fsl,imx7ulp-gpio to enable
> i.MX8ULP GPIO.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied, thanks!