* [PATCH v2 0/3] Add missing port pins for RZ/Five SoC
@ 2023-10-17 10:46 Prabhakar
2023-10-17 10:46 ` [PATCH v2 1/3] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro Prabhakar
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Prabhakar @ 2023-10-17 10:46 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Linus Walleij
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree,
linux-riscv, linux-gpio, linux-kernel, linux-renesas-soc,
Biju Das, Claudiu Beznea, Prabhakar, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Geert,
This patch series intends to incorporate the absent port pins P19 to P28,
which are exclusively available on the RZ/Five SoC.
Cheers,
Prabhakar
RFC -> v2:
* Fixed review comments pointed by Geert & Biju
RFC: https://lore.kernel.org/lkml/20230630120433.49529-3-prabhakar.mahadev-lad.rj@bp.renesas.com/T/
Lad Prabhakar (3):
pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK()
macro
pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28
riscv: dts: renesas: r9a07g043f: Update gpio-ranges property
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 263 ++++++++++++++++++--
2 files changed, 242 insertions(+), 25 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v2 1/3] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro 2023-10-17 10:46 [PATCH v2 0/3] Add missing port pins for RZ/Five SoC Prabhakar @ 2023-10-17 10:46 ` Prabhakar 2023-10-17 15:42 ` kernel test robot 2023-10-17 10:46 ` [PATCH v2 2/3] pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28 Prabhakar ` (2 subsequent siblings) 3 siblings, 1 reply; 9+ messages in thread From: Prabhakar @ 2023-10-17 10:46 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Linus Walleij Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-riscv, linux-gpio, linux-kernel, linux-renesas-soc, Biju Das, Claudiu Beznea, Prabhakar, Lad Prabhakar From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Currently we assume all the port pins are sequential ie always PX_0 to PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins P19_1 to P28_5 which have holes in them, for example only one pin on port19 is available and that is P19_1 and not P19_0. So to handle such cases include pinmap for each port which would indicate the pin availability on each port. As the pincount can be calculated based on pinmap drop this from RZG2L_GPIO_PORT_PACK() macro and update RZG2L_GPIO_PORT_GET_PINCNT() macro. Previously we had a max of 7 pins on each port but on RZ/Five Port-20 has 8 pins, so move the single pin configuration to BIT(63). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 48 +++++++++++++------------ 1 file changed, 25 insertions(+), 23 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index e6bf66fca074..b0aeeb5ef3fa 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -80,15 +80,17 @@ * n indicates number of pins in the port, a is the register index * and f is pin configuration capabilities supported. */ -#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) -#define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28) +#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) > 0 ? ((u64)(GENMASK_ULL(((n) - 1 + 28), 28))) : 0) | \ + ((a) << 20) | (f)) +#define RZG2L_GPIO_PORT_GET_PINMAP(x) (((x) & GENMASK_ULL(35, 28)) >> 28) +#define RZG2L_GPIO_PORT_GET_PINCNT(x) (hweight8(RZG2L_GPIO_PORT_GET_PINMAP((x)))) /* * BIT(31) indicates dedicated pin, p is the register index while * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits * (b * 8) and f is the pin configuration capabilities supported. */ -#define RZG2L_SINGLE_PIN BIT(31) +#define RZG2L_SINGLE_PIN BIT(63) #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ ((p) << 24) | ((b) << 20) | (f)) #define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20) @@ -180,12 +182,12 @@ struct rzg2l_hwcfg { struct rzg2l_dedicated_configs { const char *name; - u32 config; + u64 config; }; struct rzg2l_pinctrl_data { const char * const *port_pins; - const u32 *port_pin_configs; + const u64 *port_pin_configs; unsigned int n_ports; const struct rzg2l_dedicated_configs *dedicated_pins; unsigned int n_port_pins; @@ -286,7 +288,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, pins = group->pins; for (i = 0; i < group->num_pins; i++) { - unsigned int *pin_data = pctrl->desc.pins[pins[i]].drv_data; + u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); @@ -536,13 +538,13 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, } static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, - u32 cfg, u32 port, u8 bit) + u64 cfg, u32 port, u8 bit) { - u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg); + u8 pinmap = RZG2L_GPIO_PORT_GET_PINMAP(cfg); u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); - u32 data; + u64 data; - if (bit >= pincount || port >= pctrl->data->n_port_pins) + if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins) return -EINVAL; data = pctrl->data->port_pin_configs[port]; @@ -743,7 +745,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, enum pin_config_param param = pinconf_to_config_param(*config); const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; - unsigned int *pin_data = pin->drv_data; + u64 *pin_data = pin->drv_data; unsigned int arg = 0; u32 off, cfg; int ret; @@ -840,7 +842,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; - unsigned int *pin_data = pin->drv_data; + u64 *pin_data = pin->drv_data; enum pin_config_param param; unsigned int i; u32 cfg, off; @@ -1044,7 +1046,7 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - u32 *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u32 port = RZG2L_PIN_ID_TO_PORT(offset); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); @@ -1076,7 +1078,7 @@ static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, bool output) { const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); unsigned long flags; @@ -1097,7 +1099,7 @@ static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); @@ -1128,7 +1130,7 @@ static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); unsigned long flags; @@ -1161,7 +1163,7 @@ static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); u16 reg16; @@ -1246,7 +1248,7 @@ static const char * const rzg2l_gpio_names[] = { "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", }; -static const u32 r9a07g044_gpio_configs[] = { +static const u64 r9a07g044_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), @@ -1298,7 +1300,7 @@ static const u32 r9a07g044_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), }; -static const u32 r9a07g043_gpio_configs[] = { +static const u64 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), @@ -1320,7 +1322,7 @@ static const u32 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), }; -static const u32 r9a08g045_gpio_configs[] = { +static const u64 r9a08g045_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH0)), /* P1 */ @@ -1502,7 +1504,7 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); unsigned int hwirq = irqd_to_hwirq(d); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); unsigned long flags; @@ -1529,7 +1531,7 @@ static void rzg2l_gpio_irq_enable(struct irq_data *d) struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); unsigned int hwirq = irqd_to_hwirq(d); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); unsigned long flags; @@ -1748,7 +1750,7 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; struct pinctrl_pin_desc *pins; unsigned int i, j; - u32 *pin_data; + u64 *pin_data; int ret; pctrl->desc.name = DRV_NAME; -- 2.34.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/3] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro 2023-10-17 10:46 ` [PATCH v2 1/3] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro Prabhakar @ 2023-10-17 15:42 ` kernel test robot 0 siblings, 0 replies; 9+ messages in thread From: kernel test robot @ 2023-10-17 15:42 UTC (permalink / raw) To: Prabhakar, Geert Uytterhoeven, Magnus Damm, Linus Walleij Cc: oe-kbuild-all, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-riscv, linux-gpio, linux-kernel, linux-renesas-soc, Biju Das, Claudiu Beznea, Prabhakar, Lad Prabhakar Hi Prabhakar, kernel test robot noticed the following build warnings: [auto build test WARNING on next-20231017] [cannot apply to geert-renesas-drivers/renesas-pinctrl geert-renesas-devel/next linusw-pinctrl/devel linusw-pinctrl/for-next v6.6-rc6 v6.6-rc5 v6.6-rc4 linus/master v6.6-rc6] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Prabhakar/pinctrl-renesas-rzg2l-Include-pinmap-in-RZG2L_GPIO_PORT_PACK-macro/20231017-184850 base: next-20231017 patch link: https://lore.kernel.org/r/20231017104638.201260-2-prabhakar.mahadev-lad.rj%40bp.renesas.com patch subject: [PATCH v2 1/3] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro config: m68k-allyesconfig (https://download.01.org/0day-ci/archive/20231017/202310172321.wccxqLkr-lkp@intel.com/config) compiler: m68k-linux-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231017/202310172321.wccxqLkr-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202310172321.wccxqLkr-lkp@intel.com/ All warnings (new ones prefixed by >>): In file included from include/linux/bits.h:6, from include/linux/bitops.h:6, from drivers/pinctrl/renesas/pinctrl-rzg2l.c:8: drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_pinctrl_set_mux': >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:292:27: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 292 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_validate_gpio_pin': >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:544:19: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 544 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:551:20: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 551 | if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data)) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_pinctrl_pinconf_get': >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:757:15: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 757 | off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:759:25: note: in expansion of macro 'RZG2L_SINGLE_PIN' 759 | if (*pin_data & RZG2L_SINGLE_PIN) { | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_pinctrl_pinconf_set': >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:855:15: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 855 | off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:857:25: note: in expansion of macro 'RZG2L_SINGLE_PIN' 857 | if (*pin_data & RZG2L_SINGLE_PIN) { | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_gpio_request': >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1050:19: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 1050 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_gpio_set_direction': >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1082:19: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 1082 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_gpio_get_direction': >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1103:19: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 1103 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_gpio_set': >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1134:19: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 1134 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_gpio_get': >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1167:19: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 1167 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c: At top level: >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1360:26: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1360 | { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, | ^~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1362:32: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1362 | { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, | ^~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1364:26: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1364 | { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, | ^~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1366:33: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1366 | { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, | ^~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1367:33: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1367 | { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, | ^~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1368:30: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1368 | { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, | ^~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1370:30: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1370 | { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, | ^~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1372:31: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1372 | { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, | ^~~~~~~~~~~~~~~~~~~~~ include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1374:32: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1374 | { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, | ^~~~~~~~~~~~~~~~~~~~~ include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1376:32: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1376 | { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, | ^~~~~~~~~~~~~~~~~~~~~ include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1378:32: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1378 | { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, | ^~~~~~~~~~~~~~~~~~~~~ include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1380:32: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1380 | { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, | ^~~~~~~~~~~~~~~~~~~~~ include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1382:32: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1382 | { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, | ^~~~~~~~~~~~~~~~~~~~~ include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1384:32: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1384 | { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, | ^~~~~~~~~~~~~~~~~~~~~ include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1386:32: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1386 | { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, | ^~~~~~~~~~~~~~~~~~~~~ include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) vim +7 include/vdso/bits.h 3945ff37d2f48d Vincenzo Frascino 2020-03-20 6 3945ff37d2f48d Vincenzo Frascino 2020-03-20 @7 #define BIT(nr) (UL(1) << (nr)) cbdb1f163af2bb Andy Shevchenko 2022-11-28 8 #define BIT_ULL(nr) (ULL(1) << (nr)) 3945ff37d2f48d Vincenzo Frascino 2020-03-20 9 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 2/3] pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28 2023-10-17 10:46 [PATCH v2 0/3] Add missing port pins for RZ/Five SoC Prabhakar 2023-10-17 10:46 ` [PATCH v2 1/3] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro Prabhakar @ 2023-10-17 10:46 ` Prabhakar 2023-10-17 10:46 ` [PATCH v2 3/3] riscv: dts: renesas: r9a07g043f: Update gpio-ranges property Prabhakar 2023-11-29 14:43 ` [PATCH v2 0/3] Add missing port pins for RZ/Five SoC Lad, Prabhakar 3 siblings, 0 replies; 9+ messages in thread From: Prabhakar @ 2023-10-17 10:46 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Linus Walleij Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-riscv, linux-gpio, linux-kernel, linux-renesas-soc, Biju Das, Claudiu Beznea, Prabhakar, Lad Prabhakar From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Add the missing port pins P19 to P28 for RZ/Five SoC. These additional pins provide expanded capabilities and are exclusive to the RZ/Five SoC. Couple of port pins have different configuration and is not identical for the complete port so introduced struct rzg2l_variable_pin_cfg to handle such cases and introduced PIN_CFG_VARIABLE macro. The actual pin config is then assigned rzg2l_pinctrl_get_variable_pin_cfg(). Add an additional check in rzg2l_gpio_get_gpioint() to only allow GPIO pins which support interrupt facility. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 215 +++++++++++++++++++++++- 1 file changed, 213 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index b0aeeb5ef3fa..b3c66eb1835a 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -57,6 +57,8 @@ #define PIN_CFG_FILCLKSEL BIT(12) #define PIN_CFG_IOLH_C BIT(13) #define PIN_CFG_SOFT_PS BIT(14) +#define PIN_CFG_VARIABLE BIT(15) +#define PIN_CFG_NOGPIO_INT BIT(16) #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ (PIN_CFG_IOLH_##group | \ @@ -82,6 +84,11 @@ */ #define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) > 0 ? ((u64)(GENMASK_ULL(((n) - 1 + 28), 28))) : 0) | \ ((a) << 20) | (f)) +/* + * m indicates the bitmap of supported pins, a is the register index + * and f is pin configuration capabilities supported. + */ +#define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (((u64)(m) << 28) | ((a) << 20) | (f)) #define RZG2L_GPIO_PORT_GET_PINMAP(x) (((x) & GENMASK_ULL(35, 28)) >> 28) #define RZG2L_GPIO_PORT_GET_PINCNT(x) (hweight8(RZG2L_GPIO_PORT_GET_PINMAP((x)))) @@ -185,6 +192,18 @@ struct rzg2l_dedicated_configs { u64 config; }; +/** + * struct rzg2l_variable_pin_cfg - pin data cfg + * @cfg: port pin configuration + * @port: port number + * @pin: port pin + */ +struct rzg2l_variable_pin_cfg { + u32 cfg; + u8 port; + u8 pin; +}; + struct rzg2l_pinctrl_data { const char * const *port_pins; const u64 *port_pin_configs; @@ -193,6 +212,8 @@ struct rzg2l_pinctrl_data { unsigned int n_port_pins; unsigned int n_dedicated_pins; const struct rzg2l_hwcfg *hwcfg; + const struct rzg2l_variable_pin_cfg *variable_pin_cfg; + unsigned int n_variable_pin_cfg; }; /** @@ -228,6 +249,158 @@ struct rzg2l_pinctrl { static const u16 available_ps[] = { 1800, 2500, 3300 }; +#ifdef CONFIG_RISCV +static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, + u64 pincfg, + unsigned int port, + u8 pin) +{ + unsigned int i; + u8 pincount; + u8 pinmap; + u32 off; + + if (!pctrl->data->n_variable_pin_cfg) + return pincfg; + + for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) { + if (pctrl->data->variable_pin_cfg[i].port == port && + pctrl->data->variable_pin_cfg[i].pin == pin) + break; + } + if (i == pctrl->data->n_variable_pin_cfg) + return pincfg; + + pinmap = RZG2L_GPIO_PORT_GET_PINMAP(pincfg); + pincount = RZG2L_GPIO_PORT_GET_PINCNT(pincfg); + off = RZG2L_PIN_CFG_TO_PORT_OFFSET(pincfg); + + if (pinmap == pincount) + return RZG2L_GPIO_PORT_PACK(pincount, off, pctrl->data->variable_pin_cfg[i].cfg); + + return RZG2L_GPIO_PORT_SPARSE_PACK(pinmap, off, pctrl->data->variable_pin_cfg[i].cfg); +} + +static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] = { + { + .port = 20, + .pin = 0, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 1, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 2, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 3, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 4, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 5, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 6, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 7, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 23, + .pin = 1, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT + }, + { + .port = 23, + .pin = 2, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 23, + .pin = 3, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 23, + .pin = 4, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 23, + .pin = 5, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 0, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 1, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 2, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 3, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 4, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 5, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_NOGPIO_INT, + }, +}; +#endif + static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { @@ -1320,6 +1493,27 @@ static const u64 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), +#ifdef CONFIG_RISCV + /* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */ + RZG2L_GPIO_PORT_PACK(8, 0x07, PIN_CFG_VARIABLE), /* P20 */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */ + RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x3e, 0x0a, PIN_CFG_VARIABLE), /* P23 */ + RZG2L_GPIO_PORT_PACK(6, 0x0b, PIN_CFG_VARIABLE), /* P24 */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_FILONOFF | + PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_NOGPIO_INT), /* P25 */ + 0x0, /* Dummy port P26 */ + 0x0, /* Dummy port P27 */ + RZG2L_GPIO_PORT_PACK(6, 0x0f, PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_NOGPIO_INT), /* P28 */ +#endif }; static const u64 r9a08g045_gpio_configs[] = { @@ -1478,12 +1672,18 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = { PIN_CFG_IO_VMC_SD1)) }, }; -static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data) +static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) { + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; + const struct rzg2l_pinctrl_data *data = pctrl->data; + u64 *pin_data = pin_desc->drv_data; unsigned int gpioint; unsigned int i; u32 port, bit; + if (*pin_data & PIN_CFG_NOGPIO_INT) + return -EINVAL; + port = virq / 8; bit = virq % 8; @@ -1593,7 +1793,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, unsigned long flags; int gpioint, irq; - gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data); + gpioint = rzg2l_gpio_get_gpioint(child, pctrl); if (gpioint < 0) return gpioint; @@ -1778,6 +1978,13 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) if (i && !(i % RZG2L_PINS_PER_PORT)) j++; pin_data[i] = pctrl->data->port_pin_configs[j]; +#ifdef CONFIG_RISCV + if (pin_data[i] & PIN_CFG_VARIABLE) + pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl, + pin_data[i], + j, + i % RZG2L_PINS_PER_PORT); +#endif pins[i].drv_data = &pin_data[i]; } @@ -1925,6 +2132,10 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), .hwcfg = &rzg2l_hwcfg, +#ifdef CONFIG_RISCV + .variable_pin_cfg = r9a07g043f_variable_pin_cfg, + .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg), +#endif }; static struct rzg2l_pinctrl_data r9a07g044_data = { -- 2.34.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 3/3] riscv: dts: renesas: r9a07g043f: Update gpio-ranges property 2023-10-17 10:46 [PATCH v2 0/3] Add missing port pins for RZ/Five SoC Prabhakar 2023-10-17 10:46 ` [PATCH v2 1/3] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro Prabhakar 2023-10-17 10:46 ` [PATCH v2 2/3] pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28 Prabhakar @ 2023-10-17 10:46 ` Prabhakar 2023-11-29 14:43 ` [PATCH v2 0/3] Add missing port pins for RZ/Five SoC Lad, Prabhakar 3 siblings, 0 replies; 9+ messages in thread From: Prabhakar @ 2023-10-17 10:46 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Linus Walleij Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-riscv, linux-gpio, linux-kernel, linux-renesas-soc, Biju Das, Claudiu Beznea, Prabhakar, Lad Prabhakar From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> On RZ/Five we have additional pins compared to the RZ/G2UL SoC so update the gpio-ranges property in RZ/Five SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index b0796015e36b..e68a91c9fe77 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -42,6 +42,10 @@ cpu0_intc: interrupt-controller { }; }; +&pinctrl { + gpio-ranges = <&pinctrl 0 0 232>; +}; + &soc { dma-noncoherent; interrupt-parent = <&plic>; -- 2.34.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 0/3] Add missing port pins for RZ/Five SoC 2023-10-17 10:46 [PATCH v2 0/3] Add missing port pins for RZ/Five SoC Prabhakar ` (2 preceding siblings ...) 2023-10-17 10:46 ` [PATCH v2 3/3] riscv: dts: renesas: r9a07g043f: Update gpio-ranges property Prabhakar @ 2023-11-29 14:43 ` Lad, Prabhakar 2023-11-29 15:31 ` Geert Uytterhoeven 3 siblings, 1 reply; 9+ messages in thread From: Lad, Prabhakar @ 2023-11-29 14:43 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Linus Walleij Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-riscv, linux-gpio, linux-kernel, linux-renesas-soc, Biju Das, Claudiu Beznea, Lad Prabhakar Hi Geert, On Tue, Oct 17, 2023 at 11:47 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Hi Geert, > > This patch series intends to incorporate the absent port pins P19 to P28, > which are exclusively available on the RZ/Five SoC. > > Cheers, > Prabhakar > > RFC -> v2: > * Fixed review comments pointed by Geert & Biju > > RFC: https://lore.kernel.org/lkml/20230630120433.49529-3-prabhakar.mahadev-lad.rj@bp.renesas.com/T/ > > Lad Prabhakar (3): > pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() > macro > pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28 > riscv: dts: renesas: r9a07g043f: Update gpio-ranges property > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 + > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 263 ++++++++++++++++++-- > 2 files changed, 242 insertions(+), 25 deletions(-) > Gentle ping. Cheers, Prabhakar ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 0/3] Add missing port pins for RZ/Five SoC 2023-11-29 14:43 ` [PATCH v2 0/3] Add missing port pins for RZ/Five SoC Lad, Prabhakar @ 2023-11-29 15:31 ` Geert Uytterhoeven 2023-11-30 8:48 ` Lad, Prabhakar 0 siblings, 1 reply; 9+ messages in thread From: Geert Uytterhoeven @ 2023-11-29 15:31 UTC (permalink / raw) To: Lad, Prabhakar Cc: Magnus Damm, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-riscv, linux-gpio, linux-kernel, linux-renesas-soc, Biju Das, Claudiu Beznea, Lad Prabhakar Hi Prabhakar, On Wed, Nov 29, 2023 at 3:44 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Tue, Oct 17, 2023 at 11:47 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > This patch series intends to incorporate the absent port pins P19 to P28, > > which are exclusively available on the RZ/Five SoC. > > > > Cheers, > > Prabhakar > > > > RFC -> v2: > > * Fixed review comments pointed by Geert & Biju > > > > RFC: https://lore.kernel.org/lkml/20230630120433.49529-3-prabhakar.mahadev-lad.rj@bp.renesas.com/T/ > > > > Lad Prabhakar (3): > > pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() > > macro > > pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28 > > riscv: dts: renesas: r9a07g043f: Update gpio-ranges property > > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 + > > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 263 ++++++++++++++++++-- > > 2 files changed, 242 insertions(+), 25 deletions(-) > > > Gentle ping. As the kernel test robot reported a build issue for PATCH 1/3, I had removed this series from my review queue. Do you still want me to review v2, or do you want to send a v3 first? Thanks! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 0/3] Add missing port pins for RZ/Five SoC 2023-11-29 15:31 ` Geert Uytterhoeven @ 2023-11-30 8:48 ` Lad, Prabhakar 2023-11-30 9:54 ` Geert Uytterhoeven 0 siblings, 1 reply; 9+ messages in thread From: Lad, Prabhakar @ 2023-11-30 8:48 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Magnus Damm, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-riscv, linux-gpio, linux-kernel, linux-renesas-soc, Biju Das, Claudiu Beznea, Lad Prabhakar Hi Geert, On Wed, Nov 29, 2023 at 3:32 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Wed, Nov 29, 2023 at 3:44 PM Lad, Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > On Tue, Oct 17, 2023 at 11:47 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > This patch series intends to incorporate the absent port pins P19 to P28, > > > which are exclusively available on the RZ/Five SoC. > > > > > > Cheers, > > > Prabhakar > > > > > > RFC -> v2: > > > * Fixed review comments pointed by Geert & Biju > > > > > > RFC: https://lore.kernel.org/lkml/20230630120433.49529-3-prabhakar.mahadev-lad.rj@bp.renesas.com/T/ > > > > > > Lad Prabhakar (3): > > > pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() > > > macro > > > pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28 > > > riscv: dts: renesas: r9a07g043f: Update gpio-ranges property > > > > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 + > > > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 263 ++++++++++++++++++-- > > > 2 files changed, 242 insertions(+), 25 deletions(-) > > > > > Gentle ping. > > As the kernel test robot reported a build issue for PATCH 1/3, I had > removed this series from my review queue. Strange patchwork status didnt mention it as "rejected". > Do you still want me to review v2, or do you want to send a v3 first? > No worries, I'll send a v3 and we can go from there. Cheers, Prabhakar ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 0/3] Add missing port pins for RZ/Five SoC 2023-11-30 8:48 ` Lad, Prabhakar @ 2023-11-30 9:54 ` Geert Uytterhoeven 0 siblings, 0 replies; 9+ messages in thread From: Geert Uytterhoeven @ 2023-11-30 9:54 UTC (permalink / raw) To: Lad, Prabhakar Cc: Magnus Damm, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-riscv, linux-gpio, linux-kernel, linux-renesas-soc, Biju Das, Claudiu Beznea, Lad Prabhakar Hi Prabhakar, On Thu, Nov 30, 2023 at 9:48 AM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Wed, Nov 29, 2023 at 3:32 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > On Wed, Nov 29, 2023 at 3:44 PM Lad, Prabhakar > > <prabhakar.csengg@gmail.com> wrote: > > > On Tue, Oct 17, 2023 at 11:47 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > This patch series intends to incorporate the absent port pins P19 to P28, > > > > which are exclusively available on the RZ/Five SoC. > > > > > > > > Cheers, > > > > Prabhakar > > > > > > > > RFC -> v2: > > > > * Fixed review comments pointed by Geert & Biju > > > > > > > > RFC: https://lore.kernel.org/lkml/20230630120433.49529-3-prabhakar.mahadev-lad.rj@bp.renesas.com/T/ > > > > > > > > Lad Prabhakar (3): > > > > pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() > > > > macro > > > > pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28 > > > > riscv: dts: renesas: r9a07g043f: Update gpio-ranges property > > > > > > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 + > > > > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 263 ++++++++++++++++++-- > > > > 2 files changed, 242 insertions(+), 25 deletions(-) > > > > > > > Gentle ping. > > > > As the kernel test robot reported a build issue for PATCH 1/3, I had > > removed this series from my review queue. > Strange patchwork status didnt mention it as "rejected". Actually I do not use patchwork that much... > > Do you still want me to review v2, or do you want to send a v3 first? > > > No worries, I'll send a v3 and we can go from there. OK. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-11-30 9:55 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-10-17 10:46 [PATCH v2 0/3] Add missing port pins for RZ/Five SoC Prabhakar 2023-10-17 10:46 ` [PATCH v2 1/3] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro Prabhakar 2023-10-17 15:42 ` kernel test robot 2023-10-17 10:46 ` [PATCH v2 2/3] pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28 Prabhakar 2023-10-17 10:46 ` [PATCH v2 3/3] riscv: dts: renesas: r9a07g043f: Update gpio-ranges property Prabhakar 2023-11-29 14:43 ` [PATCH v2 0/3] Add missing port pins for RZ/Five SoC Lad, Prabhakar 2023-11-29 15:31 ` Geert Uytterhoeven 2023-11-30 8:48 ` Lad, Prabhakar 2023-11-30 9:54 ` Geert Uytterhoeven
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