* [PATCH V3 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver
@ 2023-10-27 7:14 Linhua Xu
2023-10-27 7:14 ` [PATCH V3 1/6] pinctrl: sprd: Modify pull-up parameters Linhua Xu
` (5 more replies)
0 siblings, 6 replies; 13+ messages in thread
From: Linhua Xu @ 2023-10-27 7:14 UTC (permalink / raw)
To: Linus Walleij
Cc: Orson Zhai, Baolin Wang, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Linhua Xu, Zhirong Qiu, Xiongpeng Wu
From: Linhua Xu <Linhua.Xu@unisoc.com>
Recently, some bugs have been discovered during use, and patch1 and patch2
are bug fixes. Also, this patchset add new features: patch3 is for
compatibility with more platforms, patch4 Increase the range of register values,
patch5 add pinctrl support for UMS512, patch6 add pinctrl support for UMS9621.
change in V3
-Add platform structure
-Add the mask definition
-Modify register definition format
-Improve code readability
-Add fixes tag
Linhua Xu (6):
pinctrl: sprd: Modify pull-up parameters
pinctrl: sprd: Fix the incorrect mask and shift definition
pinctrl: sprd: Move common and misc offset parameters to private data
pinctrl: sprd: Increase the range of register values
pinctrl: sprd: Add pinctrl support for UMS512
pinctrl: sprd: Add pinctrl support for UMS9621
drivers/pinctrl/sprd/Kconfig | 22 +
drivers/pinctrl/sprd/Makefile | 2 +
drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c | 12 +-
drivers/pinctrl/sprd/pinctrl-sprd-ums512.c | 881 +++++++++++++++
drivers/pinctrl/sprd/pinctrl-sprd-ums9621.c | 1120 +++++++++++++++++++
drivers/pinctrl/sprd/pinctrl-sprd.c | 35 +-
drivers/pinctrl/sprd/pinctrl-sprd.h | 49 +-
7 files changed, 2087 insertions(+), 34 deletions(-)
create mode 100644 drivers/pinctrl/sprd/pinctrl-sprd-ums512.c
create mode 100644 drivers/pinctrl/sprd/pinctrl-sprd-ums9621.c
--
2.17.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH V3 1/6] pinctrl: sprd: Modify pull-up parameters
2023-10-27 7:14 [PATCH V3 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linhua Xu
@ 2023-10-27 7:14 ` Linhua Xu
2023-10-27 11:29 ` Andy Shevchenko
2023-10-27 7:14 ` [PATCH V3 2/6] pinctrl: sprd: Fix the incorrect mask and shift definition Linhua Xu
` (4 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Linhua Xu @ 2023-10-27 7:14 UTC (permalink / raw)
To: Linus Walleij
Cc: Orson Zhai, Baolin Wang, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Linhua Xu, Zhirong Qiu, Xiongpeng Wu
From: Linhua Xu <Linhua.Xu@unisoc.com>
For UNISOC pin controller, there are three different configurations of
pull-up drive current. Modify the 20K pull-up resistor configuration and
add the 1.8K pull-up resistor configuration.
Fixes:<1fb4b907e808> ("pinctrl: sprd: Add Spreadtrum pin control driver")
Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
---
drivers/pinctrl/sprd/pinctrl-sprd.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c
index ca9659f4e4b1..74d8f8c3b9b6 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd.c
+++ b/drivers/pinctrl/sprd/pinctrl-sprd.c
@@ -71,7 +71,8 @@
#define SLEEP_PULL_UP_MASK 0x1
#define SLEEP_PULL_UP_SHIFT 3
-#define PULL_UP_4_7K (BIT(12) | BIT(7))
+#define PULL_UP_1_8K (BIT(12) | BIT(7))
+#define PULL_UP_4_7K BIT(12)
#define PULL_UP_20K BIT(7)
#define PULL_UP_MASK 0x21
#define PULL_UP_SHIFT 7
@@ -497,7 +498,7 @@ static int sprd_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id,
break;
case PIN_CONFIG_BIAS_DISABLE:
if ((reg & (SLEEP_PULL_DOWN | SLEEP_PULL_UP)) ||
- (reg & (PULL_DOWN | PULL_UP_4_7K | PULL_UP_20K)))
+ (reg & (PULL_DOWN | PULL_UP_4_7K | PULL_UP_20K | PULL_UP_1_8K)))
return -EINVAL;
arg = 1;
@@ -699,6 +700,8 @@ static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id,
val |= PULL_UP_20K;
else if (arg == 4700)
val |= PULL_UP_4_7K;
+ else if (arg == 1800)
+ val |= PULL_UP_1_8K;
mask = PULL_UP_MASK;
shift = PULL_UP_SHIFT;
@@ -711,7 +714,7 @@ static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id,
} else {
val = shift = 0;
mask = PULL_DOWN | PULL_UP_20K |
- PULL_UP_4_7K;
+ PULL_UP_4_7K | PULL_UP_1_8K;
}
break;
case PIN_CONFIG_SLEEP_HARDWARE_STATE:
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH V3 2/6] pinctrl: sprd: Fix the incorrect mask and shift definition
2023-10-27 7:14 [PATCH V3 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linhua Xu
2023-10-27 7:14 ` [PATCH V3 1/6] pinctrl: sprd: Modify pull-up parameters Linhua Xu
@ 2023-10-27 7:14 ` Linhua Xu
2023-10-27 11:32 ` Andy Shevchenko
2023-10-27 7:14 ` [PATCH V3 3/6] pinctrl: sprd: Move common and misc offset parameters to private data Linhua Xu
` (3 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Linhua Xu @ 2023-10-27 7:14 UTC (permalink / raw)
To: Linus Walleij
Cc: Orson Zhai, Baolin Wang, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Linhua Xu, Zhirong Qiu, Xiongpeng Wu
From: Linhua Xu <Linhua.Xu@unisoc.com>
Pull-up and pull-down are mutually exclusive. When setting one of them,
the bit of the other needs to be clear. Now, there are cases where pull-up
and pull-down are set at the same time in the code, thus fix them.
Fixes:<1fb4b907e808> ("pinctrl: sprd: Add Spreadtrum pin control driver")
Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
---
drivers/pinctrl/sprd/pinctrl-sprd.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c
index 74d8f8c3b9b6..b7a3cb9e7a61 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd.c
+++ b/drivers/pinctrl/sprd/pinctrl-sprd.c
@@ -60,22 +60,22 @@
#define DRIVE_STRENGTH_SHIFT 19
#define SLEEP_PULL_DOWN BIT(2)
-#define SLEEP_PULL_DOWN_MASK 0x1
+#define SLEEP_PULL_DOWN_MASK GENMASK(1, 0)
#define SLEEP_PULL_DOWN_SHIFT 2
#define PULL_DOWN BIT(6)
-#define PULL_DOWN_MASK 0x1
+#define PULL_DOWN_MASK (GENMASK(1, 0) | BIT(6))
#define PULL_DOWN_SHIFT 6
#define SLEEP_PULL_UP BIT(3)
-#define SLEEP_PULL_UP_MASK 0x1
-#define SLEEP_PULL_UP_SHIFT 3
+#define SLEEP_PULL_UP_MASK GENMASK(1, 0)
+#define SLEEP_PULL_UP_SHIFT 2
#define PULL_UP_1_8K (BIT(12) | BIT(7))
#define PULL_UP_4_7K BIT(12)
#define PULL_UP_20K BIT(7)
-#define PULL_UP_MASK 0x21
-#define PULL_UP_SHIFT 7
+#define PULL_UP_MASK (GENMASK(1, 0) | BIT(6))
+#define PULL_UP_SHIFT 6
#define INPUT_SCHMITT BIT(11)
#define INPUT_SCHMITT_MASK 0x1
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH V3 3/6] pinctrl: sprd: Move common and misc offset parameters to private data
2023-10-27 7:14 [PATCH V3 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linhua Xu
2023-10-27 7:14 ` [PATCH V3 1/6] pinctrl: sprd: Modify pull-up parameters Linhua Xu
2023-10-27 7:14 ` [PATCH V3 2/6] pinctrl: sprd: Fix the incorrect mask and shift definition Linhua Xu
@ 2023-10-27 7:14 ` Linhua Xu
2023-10-27 11:24 ` Andy Shevchenko
2023-10-27 7:14 ` [PATCH V3 4/6] pinctrl: sprd: Increase the range of register values Linhua Xu
` (2 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Linhua Xu @ 2023-10-27 7:14 UTC (permalink / raw)
To: Linus Walleij
Cc: Orson Zhai, Baolin Wang, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Linhua Xu, Zhirong Qiu, Xiongpeng Wu
From: Linhua Xu <Linhua.Xu@unisoc.com>
For UNISOC pin controller, the offset values of the common
register and misc register will be different. So add SoC
structure in sprd_pinctrl_of_match() and parse it in sprd-pinctrl_core.
Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
---
drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c | 12 +++++++++---
drivers/pinctrl/sprd/pinctrl-sprd.c | 14 ++++++++++----
drivers/pinctrl/sprd/pinctrl-sprd.h | 5 +++++
3 files changed, 24 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c
index d14f382f2392..6835f0f85888 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c
+++ b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c
@@ -10,6 +10,9 @@
#include "pinctrl-sprd.h"
+#define PINCTRL_REG_OFFSET 0x0020
+#define PINCTRL_REG_MISC_OFFSET 0x4020
+
enum sprd_sc9860_pins {
/* pin global control register 0 */
SC9860_VIO28_0_IRTE = SPRD_PIN_INFO(0, GLOBAL_CTRL_PIN, 11, 1, 0),
@@ -923,6 +926,11 @@ static struct sprd_pins_info sprd_sc9860_pins_info[] = {
SPRD_PINCTRL_PIN(SC9860_RFCTL39_MISC),
};
+static const struct sprd_pinctrl_priv_data sc9860_data = {
+ .common_offset = PINCTRL_REG_OFFSET,
+ .misc_offset = PINCTRL_REG_MISC_OFFSET,
+};
+
static int sprd_pinctrl_probe(struct platform_device *pdev)
{
return sprd_pinctrl_core_probe(pdev, sprd_sc9860_pins_info,
@@ -930,9 +938,7 @@ static int sprd_pinctrl_probe(struct platform_device *pdev)
}
static const struct of_device_id sprd_pinctrl_of_match[] = {
- {
- .compatible = "sprd,sc9860-pinctrl",
- },
+ { .compatible = "sprd,sc9860-pinctrl", .data = &sc9860_data},
{ },
};
MODULE_DEVICE_TABLE(of, sprd_pinctrl_of_match);
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c
index b7a3cb9e7a61..7a79735ec30a 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd.c
+++ b/drivers/pinctrl/sprd/pinctrl-sprd.c
@@ -30,8 +30,6 @@
#include "pinctrl-sprd.h"
#define PINCTRL_BIT_MASK(width) (~(~0UL << (width)))
-#define PINCTRL_REG_OFFSET 0x20
-#define PINCTRL_REG_MISC_OFFSET 0x4020
#define PINCTRL_REG_LEN 0x4
#define PIN_FUNC_MASK (BIT(4) | BIT(5))
@@ -149,12 +147,14 @@ struct sprd_pinctrl_soc_info {
* @pctl: pointer to the pinctrl handle
* @base: base address of the controller
* @info: pointer to SoC's pins description information
+ * @pdata: pointer SoC's private data structure
*/
struct sprd_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
struct sprd_pinctrl_soc_info *info;
+ const struct sprd_pinctrl_priv_data *pdata;
};
#define SPRD_PIN_CONFIG_CONTROL (PIN_CONFIG_END + 1)
@@ -1026,12 +1026,12 @@ static int sprd_pinctrl_add_pins(struct sprd_pinctrl *sprd_pctl,
ctrl_pin++;
} else if (pin->type == COMMON_PIN) {
pin->reg = (unsigned long)sprd_pctl->base +
- PINCTRL_REG_OFFSET + PINCTRL_REG_LEN *
+ sprd_pctl->pdata->common_offset + PINCTRL_REG_LEN *
(i - ctrl_pin);
com_pin++;
} else if (pin->type == MISC_PIN) {
pin->reg = (unsigned long)sprd_pctl->base +
- PINCTRL_REG_MISC_OFFSET + PINCTRL_REG_LEN *
+ sprd_pctl->pdata->misc_offset + PINCTRL_REG_LEN *
(i - ctrl_pin - com_pin);
}
}
@@ -1053,6 +1053,7 @@ int sprd_pinctrl_core_probe(struct platform_device *pdev,
struct sprd_pinctrl *sprd_pctl;
struct sprd_pinctrl_soc_info *pinctrl_info;
struct pinctrl_pin_desc *pin_desc;
+ const struct sprd_pinctrl_priv_data *priv_data;
int ret, i;
sprd_pctl = devm_kzalloc(&pdev->dev, sizeof(struct sprd_pinctrl),
@@ -1070,6 +1071,11 @@ int sprd_pinctrl_core_probe(struct platform_device *pdev,
if (!pinctrl_info)
return -ENOMEM;
+ priv_data = of_device_get_match_data(&pdev->dev);
+ if (!priv_data)
+ return -EINVAL;
+
+ sprd_pctl->pdata = priv_data;
sprd_pctl->info = pinctrl_info;
sprd_pctl->dev = &pdev->dev;
platform_set_drvdata(pdev, sprd_pctl);
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.h b/drivers/pinctrl/sprd/pinctrl-sprd.h
index 69544a3cd635..23bced4665f1 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd.h
+++ b/drivers/pinctrl/sprd/pinctrl-sprd.h
@@ -50,6 +50,11 @@ struct sprd_pins_info {
unsigned int reg;
};
+struct sprd_pinctrl_priv_data {
+ unsigned long common_offset;
+ unsigned long misc_offset;
+};
+
int sprd_pinctrl_core_probe(struct platform_device *pdev,
struct sprd_pins_info *sprd_soc_pin_info,
int pins_cnt);
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH V3 4/6] pinctrl: sprd: Increase the range of register values
2023-10-27 7:14 [PATCH V3 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linhua Xu
` (2 preceding siblings ...)
2023-10-27 7:14 ` [PATCH V3 3/6] pinctrl: sprd: Move common and misc offset parameters to private data Linhua Xu
@ 2023-10-27 7:14 ` Linhua Xu
2023-10-27 11:39 ` kernel test robot
2023-10-27 7:14 ` [PATCH V3 5/6] pinctrl: sprd: Add pinctrl support for UMS512 Linhua Xu
2023-10-27 7:14 ` [PATCH V3 6/6] pinctrl: sprd: Add pinctrl support for UMS9621 Linhua Xu
5 siblings, 1 reply; 13+ messages in thread
From: Linhua Xu @ 2023-10-27 7:14 UTC (permalink / raw)
To: Linus Walleij
Cc: Orson Zhai, Baolin Wang, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Linhua Xu, Zhirong Qiu, Xiongpeng Wu
From: Linhua Xu <Linhua.Xu@unisoc.com>
As the UNISOC pin controller version iterates, more registers are required
to meet new functional requirements. Thus modify them.
Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
---
drivers/pinctrl/sprd/pinctrl-sprd.h | 44 +++++++++++++++++------------
1 file changed, 26 insertions(+), 18 deletions(-)
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.h b/drivers/pinctrl/sprd/pinctrl-sprd.h
index 23bced4665f1..a6ba75313da0 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd.h
+++ b/drivers/pinctrl/sprd/pinctrl-sprd.h
@@ -7,30 +7,38 @@
#ifndef __PINCTRL_SPRD_H__
#define __PINCTRL_SPRD_H__
+#include <linux/bits.h>
+
struct platform_device;
-#define NUM_OFFSET (20)
-#define TYPE_OFFSET (16)
-#define BIT_OFFSET (8)
-#define WIDTH_OFFSET (4)
+#define NUM_OFFSET 22
+#define TYPE_OFFSET 18
+#define BIT_OFFSET 10
+#define WIDTH_OFFSET 6
+
+#define NUM_MASK GENMASK(10, 0)
+#define TYPE_MASK GENMASK(3, 0)
+#define BIT_MASK GENMASK(7, 0)
+#define WIDTH_MASK GENMASK(3, 0)
+#define REG_MASK GENMASK(5, 0)
-#define SPRD_PIN_INFO(num, type, offset, width, reg) \
- (((num) & 0xFFF) << NUM_OFFSET | \
- ((type) & 0xF) << TYPE_OFFSET | \
- ((offset) & 0xFF) << BIT_OFFSET | \
- ((width) & 0xF) << WIDTH_OFFSET | \
- ((reg) & 0xF))
+#define SPRD_PIN_INFO(num, type, offset, width, reg) \
+ (((num) & NUM_MASK) << NUM_OFFSET | \
+ ((type) & TYPE_MASK) << TYPE_OFFSET | \
+ ((offset) & BIT_MASK) << BIT_OFFSET | \
+ ((width) & WIDTH_MASK) << WIDTH_OFFSET | \
+ ((reg) & REG_MASK))
#define SPRD_PINCTRL_PIN(pin) SPRD_PINCTRL_PIN_DATA(pin, #pin)
-#define SPRD_PINCTRL_PIN_DATA(a, b) \
- { \
- .name = b, \
- .num = (((a) >> NUM_OFFSET) & 0xfff), \
- .type = (((a) >> TYPE_OFFSET) & 0xf), \
- .bit_offset = (((a) >> BIT_OFFSET) & 0xff), \
- .bit_width = ((a) >> WIDTH_OFFSET & 0xf), \
- .reg = ((a) & 0xf) \
+#define SPRD_PINCTRL_PIN_DATA(a, b) \
+ { \
+ .name = b, \
+ .num = (((a) >> NUM_OFFSET) & NUM_MASK), \
+ .type = (((a) >> TYPE_OFFSET) & TYPE_MASK), \
+ .bit_offset = (((a) & BIT_OFFSET) & BIT_MASK), \
+ .bit_width = (((a) & WIDTH_OFFSET) & WIDTH_MASK), \
+ .reg = ((a) & REG_MASK) \
}
enum pin_type {
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH V3 5/6] pinctrl: sprd: Add pinctrl support for UMS512
2023-10-27 7:14 [PATCH V3 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linhua Xu
` (3 preceding siblings ...)
2023-10-27 7:14 ` [PATCH V3 4/6] pinctrl: sprd: Increase the range of register values Linhua Xu
@ 2023-10-27 7:14 ` Linhua Xu
2023-10-27 11:40 ` Andy Shevchenko
2023-10-27 7:14 ` [PATCH V3 6/6] pinctrl: sprd: Add pinctrl support for UMS9621 Linhua Xu
5 siblings, 1 reply; 13+ messages in thread
From: Linhua Xu @ 2023-10-27 7:14 UTC (permalink / raw)
To: Linus Walleij
Cc: Orson Zhai, Baolin Wang, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Linhua Xu, Zhirong Qiu, Xiongpeng Wu
From: Linhua Xu <Linhua.Xu@unisoc.com>
Add the pin control driver for UNISOC UMS512 platform.
Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
---
drivers/pinctrl/sprd/Kconfig | 11 +
drivers/pinctrl/sprd/Makefile | 1 +
drivers/pinctrl/sprd/pinctrl-sprd-ums512.c | 881 +++++++++++++++++++++
3 files changed, 893 insertions(+)
create mode 100644 drivers/pinctrl/sprd/pinctrl-sprd-ums512.c
diff --git a/drivers/pinctrl/sprd/Kconfig b/drivers/pinctrl/sprd/Kconfig
index eef35d01b770..a2a653c63137 100644
--- a/drivers/pinctrl/sprd/Kconfig
+++ b/drivers/pinctrl/sprd/Kconfig
@@ -19,3 +19,14 @@ config PINCTRL_SPRD_SC9860
select PINCTRL_SPRD
help
Say Y here to enable Spreadtrum SC9860 pinctrl driver
+
+config PINCTRL_SPRD_UMS512
+ tristate "Spreadtrum ums512 pinctrl driver"
+ depends on ARCH_SPRD || COMPILE_TEST
+ select PINCTRL_SPRD
+ help
+ Say Y here to enable Spreadtrum ums512 pinctrl driver
+ Support pin function switching
+ Support pin drive capability configuration
+ Support pin pull-up and pull-down configuration
+ Support pin pull-up and pull-down configuration during sleep
diff --git a/drivers/pinctrl/sprd/Makefile b/drivers/pinctrl/sprd/Makefile
index 3d4989057739..e3509c2515c9 100644
--- a/drivers/pinctrl/sprd/Makefile
+++ b/drivers/pinctrl/sprd/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_PINCTRL_SPRD) += pinctrl-sprd.o
obj-$(CONFIG_PINCTRL_SPRD_SC9860) += pinctrl-sprd-sc9860.o
+obj-$(CONFIG_PINCTRL_SPRD_UMS512) += pinctrl-sprd-ums512.o
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd-ums512.c b/drivers/pinctrl/sprd/pinctrl-sprd-ums512.c
new file mode 100644
index 000000000000..ac155604ca5b
--- /dev/null
+++ b/drivers/pinctrl/sprd/pinctrl-sprd-ums512.c
@@ -0,0 +1,881 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Unisoc ums512 pinctrl driver
+ *
+ * Copyright (C) 2020 Unisoc, Inc.
+ * Author: linhua xu <linhua.xu@unisoc.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-sprd.h"
+
+#define PINCTRL_REG_OFFSET 0x0034
+#define PINCTRL_REG_MISC_OFFSET 0x0434
+
+enum sprd_ums512_pins {
+ /* UART_MATRIX_MTX_CFG */
+ UMS512_UART_INF6_SYS_SEL = SPRD_PIN_INFO(0, GLOBAL_CTRL_PIN, 28, 4, 1),
+ UMS512_UART_INF5_SYS_SEL = SPRD_PIN_INFO(1, GLOBAL_CTRL_PIN, 24, 4, 1),
+ UMS512_UART_INF4_SYS_SEL = SPRD_PIN_INFO(2, GLOBAL_CTRL_PIN, 20, 4, 1),
+ UMS512_UART_INF3_SYS_SEL = SPRD_PIN_INFO(3, GLOBAL_CTRL_PIN, 16, 4, 1),
+ UMS512_UART_INF2_INF3_LOOP = SPRD_PIN_INFO(4, GLOBAL_CTRL_PIN, 15, 1, 1),
+ UMS512_UART_INF2_INF4_LOOP = SPRD_PIN_INFO(5, GLOBAL_CTRL_PIN, 14, 1, 1),
+ UMS512_UART_INF2_SYS_SEL = SPRD_PIN_INFO(6, GLOBAL_CTRL_PIN, 10, 4, 1),
+ UMS512_UART_INF1_INF4_LOOP = SPRD_PIN_INFO(7, GLOBAL_CTRL_PIN, 9, 1, 1),
+ UMS512_UART_INF1_INF3_LOOP = SPRD_PIN_INFO(8, GLOBAL_CTRL_PIN, 8, 1, 1),
+ UMS512_UART_INF1_SYS_SEL = SPRD_PIN_INFO(9, GLOBAL_CTRL_PIN, 4, 4, 1),
+ UMS512_UART_INF0_SYS_SEL = SPRD_PIN_INFO(10, GLOBAL_CTRL_PIN, 0, 4, 1),
+
+ /* UART_MATRIX_MTX_CFG1 */
+ UMS512_UART_INF9_SYS_SEL = SPRD_PIN_INFO(11, GLOBAL_CTRL_PIN, 9, 4, 2),
+ UMS512_UART_INF8_SYS_SEL = SPRD_PIN_INFO(12, GLOBAL_CTRL_PIN, 5, 4, 2),
+ UMS512_UART_INF7_INF8_LOOP = SPRD_PIN_INFO(13, GLOBAL_CTRL_PIN, 4, 1, 2),
+ UMS512_UART_INF7_SYS_SEL = SPRD_PIN_INFO(14, GLOBAL_CTRL_PIN, 0, 4, 2),
+
+ /* IIS_MATRIX_MTX_CFG */
+ UMS512_IIS_INF4_INF3_LOOP = SPRD_PIN_INFO(15, GLOBAL_CTRL_PIN, 23, 1, 3),
+ UMS512_IIS_INF4_SYS_SEL = SPRD_PIN_INFO(16, GLOBAL_CTRL_PIN, 19, 4, 3),
+ UMS512_IIS_INF3_SYS_SEL = SPRD_PIN_INFO(17, GLOBAL_CTRL_PIN, 15, 4, 3),
+ UMS512_IIS_INF2_SYS_SEL = SPRD_PIN_INFO(18, GLOBAL_CTRL_PIN, 11, 4, 3),
+ UMS512_IIS_INF1_INF2_LOOP = SPRD_PIN_INFO(19, GLOBAL_CTRL_PIN, 10, 1, 3),
+ UMS512_IIS_INF1_SYS_SEL = SPRD_PIN_INFO(20, GLOBAL_CTRL_PIN, 6, 4, 3),
+ UMS512_IIS_INF0_INF2_LOOP = SPRD_PIN_INFO(21, GLOBAL_CTRL_PIN, 5, 1, 3),
+ UMS512_IIS_INF0_INF1_LOOP = SPRD_PIN_INFO(22, GLOBAL_CTRL_PIN, 4, 1, 3),
+ UMS512_IIS_INF0_SYS_SEL = SPRD_PIN_INFO(23, GLOBAL_CTRL_PIN, 0, 4, 3),
+
+ /* SIM_MATRIX_MTX_CFG */
+ UMS512_SIM_INF2_SYS_SEL = SPRD_PIN_INFO(24, GLOBAL_CTRL_PIN, 2, 1, 4),
+ UMS512_SIM_INF1_SYS_SEL = SPRD_PIN_INFO(25, GLOBAL_CTRL_PIN, 1, 1, 4),
+ UMS512_SIM_INFO_SYS_SEL = SPRD_PIN_INFO(26, GLOBAL_CTRL_PIN, 0, 1, 4),
+
+ /* SPI_MATRIX_MTX_CFG */
+ UMS512_SPI_INF3_SYS_SEL = SPRD_PIN_INFO(27, GLOBAL_CTRL_PIN, 3, 1, 5),
+ UMS512_SPI_INF2_SYS_SEL = SPRD_PIN_INFO(28, GLOBAL_CTRL_PIN, 2, 1, 5),
+ UMS512_SPI_INF1_SYS_SEL = SPRD_PIN_INFO(29, GLOBAL_CTRL_PIN, 1, 1, 5),
+ UMS512_SPI_INF0_SYS_SEL = SPRD_PIN_INFO(30, GLOBAL_CTRL_PIN, 0, 1, 5),
+
+ /* IIC_MATRIX_MTX_CFG */
+ UMS512_IIC_INF7_SYS_SEL = SPRD_PIN_INFO(31, GLOBAL_CTRL_PIN, 21, 3, 6),
+ UMS512_IIC_INF6_SYS_SEL = SPRD_PIN_INFO(32, GLOBAL_CTRL_PIN, 18, 3, 6),
+ UMS512_IIC_INF5_SYS_SEL = SPRD_PIN_INFO(33, GLOBAL_CTRL_PIN, 15, 3, 6),
+ UMS512_IIC_INF4_SYS_SEL = SPRD_PIN_INFO(34, GLOBAL_CTRL_PIN, 12, 3, 6),
+ UMS512_IIC_INF3_SYS_SEL = SPRD_PIN_INFO(35, GLOBAL_CTRL_PIN, 9, 3, 6),
+ UMS512_IIC_INF2_SYS_SEL = SPRD_PIN_INFO(36, GLOBAL_CTRL_PIN, 6, 3, 6),
+ UMS512_IIC_INF1_SYS_SEL = SPRD_PIN_INFO(37, GLOBAL_CTRL_PIN, 3, 3, 6),
+ UMS512_IIC_INF0_SYS_SEL = SPRD_PIN_INFO(38, GLOBAL_CTRL_PIN, 0, 3, 6),
+
+ /* PIN_CTRL_REG0 */
+ UMS512_PIN_CTRL_REG0 = SPRD_PIN_INFO(39, GLOBAL_CTRL_PIN, 0, 1, 7),
+
+ /* PIN_CTRL_REG1 */
+ UMS512_PIN_CTRL_REG1 = SPRD_PIN_INFO(40, GLOBAL_CTRL_PIN, 28, 4, 8),
+
+ /* PIN_CTRL_REG2 */
+ UMS512_UART_USB_PHY_SEL = SPRD_PIN_INFO(41, GLOBAL_CTRL_PIN, 31, 1, 9),
+ UMS512_USB_PHY_DM_OE = SPRD_PIN_INFO(42, GLOBAL_CTRL_PIN, 30, 1, 9),
+ UMS512_USB_PHY_DP_OE = SPRD_PIN_INFO(43, GLOBAL_CTRL_PIN, 29, 1, 9),
+
+ /* PIN_CTRL_REG3 */
+ UMS512_SP_EIC_DPAD3 = SPRD_PIN_INFO(44, GLOBAL_CTRL_PIN, 24, 8, 10),
+ UMS512_SP_EIC_DPAD2 = SPRD_PIN_INFO(45, GLOBAL_CTRL_PIN, 16, 8, 10),
+ UMS512_SP_EIC_DPAD1 = SPRD_PIN_INFO(46, GLOBAL_CTRL_PIN, 8, 8, 10),
+ UMS512_SP_EIC_DPAD0 = SPRD_PIN_INFO(47, GLOBAL_CTRL_PIN, 0, 8, 10),
+
+ /* PIN_CTRL_REG4 */
+ UMS512_SP_EIC_DPAD7 = SPRD_PIN_INFO(48, GLOBAL_CTRL_PIN, 24, 8, 11),
+ UMS512_SP_EIC_DPAD6 = SPRD_PIN_INFO(49, GLOBAL_CTRL_PIN, 16, 8, 11),
+ UMS512_SP_EIC_DPAD5 = SPRD_PIN_INFO(50, GLOBAL_CTRL_PIN, 8, 8, 11),
+ UMS512_SP_EIC_DPAD4 = SPRD_PIN_INFO(51, GLOBAL_CTRL_PIN, 0, 8, 11),
+
+ /* PIN_CTRL_REG5 */
+ UMS512_VBC_IIS_INF_SYS_SEL = SPRD_PIN_INFO(52, GLOBAL_CTRL_PIN, 20, 1, 12),
+ UMS512_CARD_DET_SEL = SPRD_PIN_INFO(53, GLOBAL_CTRL_PIN, 17, 3, 12),
+ UMS512_SIM0_DET_SEL = SPRD_PIN_INFO(54, GLOBAL_CTRL_PIN, 16, 1, 12),
+ UMS512_AP_SIM0_BD_EB = SPRD_PIN_INFO(55, GLOBAL_CTRL_PIN, 15, 1, 12),
+ UMS512_AP_EMMC_BD_EB = SPRD_PIN_INFO(56, GLOBAL_CTRL_PIN, 14, 1, 12),
+ UMS512_AP_SDIO2_BD_EB = SPRD_PIN_INFO(57, GLOBAL_CTRL_PIN, 13, 1, 12),
+ UMS512_AP_SDIO1_BD_EB = SPRD_PIN_INFO(58, GLOBAL_CTRL_PIN, 12, 1, 12),
+ UMS512_AP_SDIO0_BD_EB = SPRD_PIN_INFO(59, GLOBAL_CTRL_PIN, 11, 1, 12),
+ UMS512_PUBCP_SDIO_BD_EB = SPRD_PIN_INFO(60, GLOBAL_CTRL_PIN, 10, 1, 12),
+ UMS512_PUBCP_SIM1_BD_EB = SPRD_PIN_INFO(61, GLOBAL_CTRL_PIN, 9, 1, 12),
+ UMS512_PUBCP_SIM0_BD_EB = SPRD_PIN_INFO(62, GLOBAL_CTRL_PIN, 8, 1, 12),
+
+ /* Common pin registers definitions */
+ UMS512_EMMC_RST = SPRD_PIN_INFO(63, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_CMD = SPRD_PIN_INFO(64, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_D0 = SPRD_PIN_INFO(65, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_D3 = SPRD_PIN_INFO(66, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_D2 = SPRD_PIN_INFO(67, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_D5 = SPRD_PIN_INFO(68, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_CLK = SPRD_PIN_INFO(69, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_DS = SPRD_PIN_INFO(70, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_D1 = SPRD_PIN_INFO(71, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_D4 = SPRD_PIN_INFO(72, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_D6 = SPRD_PIN_INFO(73, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_D7 = SPRD_PIN_INFO(74, COMMON_PIN, 0, 0, 0),
+ UMS512_LCM_RSTN = SPRD_PIN_INFO(75, COMMON_PIN, 0, 0, 0),
+ UMS512_DSI_TE = SPRD_PIN_INFO(76, COMMON_PIN, 0, 0, 0),
+ UMS512_DCDC_ARM1_EN = SPRD_PIN_INFO(77, COMMON_PIN, 0, 0, 0),
+ UMS512_PTEST = SPRD_PIN_INFO(78, COMMON_PIN, 0, 0, 0),
+ UMS512_EXT_RST_B = SPRD_PIN_INFO(79, COMMON_PIN, 0, 0, 0),
+ UMS512_ADI_SCLK = SPRD_PIN_INFO(80, COMMON_PIN, 0, 0, 0),
+ UMS512_CLK_32K = SPRD_PIN_INFO(81, COMMON_PIN, 0, 0, 0),
+ UMS512_ANA_INT = SPRD_PIN_INFO(82, COMMON_PIN, 0, 0, 0),
+ UMS512_ADI_D = SPRD_PIN_INFO(83, COMMON_PIN, 0, 0, 0),
+ UMS512_AUD_SCLK = SPRD_PIN_INFO(84, COMMON_PIN, 0, 0, 0),
+ UMS512_DCDC_ARM0_EN = SPRD_PIN_INFO(85, COMMON_PIN, 0, 0, 0),
+ UMS512_AUD_ADD0 = SPRD_PIN_INFO(86, COMMON_PIN, 0, 0, 0),
+ UMS512_XTL_EN0 = SPRD_PIN_INFO(87, COMMON_PIN, 0, 0, 0),
+ UMS512_AUD_ADSYNC = SPRD_PIN_INFO(88, COMMON_PIN, 0, 0, 0),
+ UMS512_AUD_DAD0 = SPRD_PIN_INFO(89, COMMON_PIN, 0, 0, 0),
+ UMS512_XTL_EN1 = SPRD_PIN_INFO(90, COMMON_PIN, 0, 0, 0),
+ UMS512_AUD_DASYNC = SPRD_PIN_INFO(91, COMMON_PIN, 0, 0, 0),
+ UMS512_AUD_DAD1 = SPRD_PIN_INFO(92, COMMON_PIN, 0, 0, 0),
+ UMS512_CHIP_SLEEP = SPRD_PIN_INFO(93, COMMON_PIN, 0, 0, 0),
+ UMS512_SIMCLK2 = SPRD_PIN_INFO(94, COMMON_PIN, 0, 0, 0),
+ UMS512_SIMDA2 = SPRD_PIN_INFO(95, COMMON_PIN, 0, 0, 0),
+ UMS512_SIMRST2 = SPRD_PIN_INFO(96, COMMON_PIN, 0, 0, 0),
+ UMS512_SD0_CMD = SPRD_PIN_INFO(97, COMMON_PIN, 0, 0, 0),
+ UMS512_SD0_D0 = SPRD_PIN_INFO(98, COMMON_PIN, 0, 0, 0),
+ UMS512_SD0_D1 = SPRD_PIN_INFO(99, COMMON_PIN, 0, 0, 0),
+ UMS512_SD0_CLK = SPRD_PIN_INFO(100, COMMON_PIN, 0, 0, 0),
+ UMS512_SD0_D2 = SPRD_PIN_INFO(101, COMMON_PIN, 0, 0, 0),
+ UMS512_SD0_D3 = SPRD_PIN_INFO(102, COMMON_PIN, 0, 0, 0),
+ UMS512_SIMCLK0 = SPRD_PIN_INFO(103, COMMON_PIN, 0, 0, 0),
+ UMS512_SIMDA0 = SPRD_PIN_INFO(104, COMMON_PIN, 0, 0, 0),
+ UMS512_SIMRST0 = SPRD_PIN_INFO(105, COMMON_PIN, 0, 0, 0),
+ UMS512_SIMCLK1 = SPRD_PIN_INFO(106, COMMON_PIN, 0, 0, 0),
+ UMS512_SIMDA1 = SPRD_PIN_INFO(107, COMMON_PIN, 0, 0, 0),
+ UMS512_SIMRST1 = SPRD_PIN_INFO(108, COMMON_PIN, 0, 0, 0),
+ UMS512_SD2_CMD = SPRD_PIN_INFO(109, COMMON_PIN, 0, 0, 0),
+ UMS512_SD2_D0 = SPRD_PIN_INFO(110, COMMON_PIN, 0, 0, 0),
+ UMS512_SD2_D1 = SPRD_PIN_INFO(111, COMMON_PIN, 0, 0, 0),
+ UMS512_SD2_CLK = SPRD_PIN_INFO(112, COMMON_PIN, 0, 0, 0),
+ UMS512_SD2_D2 = SPRD_PIN_INFO(113, COMMON_PIN, 0, 0, 0),
+ UMS512_SD2_D3 = SPRD_PIN_INFO(114, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL0 = SPRD_PIN_INFO(115, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL1 = SPRD_PIN_INFO(116, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL2 = SPRD_PIN_INFO(117, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL3 = SPRD_PIN_INFO(118, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL4 = SPRD_PIN_INFO(119, COMMON_PIN, 0, 0, 0),
+ UMS512_DNS_D0 = SPRD_PIN_INFO(120, COMMON_PIN, 0, 0, 0),
+ UMS512_DNS_D1 = SPRD_PIN_INFO(121, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS3DI = SPRD_PIN_INFO(122, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS3DO = SPRD_PIN_INFO(123, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS3CLK = SPRD_PIN_INFO(124, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS3LRCK = SPRD_PIN_INFO(125, COMMON_PIN, 0, 0, 0),
+ UMS512_GPIO116 = SPRD_PIN_INFO(126, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL5 = SPRD_PIN_INFO(127, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL6 = SPRD_PIN_INFO(128, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL7 = SPRD_PIN_INFO(129, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL8 = SPRD_PIN_INFO(130, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL9 = SPRD_PIN_INFO(131, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL10 = SPRD_PIN_INFO(132, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL11 = SPRD_PIN_INFO(133, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL12 = SPRD_PIN_INFO(134, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL13 = SPRD_PIN_INFO(135, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL14 = SPRD_PIN_INFO(136, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL15 = SPRD_PIN_INFO(137, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL16 = SPRD_PIN_INFO(138, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL17 = SPRD_PIN_INFO(139, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL18 = SPRD_PIN_INFO(140, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL19 = SPRD_PIN_INFO(141, COMMON_PIN, 0, 0, 0),
+ UMS512_RFSCK0 = SPRD_PIN_INFO(142, COMMON_PIN, 0, 0, 0),
+ UMS512_RFSDA0 = SPRD_PIN_INFO(143, COMMON_PIN, 0, 0, 0),
+ UMS512_RFSEN0 = SPRD_PIN_INFO(144, COMMON_PIN, 0, 0, 0),
+ UMS512_RFSCK1 = SPRD_PIN_INFO(145, COMMON_PIN, 0, 0, 0),
+ UMS512_RFSDA1 = SPRD_PIN_INFO(146, COMMON_PIN, 0, 0, 0),
+ UMS512_RFSEN1 = SPRD_PIN_INFO(147, COMMON_PIN, 0, 0, 0),
+ UMS512_RFFE0_SCK = SPRD_PIN_INFO(148, COMMON_PIN, 0, 0, 0),
+ UMS512_RFFE0_SDA = SPRD_PIN_INFO(149, COMMON_PIN, 0, 0, 0),
+ UMS512_RFFE1_SCK = SPRD_PIN_INFO(150, COMMON_PIN, 0, 0, 0),
+ UMS512_RFFE1_SDA = SPRD_PIN_INFO(151, COMMON_PIN, 0, 0, 0),
+ UMS512_U1TXD = SPRD_PIN_INFO(152, COMMON_PIN, 0, 0, 0),
+ UMS512_U1RXD = SPRD_PIN_INFO(153, COMMON_PIN, 0, 0, 0),
+ UMS512_SCL6 = SPRD_PIN_INFO(154, COMMON_PIN, 0, 0, 0),
+ UMS512_SDA6 = SPRD_PIN_INFO(155, COMMON_PIN, 0, 0, 0),
+ UMS512_MTCK_ARM = SPRD_PIN_INFO(156, COMMON_PIN, 0, 0, 0),
+ UMS512_MTMS_ARM = SPRD_PIN_INFO(157, COMMON_PIN, 0, 0, 0),
+ UMS512_PWMC = SPRD_PIN_INFO(158, COMMON_PIN, 0, 0, 0),
+ UMS512_KEYOUT0 = SPRD_PIN_INFO(159, COMMON_PIN, 0, 0, 0),
+ UMS512_KEYOUT1 = SPRD_PIN_INFO(160, COMMON_PIN, 0, 0, 0),
+ UMS512_KEYOUT2 = SPRD_PIN_INFO(161, COMMON_PIN, 0, 0, 0),
+ UMS512_KEYIN0 = SPRD_PIN_INFO(162, COMMON_PIN, 0, 0, 0),
+ UMS512_KEYIN1 = SPRD_PIN_INFO(163, COMMON_PIN, 0, 0, 0),
+ UMS512_KEYIN2 = SPRD_PIN_INFO(164, COMMON_PIN, 0, 0, 0),
+ UMS512_SCL0 = SPRD_PIN_INFO(165, COMMON_PIN, 0, 0, 0),
+ UMS512_SDA0 = SPRD_PIN_INFO(166, COMMON_PIN, 0, 0, 0),
+ UMS512_SDA1 = SPRD_PIN_INFO(167, COMMON_PIN, 0, 0, 0),
+ UMS512_SCL1 = SPRD_PIN_INFO(168, COMMON_PIN, 0, 0, 0),
+ UMS512_CMMCLK0 = SPRD_PIN_INFO(169, COMMON_PIN, 0, 0, 0),
+ UMS512_CMMCLK1 = SPRD_PIN_INFO(170, COMMON_PIN, 0, 0, 0),
+ UMS512_CMRST0 = SPRD_PIN_INFO(171, COMMON_PIN, 0, 0, 0),
+ UMS512_CMRST1 = SPRD_PIN_INFO(172, COMMON_PIN, 0, 0, 0),
+ UMS512_CMPD0 = SPRD_PIN_INFO(173, COMMON_PIN, 0, 0, 0),
+ UMS512_CMPD1 = SPRD_PIN_INFO(174, COMMON_PIN, 0, 0, 0),
+ UMS512_CMMCLK2 = SPRD_PIN_INFO(175, COMMON_PIN, 0, 0, 0),
+ UMS512_CMPD2 = SPRD_PIN_INFO(176, COMMON_PIN, 0, 0, 0),
+ UMS512_CMRST2 = SPRD_PIN_INFO(177, COMMON_PIN, 0, 0, 0),
+ UMS512_GPIO84 = SPRD_PIN_INFO(178, COMMON_PIN, 0, 0, 0),
+ UMS512_GPIO85 = SPRD_PIN_INFO(179, COMMON_PIN, 0, 0, 0),
+ UMS512_GPIO86 = SPRD_PIN_INFO(180, COMMON_PIN, 0, 0, 0),
+ UMS512_GPIO87 = SPRD_PIN_INFO(181, COMMON_PIN, 0, 0, 0),
+ UMS512_GPIO88 = SPRD_PIN_INFO(182, COMMON_PIN, 0, 0, 0),
+ UMS512_SPI0_CSN = SPRD_PIN_INFO(183, COMMON_PIN, 0, 0, 0),
+ UMS512_SPI0_DO = SPRD_PIN_INFO(184, COMMON_PIN, 0, 0, 0),
+ UMS512_SPI0_DI = SPRD_PIN_INFO(185, COMMON_PIN, 0, 0, 0),
+ UMS512_SPI0_CLK = SPRD_PIN_INFO(186, COMMON_PIN, 0, 0, 0),
+ UMS512_EXTINT9 = SPRD_PIN_INFO(187, COMMON_PIN, 0, 0, 0),
+ UMS512_EXTINT10 = SPRD_PIN_INFO(188, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS1DI = SPRD_PIN_INFO(189, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS1DO = SPRD_PIN_INFO(190, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS1CLK = SPRD_PIN_INFO(191, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS1LRCK = SPRD_PIN_INFO(192, COMMON_PIN, 0, 0, 0),
+ UMS512_SCL2 = SPRD_PIN_INFO(193, COMMON_PIN, 0, 0, 0),
+ UMS512_SDA2 = SPRD_PIN_INFO(194, COMMON_PIN, 0, 0, 0),
+ UMS512_MEMS_MIC_CLK0 = SPRD_PIN_INFO(195, COMMON_PIN, 0, 0, 0),
+ UMS512_MEMS_MIC_DATA0 = SPRD_PIN_INFO(196, COMMON_PIN, 0, 0, 0),
+ UMS512_MEMS_MIC_CLK1 = SPRD_PIN_INFO(197, COMMON_PIN, 0, 0, 0),
+ UMS512_MEMS_MIC_DATA1 = SPRD_PIN_INFO(198, COMMON_PIN, 0, 0, 0),
+ UMS512_SPI2_CSN = SPRD_PIN_INFO(199, COMMON_PIN, 0, 0, 0),
+ UMS512_SPI2_DO = SPRD_PIN_INFO(200, COMMON_PIN, 0, 0, 0),
+ UMS512_SPI2_DI = SPRD_PIN_INFO(201, COMMON_PIN, 0, 0, 0),
+ UMS512_SPI2_CLK = SPRD_PIN_INFO(202, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS0DI = SPRD_PIN_INFO(203, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS0DO = SPRD_PIN_INFO(204, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS0CLK = SPRD_PIN_INFO(205, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS0LRCK = SPRD_PIN_INFO(206, COMMON_PIN, 0, 0, 0),
+ UMS512_U5TXD = SPRD_PIN_INFO(207, COMMON_PIN, 0, 0, 0),
+ UMS512_U5RXD = SPRD_PIN_INFO(208, COMMON_PIN, 0, 0, 0),
+ UMS512_CLK_AUX0 = SPRD_PIN_INFO(209, COMMON_PIN, 0, 0, 0),
+ UMS512_U0TXD = SPRD_PIN_INFO(210, COMMON_PIN, 0, 0, 0),
+ UMS512_U0RXD = SPRD_PIN_INFO(211, COMMON_PIN, 0, 0, 0),
+ UMS512_U0CTS = SPRD_PIN_INFO(212, COMMON_PIN, 0, 0, 0),
+ UMS512_U0RTS = SPRD_PIN_INFO(213, COMMON_PIN, 0, 0, 0),
+ UMS512_U4TXD = SPRD_PIN_INFO(214, COMMON_PIN, 0, 0, 0),
+ UMS512_U4RXD = SPRD_PIN_INFO(215, COMMON_PIN, 0, 0, 0),
+ UMS512_U4CTS = SPRD_PIN_INFO(216, COMMON_PIN, 0, 0, 0),
+ UMS512_U4RTS = SPRD_PIN_INFO(217, COMMON_PIN, 0, 0, 0),
+ UMS512_SD1_CMD = SPRD_PIN_INFO(218, COMMON_PIN, 0, 0, 0),
+ UMS512_SD1_D0 = SPRD_PIN_INFO(219, COMMON_PIN, 0, 0, 0),
+ UMS512_SD1_D1 = SPRD_PIN_INFO(220, COMMON_PIN, 0, 0, 0),
+ UMS512_SD1_CLK = SPRD_PIN_INFO(221, COMMON_PIN, 0, 0, 0),
+ UMS512_SD1_D2 = SPRD_PIN_INFO(222, COMMON_PIN, 0, 0, 0),
+ UMS512_SD1_D3 = SPRD_PIN_INFO(223, COMMON_PIN, 0, 0, 0),
+ UMS512_EXTINT0 = SPRD_PIN_INFO(224, COMMON_PIN, 0, 0, 0),
+ UMS512_EXTINT1 = SPRD_PIN_INFO(225, COMMON_PIN, 0, 0, 0),
+ UMS512_SDA3 = SPRD_PIN_INFO(226, COMMON_PIN, 0, 0, 0),
+ UMS512_SCL3 = SPRD_PIN_INFO(227, COMMON_PIN, 0, 0, 0),
+
+ /* MSIC pin registers definitions */
+ UMS512_EMMC_RST_MISC = SPRD_PIN_INFO(228, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_CMD_MISC = SPRD_PIN_INFO(229, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_D0_MISC = SPRD_PIN_INFO(230, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_D3_MISC = SPRD_PIN_INFO(231, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_D2_MISC = SPRD_PIN_INFO(232, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_D5_MISC = SPRD_PIN_INFO(233, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_CLK_MISC = SPRD_PIN_INFO(234, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_DS_MISC = SPRD_PIN_INFO(235, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_D1_MISC = SPRD_PIN_INFO(236, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_D4_MISC = SPRD_PIN_INFO(237, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_D6_MISC = SPRD_PIN_INFO(238, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_D7_MISC = SPRD_PIN_INFO(239, MISC_PIN, 0, 0, 0),
+ UMS512_LCM_RSTN_MISC = SPRD_PIN_INFO(240, MISC_PIN, 0, 0, 0),
+ UMS512_DSI_TE_MISC = SPRD_PIN_INFO(241, MISC_PIN, 0, 0, 0),
+ UMS512_DCDC_ARM1_EN_MISC = SPRD_PIN_INFO(242, MISC_PIN, 0, 0, 0),
+ UMS512_PTEST_MISC = SPRD_PIN_INFO(243, MISC_PIN, 0, 0, 0),
+ UMS512_EXT_RST_B_MISC = SPRD_PIN_INFO(244, MISC_PIN, 0, 0, 0),
+ UMS512_ADI_SCLK_MISC = SPRD_PIN_INFO(245, MISC_PIN, 0, 0, 0),
+ UMS512_CLK_32K_MISC = SPRD_PIN_INFO(246, MISC_PIN, 0, 0, 0),
+ UMS512_ANA_INT_MISC = SPRD_PIN_INFO(247, MISC_PIN, 0, 0, 0),
+ UMS512_ADI_D_MISC = SPRD_PIN_INFO(248, MISC_PIN, 0, 0, 0),
+ UMS512_AUD_SCLK_MISC = SPRD_PIN_INFO(249, MISC_PIN, 0, 0, 0),
+ UMS512_DCDC_ARM0_EN_MISC = SPRD_PIN_INFO(250, MISC_PIN, 0, 0, 0),
+ UMS512_AUD_ADD0_MISC = SPRD_PIN_INFO(251, MISC_PIN, 0, 0, 0),
+ UMS512_XTL_EN0_MISC = SPRD_PIN_INFO(252, MISC_PIN, 0, 0, 0),
+ UMS512_AUD_ADSYNC_MISC = SPRD_PIN_INFO(253, MISC_PIN, 0, 0, 0),
+ UMS512_AUD_DAD0_MISC = SPRD_PIN_INFO(254, MISC_PIN, 0, 0, 0),
+ UMS512_XTL_EN1_MISC = SPRD_PIN_INFO(255, MISC_PIN, 0, 0, 0),
+ UMS512_AUD_DASYNC_MISC = SPRD_PIN_INFO(256, MISC_PIN, 0, 0, 0),
+ UMS512_AUD_DAD1_MISC = SPRD_PIN_INFO(257, MISC_PIN, 0, 0, 0),
+ UMS512_CHIP_SLEEP_MISC = SPRD_PIN_INFO(258, MISC_PIN, 0, 0, 0),
+ UMS512_SIMCLK2_MISC = SPRD_PIN_INFO(259, MISC_PIN, 0, 0, 0),
+ UMS512_SIMDA2_MISC = SPRD_PIN_INFO(260, MISC_PIN, 0, 0, 0),
+ UMS512_SIMRST2_MISC = SPRD_PIN_INFO(261, MISC_PIN, 0, 0, 0),
+ UMS512_SD0_CMD_MISC = SPRD_PIN_INFO(262, MISC_PIN, 0, 0, 0),
+ UMS512_SD0_D0_MISC = SPRD_PIN_INFO(263, MISC_PIN, 0, 0, 0),
+ UMS512_SD0_D1_MISC = SPRD_PIN_INFO(264, MISC_PIN, 0, 0, 0),
+ UMS512_SD0_CLK_MISC = SPRD_PIN_INFO(265, MISC_PIN, 0, 0, 0),
+ UMS512_SD0_D2_MISC = SPRD_PIN_INFO(266, MISC_PIN, 0, 0, 0),
+ UMS512_SD0_D3_MISC = SPRD_PIN_INFO(267, MISC_PIN, 0, 0, 0),
+ UMS512_SIMCLK0_MISC = SPRD_PIN_INFO(268, MISC_PIN, 0, 0, 0),
+ UMS512_SIMDA0_MISC = SPRD_PIN_INFO(269, MISC_PIN, 0, 0, 0),
+ UMS512_SIMRST0_MISC = SPRD_PIN_INFO(270, MISC_PIN, 0, 0, 0),
+ UMS512_SIMCLK1_MISC = SPRD_PIN_INFO(271, MISC_PIN, 0, 0, 0),
+ UMS512_SIMDA1_MISC = SPRD_PIN_INFO(272, MISC_PIN, 0, 0, 0),
+ UMS512_SIMRST1_MISC = SPRD_PIN_INFO(273, MISC_PIN, 0, 0, 0),
+ UMS512_SD2_CMD_MISC = SPRD_PIN_INFO(274, MISC_PIN, 0, 0, 0),
+ UMS512_SD2_D0_MISC = SPRD_PIN_INFO(275, MISC_PIN, 0, 0, 0),
+ UMS512_SD2_D1_MISC = SPRD_PIN_INFO(276, MISC_PIN, 0, 0, 0),
+ UMS512_SD2_CLK_MISC = SPRD_PIN_INFO(277, MISC_PIN, 0, 0, 0),
+ UMS512_SD2_D2_MISC = SPRD_PIN_INFO(278, MISC_PIN, 0, 0, 0),
+ UMS512_SD2_D3_MISC = SPRD_PIN_INFO(279, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL0_MISC = SPRD_PIN_INFO(280, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL1_MISC = SPRD_PIN_INFO(281, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL2_MISC = SPRD_PIN_INFO(282, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL3_MISC = SPRD_PIN_INFO(283, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL4_MISC = SPRD_PIN_INFO(284, MISC_PIN, 0, 0, 0),
+ UMS512_DNS_D0_MISC = SPRD_PIN_INFO(285, MISC_PIN, 0, 0, 0),
+ UMS512_DNS_D1_MISC = SPRD_PIN_INFO(286, MISC_PIN, 0, 0, 0),
+ UMS512_IIS3DI_MISC = SPRD_PIN_INFO(287, MISC_PIN, 0, 0, 0),
+ UMS512_IIS3DO_MISC = SPRD_PIN_INFO(288, MISC_PIN, 0, 0, 0),
+ UMS512_IIS3CLK_MISC = SPRD_PIN_INFO(289, MISC_PIN, 0, 0, 0),
+ UMS512_IIS3LRCK_MISC = SPRD_PIN_INFO(290, MISC_PIN, 0, 0, 0),
+ UMS512_GPIO116_MISC = SPRD_PIN_INFO(291, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL5_MISC = SPRD_PIN_INFO(292, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL6_MISC = SPRD_PIN_INFO(293, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL7_MISC = SPRD_PIN_INFO(294, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL8_MISC = SPRD_PIN_INFO(295, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL9_MISC = SPRD_PIN_INFO(296, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL10_MISC = SPRD_PIN_INFO(297, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL11_MISC = SPRD_PIN_INFO(298, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL12_MISC = SPRD_PIN_INFO(299, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL13_MISC = SPRD_PIN_INFO(300, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL14_MISC = SPRD_PIN_INFO(301, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL15_MISC = SPRD_PIN_INFO(302, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL16_MISC = SPRD_PIN_INFO(303, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL17_MISC = SPRD_PIN_INFO(304, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL18_MISC = SPRD_PIN_INFO(305, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL19_MISC = SPRD_PIN_INFO(306, MISC_PIN, 0, 0, 0),
+ UMS512_RFSCK0_MISC = SPRD_PIN_INFO(307, MISC_PIN, 0, 0, 0),
+ UMS512_RFSDA0_MISC = SPRD_PIN_INFO(308, MISC_PIN, 0, 0, 0),
+ UMS512_RFSEN0_MISC = SPRD_PIN_INFO(309, MISC_PIN, 0, 0, 0),
+ UMS512_RFSCK1_MISC = SPRD_PIN_INFO(310, MISC_PIN, 0, 0, 0),
+ UMS512_RFSDA1_MISC = SPRD_PIN_INFO(311, MISC_PIN, 0, 0, 0),
+ UMS512_RFSEN1_MISC = SPRD_PIN_INFO(312, MISC_PIN, 0, 0, 0),
+ UMS512_RFFE0_SCK_MISC = SPRD_PIN_INFO(313, MISC_PIN, 0, 0, 0),
+ UMS512_RFFE0_SDA_MISC = SPRD_PIN_INFO(314, MISC_PIN, 0, 0, 0),
+ UMS512_RFFE1_SCK_MISC = SPRD_PIN_INFO(315, MISC_PIN, 0, 0, 0),
+ UMS512_RFFE1_SDA_MISC = SPRD_PIN_INFO(316, MISC_PIN, 0, 0, 0),
+ UMS512_U1TXD_MISC = SPRD_PIN_INFO(317, MISC_PIN, 0, 0, 0),
+ UMS512_U1RXD_MISC = SPRD_PIN_INFO(318, MISC_PIN, 0, 0, 0),
+ UMS512_SCL6_MISC = SPRD_PIN_INFO(319, MISC_PIN, 0, 0, 0),
+ UMS512_SDA6_MISC = SPRD_PIN_INFO(320, MISC_PIN, 0, 0, 0),
+ UMS512_MTCK_ARM_MISC = SPRD_PIN_INFO(321, MISC_PIN, 0, 0, 0),
+ UMS512_MTMS_ARM_MISC = SPRD_PIN_INFO(322, MISC_PIN, 0, 0, 0),
+ UMS512_PWMC_MISC = SPRD_PIN_INFO(323, MISC_PIN, 0, 0, 0),
+ UMS512_KEYOUT0_MISC = SPRD_PIN_INFO(324, MISC_PIN, 0, 0, 0),
+ UMS512_KEYOUT1_MISC = SPRD_PIN_INFO(325, MISC_PIN, 0, 0, 0),
+ UMS512_KEYOUT2_MISC = SPRD_PIN_INFO(326, MISC_PIN, 0, 0, 0),
+ UMS512_KEYIN0_MISC = SPRD_PIN_INFO(327, MISC_PIN, 0, 0, 0),
+ UMS512_KEYIN1_MISC = SPRD_PIN_INFO(328, MISC_PIN, 0, 0, 0),
+ UMS512_KEYIN2_MISC = SPRD_PIN_INFO(329, MISC_PIN, 0, 0, 0),
+ UMS512_SCL0_MISC = SPRD_PIN_INFO(330, MISC_PIN, 0, 0, 0),
+ UMS512_SDA0_MISC = SPRD_PIN_INFO(331, MISC_PIN, 0, 0, 0),
+ UMS512_SDA1_MISC = SPRD_PIN_INFO(332, MISC_PIN, 0, 0, 0),
+ UMS512_SCL1_MISC = SPRD_PIN_INFO(333, MISC_PIN, 0, 0, 0),
+ UMS512_CMMCLK0_MISC = SPRD_PIN_INFO(334, MISC_PIN, 0, 0, 0),
+ UMS512_CMMCLK1_MISC = SPRD_PIN_INFO(335, MISC_PIN, 0, 0, 0),
+ UMS512_CMRST0_MISC = SPRD_PIN_INFO(336, MISC_PIN, 0, 0, 0),
+ UMS512_CMRST1_MISC = SPRD_PIN_INFO(337, MISC_PIN, 0, 0, 0),
+ UMS512_CMPD0_MISC = SPRD_PIN_INFO(338, MISC_PIN, 0, 0, 0),
+ UMS512_CMPD1_MISC = SPRD_PIN_INFO(339, MISC_PIN, 0, 0, 0),
+ UMS512_CMMCLK2_MISC = SPRD_PIN_INFO(340, MISC_PIN, 0, 0, 0),
+ UMS512_CMPD2_MISC = SPRD_PIN_INFO(341, MISC_PIN, 0, 0, 0),
+ UMS512_CMRST2_MISC = SPRD_PIN_INFO(342, MISC_PIN, 0, 0, 0),
+ UMS512_GPIO84_MISC = SPRD_PIN_INFO(343, MISC_PIN, 0, 0, 0),
+ UMS512_GPIO85_MISC = SPRD_PIN_INFO(344, MISC_PIN, 0, 0, 0),
+ UMS512_GPIO86_MISC = SPRD_PIN_INFO(345, MISC_PIN, 0, 0, 0),
+ UMS512_GPIO87_MISC = SPRD_PIN_INFO(346, MISC_PIN, 0, 0, 0),
+ UMS512_GPIO88_MISC = SPRD_PIN_INFO(347, MISC_PIN, 0, 0, 0),
+ UMS512_SPI0_CSN_MISC = SPRD_PIN_INFO(348, MISC_PIN, 0, 0, 0),
+ UMS512_SPI0_DO_MISC = SPRD_PIN_INFO(349, MISC_PIN, 0, 0, 0),
+ UMS512_SPI0_DI_MISC = SPRD_PIN_INFO(350, MISC_PIN, 0, 0, 0),
+ UMS512_SPI0_CLK_MISC = SPRD_PIN_INFO(351, MISC_PIN, 0, 0, 0),
+ UMS512_EXTINT9_MISC = SPRD_PIN_INFO(352, MISC_PIN, 0, 0, 0),
+ UMS512_EXTINT10_MISC = SPRD_PIN_INFO(353, MISC_PIN, 0, 0, 0),
+ UMS512_IIS1DI_MISC = SPRD_PIN_INFO(354, MISC_PIN, 0, 0, 0),
+ UMS512_IIS1DO_MISC = SPRD_PIN_INFO(355, MISC_PIN, 0, 0, 0),
+ UMS512_IIS1CLK_MISC = SPRD_PIN_INFO(356, MISC_PIN, 0, 0, 0),
+ UMS512_IIS1LRCK_MISC = SPRD_PIN_INFO(357, MISC_PIN, 0, 0, 0),
+ UMS512_SCL2_MISC = SPRD_PIN_INFO(358, MISC_PIN, 0, 0, 0),
+ UMS512_SDA2_MISC = SPRD_PIN_INFO(359, MISC_PIN, 0, 0, 0),
+ UMS512_MEMS_MIC_CLK0_MISC = SPRD_PIN_INFO(360, MISC_PIN, 0, 0, 0),
+ UMS512_MEMS_MIC_DATA0_MISC = SPRD_PIN_INFO(361, MISC_PIN, 0, 0, 0),
+ UMS512_MEMS_MIC_CLK1_MISC = SPRD_PIN_INFO(362, MISC_PIN, 0, 0, 0),
+ UMS512_MEMS_MIC_DATA1_MISC = SPRD_PIN_INFO(363, MISC_PIN, 0, 0, 0),
+ UMS512_SPI2_CSN_MISC = SPRD_PIN_INFO(364, MISC_PIN, 0, 0, 0),
+ UMS512_SPI2_DO_MISC = SPRD_PIN_INFO(365, MISC_PIN, 0, 0, 0),
+ UMS512_SPI2_DI_MISC = SPRD_PIN_INFO(366, MISC_PIN, 0, 0, 0),
+ UMS512_SPI2_CLK_MISC = SPRD_PIN_INFO(367, MISC_PIN, 0, 0, 0),
+ UMS512_IIS0DI_MISC = SPRD_PIN_INFO(368, MISC_PIN, 0, 0, 0),
+ UMS512_IIS0DO_MISC = SPRD_PIN_INFO(369, MISC_PIN, 0, 0, 0),
+ UMS512_IIS0CLK_MISC = SPRD_PIN_INFO(370, MISC_PIN, 0, 0, 0),
+ UMS512_IIS0LRCK_MISC = SPRD_PIN_INFO(371, MISC_PIN, 0, 0, 0),
+ UMS512_U5TXD_MISC = SPRD_PIN_INFO(372, MISC_PIN, 0, 0, 0),
+ UMS512_U5RXD_MISC = SPRD_PIN_INFO(373, MISC_PIN, 0, 0, 0),
+ UMS512_CLK_AUX0_MISC = SPRD_PIN_INFO(374, MISC_PIN, 0, 0, 0),
+ UMS512_U0TXD_MISC = SPRD_PIN_INFO(375, MISC_PIN, 0, 0, 0),
+ UMS512_U0RXD_MISC = SPRD_PIN_INFO(376, MISC_PIN, 0, 0, 0),
+ UMS512_U0CTS_MISC = SPRD_PIN_INFO(377, MISC_PIN, 0, 0, 0),
+ UMS512_U0RTS_MISC = SPRD_PIN_INFO(378, MISC_PIN, 0, 0, 0),
+ UMS512_U4TXD_MISC = SPRD_PIN_INFO(379, MISC_PIN, 0, 0, 0),
+ UMS512_U4RXD_MISC = SPRD_PIN_INFO(380, MISC_PIN, 0, 0, 0),
+ UMS512_U4CTS_MISC = SPRD_PIN_INFO(381, MISC_PIN, 0, 0, 0),
+ UMS512_U4RTS_MISC = SPRD_PIN_INFO(382, MISC_PIN, 0, 0, 0),
+ UMS512_SD1_CMD_MISC = SPRD_PIN_INFO(383, MISC_PIN, 0, 0, 0),
+ UMS512_SD1_D0_MISC = SPRD_PIN_INFO(384, MISC_PIN, 0, 0, 0),
+ UMS512_SD1_D1_MISC = SPRD_PIN_INFO(385, MISC_PIN, 0, 0, 0),
+ UMS512_SD1_CLK_MISC = SPRD_PIN_INFO(386, MISC_PIN, 0, 0, 0),
+ UMS512_SD1_D2_MISC = SPRD_PIN_INFO(387, MISC_PIN, 0, 0, 0),
+ UMS512_SD1_D3_MISC = SPRD_PIN_INFO(388, MISC_PIN, 0, 0, 0),
+ UMS512_EXTINT0_MISC = SPRD_PIN_INFO(389, MISC_PIN, 0, 0, 0),
+ UMS512_EXTINT1_MISC = SPRD_PIN_INFO(390, MISC_PIN, 0, 0, 0),
+ UMS512_SDA3_MISC = SPRD_PIN_INFO(391, MISC_PIN, 0, 0, 0),
+ UMS512_SCL3_MISC = SPRD_PIN_INFO(392, MISC_PIN, 0, 0, 0),
+};
+
+static struct sprd_pins_info sprd_ums512_pins_info[] = {
+ SPRD_PINCTRL_PIN(UMS512_UART_INF6_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF5_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF4_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF3_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF2_INF3_LOOP),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF2_INF4_LOOP),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF1_INF4_LOOP),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF1_INF3_LOOP),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS512_UART_INF9_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF8_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF7_INF8_LOOP),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF7_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS512_IIS_INF4_INF3_LOOP),
+ SPRD_PINCTRL_PIN(UMS512_IIS_INF4_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIS_INF3_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIS_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIS_INF1_INF2_LOOP),
+ SPRD_PINCTRL_PIN(UMS512_IIS_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIS_INF0_INF2_LOOP),
+ SPRD_PINCTRL_PIN(UMS512_IIS_INF0_INF1_LOOP),
+ SPRD_PINCTRL_PIN(UMS512_IIS_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS512_SIM_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_SIM_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_SIM_INFO_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS512_SPI_INF3_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_SPI_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_SPI_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_SPI_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS512_IIC_INF7_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIC_INF6_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIC_INF5_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIC_INF4_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIC_INF3_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIC_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIC_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIC_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS512_PIN_CTRL_REG0),
+
+ SPRD_PINCTRL_PIN(UMS512_PIN_CTRL_REG1),
+
+ SPRD_PINCTRL_PIN(UMS512_UART_USB_PHY_SEL),
+ SPRD_PINCTRL_PIN(UMS512_USB_PHY_DM_OE),
+ SPRD_PINCTRL_PIN(UMS512_USB_PHY_DP_OE),
+
+ SPRD_PINCTRL_PIN(UMS512_SP_EIC_DPAD3),
+ SPRD_PINCTRL_PIN(UMS512_SP_EIC_DPAD2),
+ SPRD_PINCTRL_PIN(UMS512_SP_EIC_DPAD1),
+ SPRD_PINCTRL_PIN(UMS512_SP_EIC_DPAD0),
+
+ SPRD_PINCTRL_PIN(UMS512_SP_EIC_DPAD7),
+ SPRD_PINCTRL_PIN(UMS512_SP_EIC_DPAD6),
+ SPRD_PINCTRL_PIN(UMS512_SP_EIC_DPAD5),
+ SPRD_PINCTRL_PIN(UMS512_SP_EIC_DPAD4),
+
+ SPRD_PINCTRL_PIN(UMS512_VBC_IIS_INF_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_CARD_DET_SEL),
+ SPRD_PINCTRL_PIN(UMS512_SIM0_DET_SEL),
+ SPRD_PINCTRL_PIN(UMS512_AP_SIM0_BD_EB),
+ SPRD_PINCTRL_PIN(UMS512_AP_EMMC_BD_EB),
+ SPRD_PINCTRL_PIN(UMS512_AP_SDIO2_BD_EB),
+ SPRD_PINCTRL_PIN(UMS512_AP_SDIO1_BD_EB),
+ SPRD_PINCTRL_PIN(UMS512_AP_SDIO0_BD_EB),
+ SPRD_PINCTRL_PIN(UMS512_PUBCP_SDIO_BD_EB),
+ SPRD_PINCTRL_PIN(UMS512_PUBCP_SIM1_BD_EB),
+ SPRD_PINCTRL_PIN(UMS512_PUBCP_SIM0_BD_EB),
+
+ SPRD_PINCTRL_PIN(UMS512_EMMC_RST),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_CMD),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D0),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D3),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D2),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D5),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_CLK),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_DS),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D1),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D4),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D6),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D7),
+ SPRD_PINCTRL_PIN(UMS512_LCM_RSTN),
+ SPRD_PINCTRL_PIN(UMS512_DSI_TE),
+ SPRD_PINCTRL_PIN(UMS512_DCDC_ARM1_EN),
+ SPRD_PINCTRL_PIN(UMS512_PTEST),
+ SPRD_PINCTRL_PIN(UMS512_EXT_RST_B),
+ SPRD_PINCTRL_PIN(UMS512_ADI_SCLK),
+ SPRD_PINCTRL_PIN(UMS512_CLK_32K),
+ SPRD_PINCTRL_PIN(UMS512_ANA_INT),
+ SPRD_PINCTRL_PIN(UMS512_ADI_D),
+ SPRD_PINCTRL_PIN(UMS512_AUD_SCLK),
+ SPRD_PINCTRL_PIN(UMS512_DCDC_ARM0_EN),
+ SPRD_PINCTRL_PIN(UMS512_AUD_ADD0),
+ SPRD_PINCTRL_PIN(UMS512_XTL_EN0),
+ SPRD_PINCTRL_PIN(UMS512_AUD_ADSYNC),
+ SPRD_PINCTRL_PIN(UMS512_AUD_DAD0),
+ SPRD_PINCTRL_PIN(UMS512_XTL_EN1),
+ SPRD_PINCTRL_PIN(UMS512_AUD_DASYNC),
+ SPRD_PINCTRL_PIN(UMS512_AUD_DAD1),
+ SPRD_PINCTRL_PIN(UMS512_CHIP_SLEEP),
+ SPRD_PINCTRL_PIN(UMS512_SIMCLK2),
+ SPRD_PINCTRL_PIN(UMS512_SIMDA2),
+ SPRD_PINCTRL_PIN(UMS512_SIMRST2),
+ SPRD_PINCTRL_PIN(UMS512_SD0_CMD),
+ SPRD_PINCTRL_PIN(UMS512_SD0_D0),
+ SPRD_PINCTRL_PIN(UMS512_SD0_D1),
+ SPRD_PINCTRL_PIN(UMS512_SD0_CLK),
+ SPRD_PINCTRL_PIN(UMS512_SD0_D2),
+ SPRD_PINCTRL_PIN(UMS512_SD0_D3),
+ SPRD_PINCTRL_PIN(UMS512_SIMCLK0),
+ SPRD_PINCTRL_PIN(UMS512_SIMDA0),
+ SPRD_PINCTRL_PIN(UMS512_SIMRST0),
+ SPRD_PINCTRL_PIN(UMS512_SIMCLK1),
+ SPRD_PINCTRL_PIN(UMS512_SIMDA1),
+ SPRD_PINCTRL_PIN(UMS512_SIMRST1),
+ SPRD_PINCTRL_PIN(UMS512_SD2_CMD),
+ SPRD_PINCTRL_PIN(UMS512_SD2_D0),
+ SPRD_PINCTRL_PIN(UMS512_SD2_D1),
+ SPRD_PINCTRL_PIN(UMS512_SD2_CLK),
+ SPRD_PINCTRL_PIN(UMS512_SD2_D2),
+ SPRD_PINCTRL_PIN(UMS512_SD2_D3),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL0),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL1),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL2),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL3),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL4),
+ SPRD_PINCTRL_PIN(UMS512_DNS_D0),
+ SPRD_PINCTRL_PIN(UMS512_DNS_D1),
+ SPRD_PINCTRL_PIN(UMS512_IIS3DI),
+ SPRD_PINCTRL_PIN(UMS512_IIS3DO),
+ SPRD_PINCTRL_PIN(UMS512_IIS3CLK),
+ SPRD_PINCTRL_PIN(UMS512_IIS3LRCK),
+ SPRD_PINCTRL_PIN(UMS512_GPIO116),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL5),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL6),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL7),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL8),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL9),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL10),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL11),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL12),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL13),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL14),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL15),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL16),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL17),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL18),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL19),
+ SPRD_PINCTRL_PIN(UMS512_RFSCK0),
+ SPRD_PINCTRL_PIN(UMS512_RFSDA0),
+ SPRD_PINCTRL_PIN(UMS512_RFSEN0),
+ SPRD_PINCTRL_PIN(UMS512_RFSCK1),
+ SPRD_PINCTRL_PIN(UMS512_RFSDA1),
+ SPRD_PINCTRL_PIN(UMS512_RFSEN1),
+ SPRD_PINCTRL_PIN(UMS512_RFFE0_SCK),
+ SPRD_PINCTRL_PIN(UMS512_RFFE0_SDA),
+ SPRD_PINCTRL_PIN(UMS512_RFFE1_SCK),
+ SPRD_PINCTRL_PIN(UMS512_RFFE1_SDA),
+ SPRD_PINCTRL_PIN(UMS512_U1TXD),
+ SPRD_PINCTRL_PIN(UMS512_U1RXD),
+ SPRD_PINCTRL_PIN(UMS512_SCL6),
+ SPRD_PINCTRL_PIN(UMS512_SDA6),
+ SPRD_PINCTRL_PIN(UMS512_MTCK_ARM),
+ SPRD_PINCTRL_PIN(UMS512_MTMS_ARM),
+ SPRD_PINCTRL_PIN(UMS512_PWMC),
+ SPRD_PINCTRL_PIN(UMS512_KEYOUT0),
+ SPRD_PINCTRL_PIN(UMS512_KEYOUT1),
+ SPRD_PINCTRL_PIN(UMS512_KEYOUT2),
+ SPRD_PINCTRL_PIN(UMS512_KEYIN0),
+ SPRD_PINCTRL_PIN(UMS512_KEYIN1),
+ SPRD_PINCTRL_PIN(UMS512_KEYIN2),
+ SPRD_PINCTRL_PIN(UMS512_SCL0),
+ SPRD_PINCTRL_PIN(UMS512_SDA0),
+ SPRD_PINCTRL_PIN(UMS512_SDA1),
+ SPRD_PINCTRL_PIN(UMS512_SCL1),
+ SPRD_PINCTRL_PIN(UMS512_CMMCLK0),
+ SPRD_PINCTRL_PIN(UMS512_CMMCLK1),
+ SPRD_PINCTRL_PIN(UMS512_CMRST0),
+ SPRD_PINCTRL_PIN(UMS512_CMRST1),
+ SPRD_PINCTRL_PIN(UMS512_CMPD0),
+ SPRD_PINCTRL_PIN(UMS512_CMPD1),
+ SPRD_PINCTRL_PIN(UMS512_CMMCLK2),
+ SPRD_PINCTRL_PIN(UMS512_CMPD2),
+ SPRD_PINCTRL_PIN(UMS512_CMRST2),
+ SPRD_PINCTRL_PIN(UMS512_GPIO84),
+ SPRD_PINCTRL_PIN(UMS512_GPIO85),
+ SPRD_PINCTRL_PIN(UMS512_GPIO86),
+ SPRD_PINCTRL_PIN(UMS512_GPIO87),
+ SPRD_PINCTRL_PIN(UMS512_GPIO88),
+ SPRD_PINCTRL_PIN(UMS512_SPI0_CSN),
+ SPRD_PINCTRL_PIN(UMS512_SPI0_DO),
+ SPRD_PINCTRL_PIN(UMS512_SPI0_DI),
+ SPRD_PINCTRL_PIN(UMS512_SPI0_CLK),
+ SPRD_PINCTRL_PIN(UMS512_EXTINT9),
+ SPRD_PINCTRL_PIN(UMS512_EXTINT10),
+ SPRD_PINCTRL_PIN(UMS512_IIS1DI),
+ SPRD_PINCTRL_PIN(UMS512_IIS1DO),
+ SPRD_PINCTRL_PIN(UMS512_IIS1CLK),
+ SPRD_PINCTRL_PIN(UMS512_IIS1LRCK),
+ SPRD_PINCTRL_PIN(UMS512_SCL2),
+ SPRD_PINCTRL_PIN(UMS512_SDA2),
+ SPRD_PINCTRL_PIN(UMS512_MEMS_MIC_CLK0),
+ SPRD_PINCTRL_PIN(UMS512_MEMS_MIC_DATA0),
+ SPRD_PINCTRL_PIN(UMS512_MEMS_MIC_CLK1),
+ SPRD_PINCTRL_PIN(UMS512_MEMS_MIC_DATA1),
+ SPRD_PINCTRL_PIN(UMS512_SPI2_CSN),
+ SPRD_PINCTRL_PIN(UMS512_SPI2_DO),
+ SPRD_PINCTRL_PIN(UMS512_SPI2_DI),
+ SPRD_PINCTRL_PIN(UMS512_SPI2_CLK),
+ SPRD_PINCTRL_PIN(UMS512_IIS0DI),
+ SPRD_PINCTRL_PIN(UMS512_IIS0DO),
+ SPRD_PINCTRL_PIN(UMS512_IIS0CLK),
+ SPRD_PINCTRL_PIN(UMS512_IIS0LRCK),
+ SPRD_PINCTRL_PIN(UMS512_U5TXD),
+ SPRD_PINCTRL_PIN(UMS512_U5RXD),
+ SPRD_PINCTRL_PIN(UMS512_CLK_AUX0),
+ SPRD_PINCTRL_PIN(UMS512_U0TXD),
+ SPRD_PINCTRL_PIN(UMS512_U0RXD),
+ SPRD_PINCTRL_PIN(UMS512_U0CTS),
+ SPRD_PINCTRL_PIN(UMS512_U0RTS),
+ SPRD_PINCTRL_PIN(UMS512_U4TXD),
+ SPRD_PINCTRL_PIN(UMS512_U4RXD),
+ SPRD_PINCTRL_PIN(UMS512_U4CTS),
+ SPRD_PINCTRL_PIN(UMS512_U4RTS),
+ SPRD_PINCTRL_PIN(UMS512_SD1_CMD),
+ SPRD_PINCTRL_PIN(UMS512_SD1_D0),
+ SPRD_PINCTRL_PIN(UMS512_SD1_D1),
+ SPRD_PINCTRL_PIN(UMS512_SD1_CLK),
+ SPRD_PINCTRL_PIN(UMS512_SD1_D2),
+ SPRD_PINCTRL_PIN(UMS512_SD1_D3),
+ SPRD_PINCTRL_PIN(UMS512_EXTINT0),
+ SPRD_PINCTRL_PIN(UMS512_EXTINT1),
+ SPRD_PINCTRL_PIN(UMS512_SDA3),
+ SPRD_PINCTRL_PIN(UMS512_SCL3),
+
+ SPRD_PINCTRL_PIN(UMS512_EMMC_RST_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_CMD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D3_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D5_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_DS_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D4_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D6_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D7_MISC),
+ SPRD_PINCTRL_PIN(UMS512_LCM_RSTN_MISC),
+ SPRD_PINCTRL_PIN(UMS512_DSI_TE_MISC),
+ SPRD_PINCTRL_PIN(UMS512_DCDC_ARM1_EN_MISC),
+ SPRD_PINCTRL_PIN(UMS512_PTEST_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EXT_RST_B_MISC),
+ SPRD_PINCTRL_PIN(UMS512_ADI_SCLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CLK_32K_MISC),
+ SPRD_PINCTRL_PIN(UMS512_ANA_INT_MISC),
+ SPRD_PINCTRL_PIN(UMS512_ADI_D_MISC),
+ SPRD_PINCTRL_PIN(UMS512_AUD_SCLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_DCDC_ARM0_EN_MISC),
+ SPRD_PINCTRL_PIN(UMS512_AUD_ADD0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_XTL_EN0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_AUD_ADSYNC_MISC),
+ SPRD_PINCTRL_PIN(UMS512_AUD_DAD0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_XTL_EN1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_AUD_DASYNC_MISC),
+ SPRD_PINCTRL_PIN(UMS512_AUD_DAD1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CHIP_SLEEP_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SIMCLK2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SIMDA2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SIMRST2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD0_CMD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD0_D0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD0_D1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD0_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD0_D2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD0_D3_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SIMCLK0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SIMDA0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SIMRST0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SIMCLK1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SIMDA1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SIMRST1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD2_CMD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD2_D0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD2_D1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD2_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD2_D2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD2_D3_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL3_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL4_MISC),
+ SPRD_PINCTRL_PIN(UMS512_DNS_D0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_DNS_D1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS3DI_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS3DO_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS3CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS3LRCK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_GPIO116_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL5_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL6_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL7_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL8_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL9_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL10_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL11_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL12_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL13_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL14_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL15_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL16_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL17_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL18_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL19_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFSCK0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFSDA0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFSEN0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFSCK1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFSDA1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFSEN1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFFE0_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFFE0_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFFE1_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFFE1_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U1TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U1RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SCL6_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SDA6_MISC),
+ SPRD_PINCTRL_PIN(UMS512_MTCK_ARM_MISC),
+ SPRD_PINCTRL_PIN(UMS512_MTMS_ARM_MISC),
+ SPRD_PINCTRL_PIN(UMS512_PWMC_MISC),
+ SPRD_PINCTRL_PIN(UMS512_KEYOUT0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_KEYOUT1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_KEYOUT2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_KEYIN0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_KEYIN1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_KEYIN2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SCL0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SDA0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SDA1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SCL1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CMMCLK0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CMMCLK1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CMRST0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CMRST1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CMPD0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CMPD1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CMMCLK2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CMPD2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CMRST2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_GPIO84_MISC),
+ SPRD_PINCTRL_PIN(UMS512_GPIO85_MISC),
+ SPRD_PINCTRL_PIN(UMS512_GPIO86_MISC),
+ SPRD_PINCTRL_PIN(UMS512_GPIO87_MISC),
+ SPRD_PINCTRL_PIN(UMS512_GPIO88_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SPI0_CSN_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SPI0_DO_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SPI0_DI_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SPI0_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EXTINT9_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EXTINT10_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS1DI_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS1DO_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS1CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS1LRCK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SCL2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SDA2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_MEMS_MIC_CLK0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_MEMS_MIC_DATA0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_MEMS_MIC_CLK1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_MEMS_MIC_DATA1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SPI2_CSN_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SPI2_DO_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SPI2_DI_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SPI2_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS0DI_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS0DO_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS0CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS0LRCK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U5TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U5RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CLK_AUX0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U0TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U0RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U0CTS_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U0RTS_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U4TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U4RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U4CTS_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U4RTS_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD1_CMD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD1_D0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD1_D1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD1_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD1_D2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD1_D3_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EXTINT0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EXTINT1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SDA3_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SCL3_MISC),
+};
+
+static const struct sprd_pinctrl_priv_data ums512_data = {
+ .common_offset = PINCTRL_REG_OFFSET,
+ .misc_offset = PINCTRL_REG_MISC_OFFSET,
+};
+
+static int sprd_pinctrl_probe(struct platform_device *pdev)
+{
+ return sprd_pinctrl_core_probe(pdev, sprd_ums512_pins_info,
+ ARRAY_SIZE(sprd_ums512_pins_info));
+}
+
+static const struct of_device_id sprd_pinctrl_of_match[] = {
+ { .compatible = "sprd,ums512-pinctrl", .data = &ums512_data},
+ { }
+};
+MODULE_DEVICE_TABLE(of, sprd_pinctrl_of_match);
+
+static struct platform_driver sprd_pinctrl_driver = {
+ .driver = {
+ .name = "sprd-pinctrl",
+ .of_match_table = sprd_pinctrl_of_match,
+ },
+ .probe = sprd_pinctrl_probe,
+ .remove = sprd_pinctrl_remove,
+ .shutdown = sprd_pinctrl_shutdown,
+};
+module_platform_driver(sprd_pinctrl_driver);
+
+MODULE_DESCRIPTION("UNISOC Pin Controller Driver");
+MODULE_AUTHOR("linhua xu <linhua.xu@unisoc.com>");
+MODULE_LICENSE("GPL");
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH V3 6/6] pinctrl: sprd: Add pinctrl support for UMS9621
2023-10-27 7:14 [PATCH V3 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linhua Xu
` (4 preceding siblings ...)
2023-10-27 7:14 ` [PATCH V3 5/6] pinctrl: sprd: Add pinctrl support for UMS512 Linhua Xu
@ 2023-10-27 7:14 ` Linhua Xu
2023-10-27 11:42 ` Andy Shevchenko
5 siblings, 1 reply; 13+ messages in thread
From: Linhua Xu @ 2023-10-27 7:14 UTC (permalink / raw)
To: Linus Walleij
Cc: Orson Zhai, Baolin Wang, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Linhua Xu, Zhirong Qiu, Xiongpeng Wu
From: Linhua Xu <Linhua.Xu@unisoc.com>
Add the pin control driver for UNISOC UMS9621 platform.
Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
---
drivers/pinctrl/sprd/Kconfig | 11 +
drivers/pinctrl/sprd/Makefile | 1 +
drivers/pinctrl/sprd/pinctrl-sprd-ums9621.c | 1120 +++++++++++++++++++
3 files changed, 1132 insertions(+)
create mode 100644 drivers/pinctrl/sprd/pinctrl-sprd-ums9621.c
diff --git a/drivers/pinctrl/sprd/Kconfig b/drivers/pinctrl/sprd/Kconfig
index a2a653c63137..b57f0555dfa6 100644
--- a/drivers/pinctrl/sprd/Kconfig
+++ b/drivers/pinctrl/sprd/Kconfig
@@ -30,3 +30,14 @@ config PINCTRL_SPRD_UMS512
Support pin drive capability configuration
Support pin pull-up and pull-down configuration
Support pin pull-up and pull-down configuration during sleep
+
+config PINCTRL_SPRD_UMS9621
+ tristate "Spreadtrum ums9621 pinctrl driver"
+ depends on ARCH_SPRD || COMPILE_TEST
+ select PINCTRL_SPRD
+ help
+ Say Y here to enable Spreadtrum ums512 pinctrl driver
+ Support pin function switching
+ Support pin drive capability configuration
+ Support pin pull-up and pull-down configuration
+ Support pin pull-up and pull-down configuration during sleep
diff --git a/drivers/pinctrl/sprd/Makefile b/drivers/pinctrl/sprd/Makefile
index e3509c2515c9..6c1946c664b7 100644
--- a/drivers/pinctrl/sprd/Makefile
+++ b/drivers/pinctrl/sprd/Makefile
@@ -2,3 +2,4 @@
obj-$(CONFIG_PINCTRL_SPRD) += pinctrl-sprd.o
obj-$(CONFIG_PINCTRL_SPRD_SC9860) += pinctrl-sprd-sc9860.o
obj-$(CONFIG_PINCTRL_SPRD_UMS512) += pinctrl-sprd-ums512.o
+obj-$(CONFIG_PINCTRL_SPRD_UMS9621) += pinctrl-sprd-ums9621.o
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd-ums9621.c b/drivers/pinctrl/sprd/pinctrl-sprd-ums9621.c
new file mode 100644
index 000000000000..9536fbd67419
--- /dev/null
+++ b/drivers/pinctrl/sprd/pinctrl-sprd-ums9621.c
@@ -0,0 +1,1120 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Unisoc ums9621 pinctrl driver
+ *
+ * Copyright (C) 2021 Unisoc, Inc.
+ * Author: zhirong.qiu <zhirong.qiu@unisoc.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-sprd.h"
+
+#define PINCTRL_REG_OFFSET 0x0044
+#define PINCTRL_REG_MISC_OFFSET 0x0444
+
+enum sprd_ums9621_pins {
+ /*sim_matrix_mtx_cfg*/
+ UMS9621_SIM_INF1_SYS_SEL = SPRD_PIN_INFO(0, GLOBAL_CTRL_PIN, 1, 1, 1),
+ UMS9621_SIM_INF0_SYS_SEL = SPRD_PIN_INFO(1, GLOBAL_CTRL_PIN, 0, 1, 1),
+
+ /*dmic_matrix_mtx_cfg*/
+ UMS9621_DMIC_INF2_SYS_SEL = SPRD_PIN_INFO(2, GLOBAL_CTRL_PIN, 2, 1, 2),
+ UMS9621_DMIC_INF1_SYS_SEL = SPRD_PIN_INFO(3, GLOBAL_CTRL_PIN, 1, 1, 2),
+ UMS9621_DMIC_INF0_SYS_SEL = SPRD_PIN_INFO(4, GLOBAL_CTRL_PIN, 0, 1, 2),
+
+ /*uart_matrix_mtx_cfg*/
+ UMS9621_UART_INF6_SYS_SEL = SPRD_PIN_INFO(5, GLOBAL_CTRL_PIN, 28, 4, 3),
+ UMS9621_UART_INF5_SYS_SEL = SPRD_PIN_INFO(6, GLOBAL_CTRL_PIN, 24, 4, 3),
+ UMS9621_UART_INF4_SYS_SEL = SPRD_PIN_INFO(7, GLOBAL_CTRL_PIN, 20, 4, 3),
+ UMS9621_UART_INF3_SYS_SEL = SPRD_PIN_INFO(8, GLOBAL_CTRL_PIN, 16, 4, 3),
+ UMS9621_UART_INF2_INF3_LOOP = SPRD_PIN_INFO(9, GLOBAL_CTRL_PIN, 15, 1, 3),
+ UMS9621_UART_INF2_INF4_LOOP = SPRD_PIN_INFO(10, GLOBAL_CTRL_PIN, 14, 1, 3),
+ UMS9621_UART_INF2_SYS_SEL = SPRD_PIN_INFO(11, GLOBAL_CTRL_PIN, 10, 4, 3),
+ UMS9621_UART_INF1_INF4_LOOP = SPRD_PIN_INFO(12, GLOBAL_CTRL_PIN, 9, 1, 3),
+ UMS9621_UART_INF1_INF3_LOOP = SPRD_PIN_INFO(13, GLOBAL_CTRL_PIN, 8, 1, 3),
+ UMS9621_UART_INF1_SYS_SEL = SPRD_PIN_INFO(14, GLOBAL_CTRL_PIN, 4, 4, 3),
+ UMS9621_UART_INF0_SYS_SEL = SPRD_PIN_INFO(15, GLOBAL_CTRL_PIN, 0, 4, 3),
+
+ /*uart_matrix_mtx_cfg1*/
+ UMS9621_UART_INF8_SYS_SEL = SPRD_PIN_INFO(16, GLOBAL_CTRL_PIN, 4, 4, 4),
+ UMS9621_UART_INF7_SYS_SEL = SPRD_PIN_INFO(17, GLOBAL_CTRL_PIN, 0, 4, 4),
+
+ /*iis_matrix_mtx_cfg*/
+ UMS9621_IIS_INF4_SYS_SEL = SPRD_PIN_INFO(18, GLOBAL_CTRL_PIN, 23, 5, 5),
+ UMS9621_IIS_INF3_SYS_SEL = SPRD_PIN_INFO(19, GLOBAL_CTRL_PIN, 18, 5, 5),
+ UMS9621_IIS_INF2_SYS_SEL = SPRD_PIN_INFO(20, GLOBAL_CTRL_PIN, 13, 5, 5),
+ UMS9621_IIS_INF1_INF2_LOOP = SPRD_PIN_INFO(21, GLOBAL_CTRL_PIN, 12, 1, 5),
+ UMS9621_IIS_INF1_SYS_SEL = SPRD_PIN_INFO(22, GLOBAL_CTRL_PIN, 7, 5, 5),
+ UMS9621_IIS_INF0_INF2_LOOP = SPRD_PIN_INFO(23, GLOBAL_CTRL_PIN, 6, 1, 5),
+ UMS9621_IIS_INF0_INF1_LOOP = SPRD_PIN_INFO(24, GLOBAL_CTRL_PIN, 5, 1, 5),
+ UMS9621_IIS_INF0_SYS_SEL = SPRD_PIN_INFO(25, GLOBAL_CTRL_PIN, 0, 5, 5),
+
+ /*iis_matrix_mtx_cfg1*/
+ UMS9621_IIS_INF6_SYS_SEL = SPRD_PIN_INFO(26, GLOBAL_CTRL_PIN, 5, 1, 6),
+ UMS9621_IIS_INF5_SYS_SEL = SPRD_PIN_INFO(27, GLOBAL_CTRL_PIN, 0, 5, 6),
+
+ /*spi_matrix_mtx_cfg*/
+ UMS9621_SPI_INF3_SYS_SEL = SPRD_PIN_INFO(28, GLOBAL_CTRL_PIN, 6, 2, 7),
+ UMS9621_SPI_INF2_SYS_SEL = SPRD_PIN_INFO(29, GLOBAL_CTRL_PIN, 4, 2, 7),
+ UMS9621_SPI_INF1_SYS_SEL = SPRD_PIN_INFO(30, GLOBAL_CTRL_PIN, 2, 2, 7),
+ UMS9621_SPI_INF0_SYS_SEL = SPRD_PIN_INFO(31, GLOBAL_CTRL_PIN, 0, 2, 7),
+
+ /*iic_matrix_mtx_cfg*/
+ UMS9621_IIC_INF7_SYS_SEL = SPRD_PIN_INFO(32, GLOBAL_CTRL_PIN, 28, 4, 8),
+ UMS9621_IIC_INF6_SYS_SEL = SPRD_PIN_INFO(33, GLOBAL_CTRL_PIN, 24, 4, 8),
+ UMS9621_IIC_INF5_SYS_SEL = SPRD_PIN_INFO(34, GLOBAL_CTRL_PIN, 20, 4, 8),
+ UMS9621_IIC_INF4_SYS_SEL = SPRD_PIN_INFO(35, GLOBAL_CTRL_PIN, 16, 4, 8),
+ UMS9621_IIC_INF3_SYS_SEL = SPRD_PIN_INFO(36, GLOBAL_CTRL_PIN, 12, 4, 8),
+ UMS9621_IIC_INF2_SYS_SEL = SPRD_PIN_INFO(37, GLOBAL_CTRL_PIN, 8, 4, 8),
+ UMS9621_IIC_INF1_SYS_SEL = SPRD_PIN_INFO(38, GLOBAL_CTRL_PIN, 4, 4, 8),
+ UMS9621_IIC_INF0_SYS_SEL = SPRD_PIN_INFO(39, GLOBAL_CTRL_PIN, 0, 4, 8),
+
+ /*iic_matrix_mtx_cfg1*/
+ UMS9621_IIC_INF9_SYS_SEL = SPRD_PIN_INFO(40, GLOBAL_CTRL_PIN, 4, 4, 9),
+ UMS9621_IIC_INF8_SYS_SEL = SPRD_PIN_INFO(41, GLOBAL_CTRL_PIN, 0, 4, 9),
+
+ /*hot_plug_matrix_mtx_cfg*/
+ UMS9621_HOT_PLUG_DET_INF2_SYS_SEL = SPRD_PIN_INFO(42, GLOBAL_CTRL_PIN, 4, 2, 10),
+ UMS9621_HOT_PLUG_DET_INF1_SYS_SEL = SPRD_PIN_INFO(43, GLOBAL_CTRL_PIN, 2, 2, 10),
+ UMS9621_HOT_PLUG_DET_INF0_SYS_SEL = SPRD_PIN_INFO(44, GLOBAL_CTRL_PIN, 0, 2, 10),
+
+ /*PIN_CTRL_REG0*/
+ UMS9621_PIN_CTRL_REG0_FUNC_CFG = SPRD_PIN_INFO(45, GLOBAL_CTRL_PIN, 0, 1, 11),
+
+ /*PIN_CTRL_REG1*/
+ UMS9621_PIN_CTRL_REG1_FUNC_CFG = SPRD_PIN_INFO(46, GLOBAL_CTRL_PIN, 0, 0, 12),
+
+ /*PIN_CTRL_REG2*/
+ UMS9621_UART_USB_PHY_SEL = SPRD_PIN_INFO(47, GLOBAL_CTRL_PIN, 29, 3, 13),
+
+
+ /*PIN_CTRL_REG3*/
+ UMS9621_CH_EIC_DPAD3 = SPRD_PIN_INFO(48, GLOBAL_CTRL_PIN, 24, 8, 14),
+ UMS9621_CH_EIC_DPAD2 = SPRD_PIN_INFO(49, GLOBAL_CTRL_PIN, 16, 8, 14),
+ UMS9621_CH_EIC_DPAD1 = SPRD_PIN_INFO(50, GLOBAL_CTRL_PIN, 8, 8, 14),
+ UMS9621_CH_EIC_DPAD0 = SPRD_PIN_INFO(51, GLOBAL_CTRL_PIN, 0, 8, 14),
+
+ /*PIN_CTRL_REG4*/
+ UMS9621_CH_EIC_DPAD7 = SPRD_PIN_INFO(52, GLOBAL_CTRL_PIN, 24, 8, 15),
+ UMS9621_CH_EIC_DPAD6 = SPRD_PIN_INFO(53, GLOBAL_CTRL_PIN, 16, 8, 15),
+ UMS9621_CH_EIC_DPAD5 = SPRD_PIN_INFO(54, GLOBAL_CTRL_PIN, 8, 8, 15),
+ UMS9621_CH_EIC_DPAD4 = SPRD_PIN_INFO(55, GLOBAL_CTRL_PIN, 0, 8, 15),
+
+ /*PIN_CTRL_REG5*/
+ UMS9621_CORE_OUT_WDGRST_SOUR_SEL = SPRD_PIN_INFO(56, GLOBAL_CTRL_PIN, 28, 4, 16),
+ UMS9621_VBC_IIS_INF_SYS_SEL = SPRD_PIN_INFO(57, GLOBAL_CTRL_PIN, 20, 1, 16),
+ UMS9621_VAD_DIN_SEL = SPRD_PIN_INFO(58, GLOBAL_CTRL_PIN, 19, 1, 16),
+ UMS9621_TF_DET_SW = SPRD_PIN_INFO(59, GLOBAL_CTRL_PIN, 10, 1, 16),
+ UMS9621_CORE_IN_TF_DET_MUX = SPRD_PIN_INFO(60, GLOBAL_CTRL_PIN, 8, 2, 16),
+ UMS9621_SIM1_DET_SW = SPRD_PIN_INFO(61, GLOBAL_CTRL_PIN, 6, 1, 16),
+ UMS9621_CORE_IN_SIM1_DET_MUX = SPRD_PIN_INFO(62, GLOBAL_CTRL_PIN, 4, 2, 16),
+ UMS9621_SIM0_DET_SW = SPRD_PIN_INFO(63, GLOBAL_CTRL_PIN, 2, 1, 16),
+ UMS9621_CORE_IN_SIM0_DET_MUX = SPRD_PIN_INFO(64, GLOBAL_CTRL_PIN, 0, 2, 16),
+
+ /* Common pin registers definitions */
+ UMS9621_SD1_CMD = SPRD_PIN_INFO(65, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD1_D0 = SPRD_PIN_INFO(66, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD1_D1 = SPRD_PIN_INFO(67, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD1_CLK = SPRD_PIN_INFO(68, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD1_D2 = SPRD_PIN_INFO(69, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD1_D3 = SPRD_PIN_INFO(70, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_RST = SPRD_PIN_INFO(71, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_CMD = SPRD_PIN_INFO(72, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_D0 = SPRD_PIN_INFO(73, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_D3 = SPRD_PIN_INFO(74, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_D2 = SPRD_PIN_INFO(75, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_D5 = SPRD_PIN_INFO(76, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_CLK = SPRD_PIN_INFO(77, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_DS = SPRD_PIN_INFO(78, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_D1 = SPRD_PIN_INFO(79, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_D4 = SPRD_PIN_INFO(80, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_D6 = SPRD_PIN_INFO(81, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_D7 = SPRD_PIN_INFO(82, COMMON_PIN, 0, 0, 0),
+ UMS9621_DNS_D0 = SPRD_PIN_INFO(83, COMMON_PIN, 0, 0, 0),
+ UMS9621_DNS_D1 = SPRD_PIN_INFO(84, COMMON_PIN, 0, 0, 0),
+ UMS9621_LCM0_RSTN = SPRD_PIN_INFO(85, COMMON_PIN, 0, 0, 0),
+ UMS9621_DSI0_TE = SPRD_PIN_INFO(86, COMMON_PIN, 0, 0, 0),
+ UMS9621_PWMA = SPRD_PIN_INFO(87, COMMON_PIN, 0, 0, 0),
+ UMS9621_EXTINT0 = SPRD_PIN_INFO(88, COMMON_PIN, 0, 0, 0),
+ UMS9621_EXTINT1 = SPRD_PIN_INFO(89, COMMON_PIN, 0, 0, 0),
+ UMS9621_SDA3 = SPRD_PIN_INFO(90, COMMON_PIN, 0, 0, 0),
+ UMS9621_SCL3 = SPRD_PIN_INFO(91, COMMON_PIN, 0, 0, 0),
+ UMS9621_DCDC_ARM1_EN = SPRD_PIN_INFO(92, COMMON_PIN, 0, 0, 0),
+ UMS9621_PTEST = SPRD_PIN_INFO(93, COMMON_PIN, 0, 0, 0),
+ UMS9621_EXT_RST_B = SPRD_PIN_INFO(94, COMMON_PIN, 0, 0, 0),
+ UMS9621_ADI_SCLK = SPRD_PIN_INFO(95, COMMON_PIN, 0, 0, 0),
+ UMS9621_CLK_32K = SPRD_PIN_INFO(96, COMMON_PIN, 0, 0, 0),
+ UMS9621_ANA_INT1 = SPRD_PIN_INFO(97, COMMON_PIN, 0, 0, 0),
+ UMS9621_ANA_INT0 = SPRD_PIN_INFO(98, COMMON_PIN, 0, 0, 0),
+ UMS9621_ANA_INT2 = SPRD_PIN_INFO(99, COMMON_PIN, 0, 0, 0),
+ UMS9621_ADI_D = SPRD_PIN_INFO(100, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_SCLK = SPRD_PIN_INFO(101, COMMON_PIN, 0, 0, 0),
+ UMS9621_DCDC_ARM0_EN = SPRD_PIN_INFO(102, COMMON_PIN, 0, 0, 0),
+ UMS9621_DCDC_ARM2_EN = SPRD_PIN_INFO(103, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_ADD0 = SPRD_PIN_INFO(104, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_ADD1 = SPRD_PIN_INFO(105, COMMON_PIN, 0, 0, 0),
+ UMS9621_XTL_EN0 = SPRD_PIN_INFO(106, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_ADSYNC = SPRD_PIN_INFO(107, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_DAD0 = SPRD_PIN_INFO(108, COMMON_PIN, 0, 0, 0),
+ UMS9621_XTL_EN1 = SPRD_PIN_INFO(109, COMMON_PIN, 0, 0, 0),
+ UMS9621_XTL_EN2 = SPRD_PIN_INFO(110, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_DASYNC = SPRD_PIN_INFO(111, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_DAD1 = SPRD_PIN_INFO(112, COMMON_PIN, 0, 0, 0),
+ UMS9621_CHIP_SLEEP = SPRD_PIN_INFO(113, COMMON_PIN, 0, 0, 0),
+ UMS9621_CHG_TYPE = SPRD_PIN_INFO(114, COMMON_PIN, 0, 0, 0),
+ UMS9621_SIMCLK0 = SPRD_PIN_INFO(115, COMMON_PIN, 0, 0, 0),
+ UMS9621_SIMDA0 = SPRD_PIN_INFO(116, COMMON_PIN, 0, 0, 0),
+ UMS9621_SIMRST0 = SPRD_PIN_INFO(117, COMMON_PIN, 0, 0, 0),
+ UMS9621_SIMCLK1 = SPRD_PIN_INFO(118, COMMON_PIN, 0, 0, 0),
+ UMS9621_SIMDA1 = SPRD_PIN_INFO(119, COMMON_PIN, 0, 0, 0),
+ UMS9621_SIMRST1 = SPRD_PIN_INFO(120, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD0_CMD = SPRD_PIN_INFO(121, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD0_D_0 = SPRD_PIN_INFO(122, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD0_D_1 = SPRD_PIN_INFO(123, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD0_CLK = SPRD_PIN_INFO(124, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD0_D_2 = SPRD_PIN_INFO(125, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD0_D_3 = SPRD_PIN_INFO(126, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD2_CLK = SPRD_PIN_INFO(127, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD2_D1 = SPRD_PIN_INFO(128, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD2_CMD = SPRD_PIN_INFO(129, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD2_D0 = SPRD_PIN_INFO(130, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD2_D2 = SPRD_PIN_INFO(131, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD2_D3 = SPRD_PIN_INFO(132, COMMON_PIN, 0, 0, 0),
+ UMS9621_SIM_DET0 = SPRD_PIN_INFO(133, COMMON_PIN, 0, 0, 0),
+ UMS9621_SIM_DET1 = SPRD_PIN_INFO(134, COMMON_PIN, 0, 0, 0),
+ UMS9621_TF_DET = SPRD_PIN_INFO(135, COMMON_PIN, 0, 0, 0),
+ UMS9621_BAT_DET = SPRD_PIN_INFO(136, COMMON_PIN, 0, 0, 0),
+ UMS9621_SCL4 = SPRD_PIN_INFO(137, COMMON_PIN, 0, 0, 0),
+ UMS9621_SDA4 = SPRD_PIN_INFO(138, COMMON_PIN, 0, 0, 0),
+ UMS9621_CLK_AUX1 = SPRD_PIN_INFO(139, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS1DI = SPRD_PIN_INFO(140, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS1DO = SPRD_PIN_INFO(141, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS1CLK = SPRD_PIN_INFO(142, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS1LRCK = SPRD_PIN_INFO(143, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS3DI = SPRD_PIN_INFO(144, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS3DO = SPRD_PIN_INFO(145, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS3LRCK = SPRD_PIN_INFO(146, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS3CLK = SPRD_PIN_INFO(147, COMMON_PIN, 0, 0, 0),
+ UMS9621_CLK_AUX2 = SPRD_PIN_INFO(148, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_0 = SPRD_PIN_INFO(149, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_1 = SPRD_PIN_INFO(150, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_2 = SPRD_PIN_INFO(151, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_3 = SPRD_PIN_INFO(152, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_4 = SPRD_PIN_INFO(153, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_5 = SPRD_PIN_INFO(154, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_6 = SPRD_PIN_INFO(155, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_7 = SPRD_PIN_INFO(156, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_8 = SPRD_PIN_INFO(157, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_9 = SPRD_PIN_INFO(158, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_10 = SPRD_PIN_INFO(159, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_11 = SPRD_PIN_INFO(160, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_12 = SPRD_PIN_INFO(161, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_13 = SPRD_PIN_INFO(162, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_14 = SPRD_PIN_INFO(163, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_15 = SPRD_PIN_INFO(164, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE0_SCK = SPRD_PIN_INFO(165, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE0_SDA = SPRD_PIN_INFO(166, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE1_SCK = SPRD_PIN_INFO(167, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE1_SDA = SPRD_PIN_INFO(168, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE2_SCK = SPRD_PIN_INFO(169, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE2_SDA = SPRD_PIN_INFO(170, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE3_SCK = SPRD_PIN_INFO(171, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE3_SDA = SPRD_PIN_INFO(172, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE4_SCK = SPRD_PIN_INFO(173, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE4_SDA = SPRD_PIN_INFO(174, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE5_SCK = SPRD_PIN_INFO(175, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE5_SDA = SPRD_PIN_INFO(176, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE6_SCK = SPRD_PIN_INFO(177, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE6_SDA = SPRD_PIN_INFO(178, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE7_SCK = SPRD_PIN_INFO(179, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE7_SDA = SPRD_PIN_INFO(180, COMMON_PIN, 0, 0, 0),
+ UMS9621_LVDSRF_ADDAC0_ON = SPRD_PIN_INFO(181, COMMON_PIN, 0, 0, 0),
+ UMS9621_LVDSRF_ADDAC1_ON = SPRD_PIN_INFO(182, COMMON_PIN, 0, 0, 0),
+ UMS9621_LVDSRF_ADDAC2_ON = SPRD_PIN_INFO(183, COMMON_PIN, 0, 0, 0),
+ UMS9621_LVDSRF_ADDAC3_ON = SPRD_PIN_INFO(184, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SDA0 = SPRD_PIN_INFO(185, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SDA1 = SPRD_PIN_INFO(186, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SDA2 = SPRD_PIN_INFO(187, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SDA3 = SPRD_PIN_INFO(188, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SCK = SPRD_PIN_INFO(189, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SEN = SPRD_PIN_INFO(190, COMMON_PIN, 0, 0, 0),
+ UMS9621_SCL6 = SPRD_PIN_INFO(191, COMMON_PIN, 0, 0, 0),
+ UMS9621_SDA6 = SPRD_PIN_INFO(192, COMMON_PIN, 0, 0, 0),
+ UMS9621_VDSP_TDO = SPRD_PIN_INFO(193, COMMON_PIN, 0, 0, 0),
+ UMS9621_VDSP_TDI = SPRD_PIN_INFO(194, COMMON_PIN, 0, 0, 0),
+ UMS9621_VDSP_TMS = SPRD_PIN_INFO(195, COMMON_PIN, 0, 0, 0),
+ UMS9621_VDSP_TCK = SPRD_PIN_INFO(196, COMMON_PIN, 0, 0, 0),
+ UMS9621_VDSP_RTCK = SPRD_PIN_INFO(197, COMMON_PIN, 0, 0, 0),
+ UMS9621_DMIC_CLK2 = SPRD_PIN_INFO(198, COMMON_PIN, 0, 0, 0),
+ UMS9621_DMIC_DATA2 = SPRD_PIN_INFO(199, COMMON_PIN, 0, 0, 0),
+ UMS9621_DMIC_CLK0 = SPRD_PIN_INFO(200, COMMON_PIN, 0, 0, 0),
+ UMS9621_DMIC_DATA0 = SPRD_PIN_INFO(201, COMMON_PIN, 0, 0, 0),
+ UMS9621_DMIC_CLK1 = SPRD_PIN_INFO(202, COMMON_PIN, 0, 0, 0),
+ UMS9621_DMIC_DATA1 = SPRD_PIN_INFO(203, COMMON_PIN, 0, 0, 0),
+ UMS9621_U2TXD = SPRD_PIN_INFO(204, COMMON_PIN, 0, 0, 0),
+ UMS9621_U2RXD = SPRD_PIN_INFO(205, COMMON_PIN, 0, 0, 0),
+ UMS9621_U1TXD = SPRD_PIN_INFO(206, COMMON_PIN, 0, 0, 0),
+ UMS9621_U1RXD = SPRD_PIN_INFO(207, COMMON_PIN, 0, 0, 0),
+ UMS9621_U7TXD = SPRD_PIN_INFO(208, COMMON_PIN, 0, 0, 0),
+ UMS9621_U7RXD = SPRD_PIN_INFO(209, COMMON_PIN, 0, 0, 0),
+ UMS9621_U6TXD = SPRD_PIN_INFO(210, COMMON_PIN, 0, 0, 0),
+ UMS9621_U6RXD = SPRD_PIN_INFO(211, COMMON_PIN, 0, 0, 0),
+ UMS9621_MTCK_ARM = SPRD_PIN_INFO(212, COMMON_PIN, 0, 0, 0),
+ UMS9621_MTMS_ARM = SPRD_PIN_INFO(213, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_TDO = SPRD_PIN_INFO(214, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_RTCK = SPRD_PIN_INFO(215, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_TDI = SPRD_PIN_INFO(216, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_TCK = SPRD_PIN_INFO(217, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_TMS = SPRD_PIN_INFO(218, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMMCLK0 = SPRD_PIN_INFO(219, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMMCLK1 = SPRD_PIN_INFO(220, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMMCLK2 = SPRD_PIN_INFO(221, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMMCLK3 = SPRD_PIN_INFO(222, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMRST0 = SPRD_PIN_INFO(223, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMRST1 = SPRD_PIN_INFO(224, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMRST2 = SPRD_PIN_INFO(225, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMRST3 = SPRD_PIN_INFO(226, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMRST4 = SPRD_PIN_INFO(227, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMRST5 = SPRD_PIN_INFO(228, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMPD0 = SPRD_PIN_INFO(229, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMPD1 = SPRD_PIN_INFO(230, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMPD2 = SPRD_PIN_INFO(231, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMPD3 = SPRD_PIN_INFO(232, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMPD4 = SPRD_PIN_INFO(233, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMPD5 = SPRD_PIN_INFO(234, COMMON_PIN, 0, 0, 0),
+ UMS9621_SCL0 = SPRD_PIN_INFO(235, COMMON_PIN, 0, 0, 0),
+ UMS9621_SDA0 = SPRD_PIN_INFO(236, COMMON_PIN, 0, 0, 0),
+ UMS9621_SCL1 = SPRD_PIN_INFO(237, COMMON_PIN, 0, 0, 0),
+ UMS9621_SDA1 = SPRD_PIN_INFO(238, COMMON_PIN, 0, 0, 0),
+ UMS9621_SCL8 = SPRD_PIN_INFO(239, COMMON_PIN, 0, 0, 0),
+ UMS9621_SDA8 = SPRD_PIN_INFO(240, COMMON_PIN, 0, 0, 0),
+ UMS9621_SCL9 = SPRD_PIN_INFO(241, COMMON_PIN, 0, 0, 0),
+ UMS9621_SDA9 = SPRD_PIN_INFO(242, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI2_CSN = SPRD_PIN_INFO(243, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI2_DO = SPRD_PIN_INFO(244, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI2_DI = SPRD_PIN_INFO(245, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI2_CLK = SPRD_PIN_INFO(246, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI3_CSN = SPRD_PIN_INFO(247, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI3_CLK = SPRD_PIN_INFO(248, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI3_DI = SPRD_PIN_INFO(249, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI3_DO = SPRD_PIN_INFO(250, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI0_CSN = SPRD_PIN_INFO(251, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI0_DO = SPRD_PIN_INFO(252, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI0_DI = SPRD_PIN_INFO(253, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI0_CLK = SPRD_PIN_INFO(254, COMMON_PIN, 0, 0, 0),
+ UMS9621_SCL2 = SPRD_PIN_INFO(255, COMMON_PIN, 0, 0, 0),
+ UMS9621_SDA2 = SPRD_PIN_INFO(256, COMMON_PIN, 0, 0, 0),
+ UMS9621_KEYOUT1 = SPRD_PIN_INFO(257, COMMON_PIN, 0, 0, 0),
+ UMS9621_KEYOUT0 = SPRD_PIN_INFO(258, COMMON_PIN, 0, 0, 0),
+ UMS9621_KEYOUT2 = SPRD_PIN_INFO(259, COMMON_PIN, 0, 0, 0),
+ UMS9621_EXTINT9 = SPRD_PIN_INFO(260, COMMON_PIN, 0, 0, 0),
+ UMS9621_EXTINT10 = SPRD_PIN_INFO(261, COMMON_PIN, 0, 0, 0),
+ UMS9621_KEYIN0 = SPRD_PIN_INFO(262, COMMON_PIN, 0, 0, 0),
+ UMS9621_KEYIN1 = SPRD_PIN_INFO(263, COMMON_PIN, 0, 0, 0),
+ UMS9621_KEYIN2 = SPRD_PIN_INFO(264, COMMON_PIN, 0, 0, 0),
+ UMS9621_U5TXD = SPRD_PIN_INFO(265, COMMON_PIN, 0, 0, 0),
+ UMS9621_U5RXD = SPRD_PIN_INFO(266, COMMON_PIN, 0, 0, 0),
+ UMS9621_CLK_AUX0 = SPRD_PIN_INFO(267, COMMON_PIN, 0, 0, 0),
+ UMS9621_U0TXD = SPRD_PIN_INFO(268, COMMON_PIN, 0, 0, 0),
+ UMS9621_U0RXD = SPRD_PIN_INFO(269, COMMON_PIN, 0, 0, 0),
+ UMS9621_U0CTS = SPRD_PIN_INFO(270, COMMON_PIN, 0, 0, 0),
+ UMS9621_U0RTS = SPRD_PIN_INFO(271, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS0DI = SPRD_PIN_INFO(272, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS0DO = SPRD_PIN_INFO(273, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS0CLK = SPRD_PIN_INFO(274, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS0LRCK = SPRD_PIN_INFO(275, COMMON_PIN, 0, 0, 0),
+ UMS9621_PWMC = SPRD_PIN_INFO(276, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS4DO = SPRD_PIN_INFO(277, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS4DI = SPRD_PIN_INFO(278, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS4CLK = SPRD_PIN_INFO(279, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS4LRCK = SPRD_PIN_INFO(280, COMMON_PIN, 0, 0, 0),
+ UMS9621_U4TXD = SPRD_PIN_INFO(281, COMMON_PIN, 0, 0, 0),
+ UMS9621_U4RXD = SPRD_PIN_INFO(282, COMMON_PIN, 0, 0, 0),
+ UMS9621_U4CTS = SPRD_PIN_INFO(283, COMMON_PIN, 0, 0, 0),
+ UMS9621_U4RTS = SPRD_PIN_INFO(284, COMMON_PIN, 0, 0, 0),
+
+ /* MSIC pin registers definitions */
+ UMS9621_SD1_CMD_MISC = SPRD_PIN_INFO(285, MISC_PIN, 0, 0, 0),
+ UMS9621_SD1_D0_MISC = SPRD_PIN_INFO(286, MISC_PIN, 0, 0, 0),
+ UMS9621_SD1_D1_MISC = SPRD_PIN_INFO(287, MISC_PIN, 0, 0, 0),
+ UMS9621_SD1_CLK_MISC = SPRD_PIN_INFO(288, MISC_PIN, 0, 0, 0),
+ UMS9621_SD1_D2_MISC = SPRD_PIN_INFO(289, MISC_PIN, 0, 0, 0),
+ UMS9621_SD1_D3_MISC = SPRD_PIN_INFO(290, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_RST_MISC = SPRD_PIN_INFO(291, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_CMD_MISC = SPRD_PIN_INFO(292, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_D0_MISC = SPRD_PIN_INFO(293, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_D3_MISC = SPRD_PIN_INFO(294, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_D2_MISC = SPRD_PIN_INFO(295, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_D5_MISC = SPRD_PIN_INFO(296, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_CLK_MISC = SPRD_PIN_INFO(297, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_DS_MISC = SPRD_PIN_INFO(298, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_D1_MISC = SPRD_PIN_INFO(299, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_D4_MISC = SPRD_PIN_INFO(300, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_D6_MISC = SPRD_PIN_INFO(301, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_D7_MISC = SPRD_PIN_INFO(302, MISC_PIN, 0, 0, 0),
+ UMS9621_DNS_D0_MISC = SPRD_PIN_INFO(303, MISC_PIN, 0, 0, 0),
+ UMS9621_DNS_D1_MISC = SPRD_PIN_INFO(304, MISC_PIN, 0, 0, 0),
+ UMS9621_LCM0_RSTN_MISC = SPRD_PIN_INFO(305, MISC_PIN, 0, 0, 0),
+ UMS9621_DSI0_TE_MISC = SPRD_PIN_INFO(306, MISC_PIN, 0, 0, 0),
+ UMS9621_PWMA_MISC = SPRD_PIN_INFO(307, MISC_PIN, 0, 0, 0),
+ UMS9621_EXTINT0_MISC = SPRD_PIN_INFO(308, MISC_PIN, 0, 0, 0),
+ UMS9621_EXTINT1_MISC = SPRD_PIN_INFO(309, MISC_PIN, 0, 0, 0),
+ UMS9621_SDA3_MISC = SPRD_PIN_INFO(310, MISC_PIN, 0, 0, 0),
+ UMS9621_SCL3_MISC = SPRD_PIN_INFO(311, MISC_PIN, 0, 0, 0),
+ UMS9621_DCDC_ARM1_EN_MISC = SPRD_PIN_INFO(312, MISC_PIN, 0, 0, 0),
+ UMS9621_PTEST_MISC = SPRD_PIN_INFO(313, MISC_PIN, 0, 0, 0),
+ UMS9621_EXT_RST_B_MISC = SPRD_PIN_INFO(314, MISC_PIN, 0, 0, 0),
+ UMS9621_ADI_SCLK_MISC = SPRD_PIN_INFO(315, MISC_PIN, 0, 0, 0),
+ UMS9621_CLK_32K_MISC = SPRD_PIN_INFO(316, MISC_PIN, 0, 0, 0),
+ UMS9621_ANA_INT1_MISC = SPRD_PIN_INFO(317, MISC_PIN, 0, 0, 0),
+ UMS9621_ANA_INT0_MISC = SPRD_PIN_INFO(318, MISC_PIN, 0, 0, 0),
+ UMS9621_ANA_INT2_MISC = SPRD_PIN_INFO(319, MISC_PIN, 0, 0, 0),
+ UMS9621_ADI_D_MISC = SPRD_PIN_INFO(320, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_SCLK_MISC = SPRD_PIN_INFO(321, MISC_PIN, 0, 0, 0),
+ UMS9621_DCDC_ARM0_EN_MISC = SPRD_PIN_INFO(322, MISC_PIN, 0, 0, 0),
+ UMS9621_DCDC_ARM2_EN_MISC = SPRD_PIN_INFO(323, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_ADD0_MISC = SPRD_PIN_INFO(324, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_ADD1_MISC = SPRD_PIN_INFO(325, MISC_PIN, 0, 0, 0),
+ UMS9621_XTL_EN0_MISC = SPRD_PIN_INFO(326, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_ADSYNC_MISC = SPRD_PIN_INFO(327, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_DAD0_MISC = SPRD_PIN_INFO(328, MISC_PIN, 0, 0, 0),
+ UMS9621_XTL_EN1_MISC = SPRD_PIN_INFO(329, MISC_PIN, 0, 0, 0),
+ UMS9621_XTL_EN2_MISC = SPRD_PIN_INFO(330, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_DASYNC_MISC = SPRD_PIN_INFO(331, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_DAD1_MISC = SPRD_PIN_INFO(332, MISC_PIN, 0, 0, 0),
+ UMS9621_CHIP_SLEEP_MISC = SPRD_PIN_INFO(333, MISC_PIN, 0, 0, 0),
+ UMS9621_CHG_TYPE_MISC = SPRD_PIN_INFO(334, MISC_PIN, 0, 0, 0),
+ UMS9621_SIMCLK0_MISC = SPRD_PIN_INFO(335, MISC_PIN, 0, 0, 0),
+ UMS9621_SIMDA0_MISC = SPRD_PIN_INFO(336, MISC_PIN, 0, 0, 0),
+ UMS9621_SIMRST0_MISC = SPRD_PIN_INFO(337, MISC_PIN, 0, 0, 0),
+ UMS9621_SIMCLK1_MISC = SPRD_PIN_INFO(338, MISC_PIN, 0, 0, 0),
+ UMS9621_SIMDA1_MISC = SPRD_PIN_INFO(339, MISC_PIN, 0, 0, 0),
+ UMS9621_SIMRST1_MISC = SPRD_PIN_INFO(340, MISC_PIN, 0, 0, 0),
+ UMS9621_SD0_CMD_MISC = SPRD_PIN_INFO(341, MISC_PIN, 0, 0, 0),
+ UMS9621_SD0_D_0_MISC = SPRD_PIN_INFO(342, MISC_PIN, 0, 0, 0),
+ UMS9621_SD0_D_1_MISC = SPRD_PIN_INFO(343, MISC_PIN, 0, 0, 0),
+ UMS9621_SD0_CLK_MISC = SPRD_PIN_INFO(344, MISC_PIN, 0, 0, 0),
+ UMS9621_SD0_D_2_MISC = SPRD_PIN_INFO(345, MISC_PIN, 0, 0, 0),
+ UMS9621_SD0_D_3_MISC = SPRD_PIN_INFO(346, MISC_PIN, 0, 0, 0),
+ UMS9621_SD2_CLK_MISC = SPRD_PIN_INFO(347, MISC_PIN, 0, 0, 0),
+ UMS9621_SD2_D1_MISC = SPRD_PIN_INFO(348, MISC_PIN, 0, 0, 0),
+ UMS9621_SD2_CMD_MISC = SPRD_PIN_INFO(349, MISC_PIN, 0, 0, 0),
+ UMS9621_SD2_D0_MISC = SPRD_PIN_INFO(350, MISC_PIN, 0, 0, 0),
+ UMS9621_SD2_D2_MISC = SPRD_PIN_INFO(351, MISC_PIN, 0, 0, 0),
+ UMS9621_SD2_D3_MISC = SPRD_PIN_INFO(352, MISC_PIN, 0, 0, 0),
+ UMS9621_SIM_DET0_MISC = SPRD_PIN_INFO(353, MISC_PIN, 0, 0, 0),
+ UMS9621_SIM_DET1_MISC = SPRD_PIN_INFO(354, MISC_PIN, 0, 0, 0),
+ UMS9621_TF_DET_MISC = SPRD_PIN_INFO(355, MISC_PIN, 0, 0, 0),
+ UMS9621_BAT_DET_MISC = SPRD_PIN_INFO(356, MISC_PIN, 0, 0, 0),
+ UMS9621_SCL4_MISC = SPRD_PIN_INFO(357, MISC_PIN, 0, 0, 0),
+ UMS9621_SDA4_MISC = SPRD_PIN_INFO(358, MISC_PIN, 0, 0, 0),
+ UMS9621_CLK_AUX1_MISC = SPRD_PIN_INFO(359, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS1DI_MISC = SPRD_PIN_INFO(360, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS1DO_MISC = SPRD_PIN_INFO(361, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS1CLK_MISC = SPRD_PIN_INFO(362, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS1LRCK_MISC = SPRD_PIN_INFO(363, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS3DI_MISC = SPRD_PIN_INFO(364, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS3DO_MISC = SPRD_PIN_INFO(365, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS3LRCK_MISC = SPRD_PIN_INFO(366, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS3CLK_MISC = SPRD_PIN_INFO(367, MISC_PIN, 0, 0, 0),
+ UMS9621_CLK_AUX2_MISC = SPRD_PIN_INFO(368, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_0_MISC = SPRD_PIN_INFO(369, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_1_MISC = SPRD_PIN_INFO(370, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_2_MISC = SPRD_PIN_INFO(371, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_3_MISC = SPRD_PIN_INFO(372, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_4_MISC = SPRD_PIN_INFO(373, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_5_MISC = SPRD_PIN_INFO(374, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_6_MISC = SPRD_PIN_INFO(375, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_7_MISC = SPRD_PIN_INFO(376, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_8_MISC = SPRD_PIN_INFO(377, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_9_MISC = SPRD_PIN_INFO(378, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_10_MISC = SPRD_PIN_INFO(379, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_11_MISC = SPRD_PIN_INFO(380, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_12_MISC = SPRD_PIN_INFO(381, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_13_MISC = SPRD_PIN_INFO(382, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_14_MISC = SPRD_PIN_INFO(383, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_15_MISC = SPRD_PIN_INFO(384, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE0_SCK_MISC = SPRD_PIN_INFO(385, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE0_SDA_MISC = SPRD_PIN_INFO(386, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE1_SCK_MISC = SPRD_PIN_INFO(387, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE1_SDA_MISC = SPRD_PIN_INFO(388, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE2_SCK_MISC = SPRD_PIN_INFO(389, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE2_SDA_MISC = SPRD_PIN_INFO(390, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE3_SCK_MISC = SPRD_PIN_INFO(391, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE3_SDA_MISC = SPRD_PIN_INFO(392, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE4_SCK_MISC = SPRD_PIN_INFO(393, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE4_SDA_MISC = SPRD_PIN_INFO(394, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE5_SCK_MISC = SPRD_PIN_INFO(395, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE5_SDA_MISC = SPRD_PIN_INFO(396, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE6_SCK_MISC = SPRD_PIN_INFO(397, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE6_SDA_MISC = SPRD_PIN_INFO(398, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE7_SCK_MISC = SPRD_PIN_INFO(399, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE7_SDA_MISC = SPRD_PIN_INFO(400, MISC_PIN, 0, 0, 0),
+ UMS9621_LVDSRF_ADDAC0_ON_MISC = SPRD_PIN_INFO(401, MISC_PIN, 0, 0, 0),
+ UMS9621_LVDSRF_ADDAC1_ON_MISC = SPRD_PIN_INFO(402, MISC_PIN, 0, 0, 0),
+ UMS9621_LVDSRF_ADDAC2_ON_MISC = SPRD_PIN_INFO(403, MISC_PIN, 0, 0, 0),
+ UMS9621_LVDSRF_ADDAC3_ON_MISC = SPRD_PIN_INFO(404, MISC_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SDA0_MISC = SPRD_PIN_INFO(405, MISC_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SDA1_MISC = SPRD_PIN_INFO(406, MISC_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SDA2_MISC = SPRD_PIN_INFO(407, MISC_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SDA3_MISC = SPRD_PIN_INFO(408, MISC_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SCK_MISC = SPRD_PIN_INFO(409, MISC_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SEN_MISC = SPRD_PIN_INFO(410, MISC_PIN, 0, 0, 0),
+ UMS9621_SCL6_MISC = SPRD_PIN_INFO(411, MISC_PIN, 0, 0, 0),
+ UMS9621_SDA6_MISC = SPRD_PIN_INFO(412, MISC_PIN, 0, 0, 0),
+ UMS9621_VDSP_TDO_MISC = SPRD_PIN_INFO(413, MISC_PIN, 0, 0, 0),
+ UMS9621_VDSP_TDI_MISC = SPRD_PIN_INFO(414, MISC_PIN, 0, 0, 0),
+ UMS9621_VDSP_TMS_MISC = SPRD_PIN_INFO(415, MISC_PIN, 0, 0, 0),
+ UMS9621_VDSP_TCK_MISC = SPRD_PIN_INFO(416, MISC_PIN, 0, 0, 0),
+ UMS9621_VDSP_RTCK_MISC = SPRD_PIN_INFO(417, MISC_PIN, 0, 0, 0),
+ UMS9621_DMIC_CLK2_MISC = SPRD_PIN_INFO(418, MISC_PIN, 0, 0, 0),
+ UMS9621_DMIC_DATA2_MISC = SPRD_PIN_INFO(419, MISC_PIN, 0, 0, 0),
+ UMS9621_DMIC_CLK0_MISC = SPRD_PIN_INFO(420, MISC_PIN, 0, 0, 0),
+ UMS9621_DMIC_DATA0_MISC = SPRD_PIN_INFO(421, MISC_PIN, 0, 0, 0),
+ UMS9621_DMIC_CLK1_MISC = SPRD_PIN_INFO(422, MISC_PIN, 0, 0, 0),
+ UMS9621_DMIC_DATA1_MISC = SPRD_PIN_INFO(423, MISC_PIN, 0, 0, 0),
+ UMS9621_U2TXD_MISC = SPRD_PIN_INFO(424, MISC_PIN, 0, 0, 0),
+ UMS9621_U2RXD_MISC = SPRD_PIN_INFO(425, MISC_PIN, 0, 0, 0),
+ UMS9621_U1TXD_MISC = SPRD_PIN_INFO(426, MISC_PIN, 0, 0, 0),
+ UMS9621_U1RXD_MISC = SPRD_PIN_INFO(427, MISC_PIN, 0, 0, 0),
+ UMS9621_U7TXD_MISC = SPRD_PIN_INFO(428, MISC_PIN, 0, 0, 0),
+ UMS9621_U7RXD_MISC = SPRD_PIN_INFO(429, MISC_PIN, 0, 0, 0),
+ UMS9621_U6TXD_MISC = SPRD_PIN_INFO(430, MISC_PIN, 0, 0, 0),
+ UMS9621_U6RXD_MISC = SPRD_PIN_INFO(431, MISC_PIN, 0, 0, 0),
+ UMS9621_MTCK_ARM_MISC = SPRD_PIN_INFO(432, MISC_PIN, 0, 0, 0),
+ UMS9621_MTMS_ARM_MISC = SPRD_PIN_INFO(433, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_TDO_MISC = SPRD_PIN_INFO(434, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_RTCK_MISC = SPRD_PIN_INFO(435, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_TDI_MISC = SPRD_PIN_INFO(436, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_TCK_MISC = SPRD_PIN_INFO(437, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_TMS_MISC = SPRD_PIN_INFO(438, MISC_PIN, 0, 0, 0),
+ UMS9621_CMMCLK0_MISC = SPRD_PIN_INFO(439, MISC_PIN, 0, 0, 0),
+ UMS9621_CMMCLK1_MISC = SPRD_PIN_INFO(440, MISC_PIN, 0, 0, 0),
+ UMS9621_CMMCLK2_MISC = SPRD_PIN_INFO(441, MISC_PIN, 0, 0, 0),
+ UMS9621_CMMCLK3_MISC = SPRD_PIN_INFO(442, MISC_PIN, 0, 0, 0),
+ UMS9621_CMRST0_MISC = SPRD_PIN_INFO(443, MISC_PIN, 0, 0, 0),
+ UMS9621_CMRST1_MISC = SPRD_PIN_INFO(444, MISC_PIN, 0, 0, 0),
+ UMS9621_CMRST2_MISC = SPRD_PIN_INFO(445, MISC_PIN, 0, 0, 0),
+ UMS9621_CMRST3_MISC = SPRD_PIN_INFO(446, MISC_PIN, 0, 0, 0),
+ UMS9621_CMRST4_MISC = SPRD_PIN_INFO(447, MISC_PIN, 0, 0, 0),
+ UMS9621_CMRST5_MISC = SPRD_PIN_INFO(448, MISC_PIN, 0, 0, 0),
+ UMS9621_CMPD0_MISC = SPRD_PIN_INFO(449, MISC_PIN, 0, 0, 0),
+ UMS9621_CMPD1_MISC = SPRD_PIN_INFO(450, MISC_PIN, 0, 0, 0),
+ UMS9621_CMPD2_MISC = SPRD_PIN_INFO(451, MISC_PIN, 0, 0, 0),
+ UMS9621_CMPD3_MISC = SPRD_PIN_INFO(452, MISC_PIN, 0, 0, 0),
+ UMS9621_CMPD4_MISC = SPRD_PIN_INFO(453, MISC_PIN, 0, 0, 0),
+ UMS9621_CMPD5_MISC = SPRD_PIN_INFO(454, MISC_PIN, 0, 0, 0),
+ UMS9621_SCL0_MISC = SPRD_PIN_INFO(455, MISC_PIN, 0, 0, 0),
+ UMS9621_SDA0_MISC = SPRD_PIN_INFO(456, MISC_PIN, 0, 0, 0),
+ UMS9621_SCL1_MISC = SPRD_PIN_INFO(457, MISC_PIN, 0, 0, 0),
+ UMS9621_SDA1_MISC = SPRD_PIN_INFO(458, MISC_PIN, 0, 0, 0),
+ UMS9621_SCL8_MISC = SPRD_PIN_INFO(459, MISC_PIN, 0, 0, 0),
+ UMS9621_SDA8_MISC = SPRD_PIN_INFO(460, MISC_PIN, 0, 0, 0),
+ UMS9621_SCL9_MISC = SPRD_PIN_INFO(461, MISC_PIN, 0, 0, 0),
+ UMS9621_SDA9_MISC = SPRD_PIN_INFO(462, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI2_CSN_MISC = SPRD_PIN_INFO(463, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI2_DO_MISC = SPRD_PIN_INFO(464, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI2_DI_MISC = SPRD_PIN_INFO(465, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI2_CLK_MISC = SPRD_PIN_INFO(466, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI3_CSN_MISC = SPRD_PIN_INFO(467, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI3_CLK_MISC = SPRD_PIN_INFO(468, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI3_DI_MISC = SPRD_PIN_INFO(469, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI3_DO_MISC = SPRD_PIN_INFO(470, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI0_CSN_MISC = SPRD_PIN_INFO(471, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI0_DO_MISC = SPRD_PIN_INFO(472, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI0_DI_MISC = SPRD_PIN_INFO(473, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI0_CLK_MISC = SPRD_PIN_INFO(474, MISC_PIN, 0, 0, 0),
+ UMS9621_SCL2_MISC = SPRD_PIN_INFO(475, MISC_PIN, 0, 0, 0),
+ UMS9621_SDA2_MISC = SPRD_PIN_INFO(476, MISC_PIN, 0, 0, 0),
+ UMS9621_KEYOUT1_MISC = SPRD_PIN_INFO(477, MISC_PIN, 0, 0, 0),
+ UMS9621_KEYOUT0_MISC = SPRD_PIN_INFO(478, MISC_PIN, 0, 0, 0),
+ UMS9621_KEYOUT2_MISC = SPRD_PIN_INFO(479, MISC_PIN, 0, 0, 0),
+ UMS9621_EXTINT9_MISC = SPRD_PIN_INFO(480, MISC_PIN, 0, 0, 0),
+ UMS9621_EXTINT10_MISC = SPRD_PIN_INFO(481, MISC_PIN, 0, 0, 0),
+ UMS9621_KEYIN0_MISC = SPRD_PIN_INFO(482, MISC_PIN, 0, 0, 0),
+ UMS9621_KEYIN1_MISC = SPRD_PIN_INFO(483, MISC_PIN, 0, 0, 0),
+ UMS9621_KEYIN2_MISC = SPRD_PIN_INFO(484, MISC_PIN, 0, 0, 0),
+ UMS9621_U5TXD_MISC = SPRD_PIN_INFO(485, MISC_PIN, 0, 0, 0),
+ UMS9621_U5RXD_MISC = SPRD_PIN_INFO(486, MISC_PIN, 0, 0, 0),
+ UMS9621_CLK_AUX0_MISC = SPRD_PIN_INFO(487, MISC_PIN, 0, 0, 0),
+ UMS9621_U0TXD_MISC = SPRD_PIN_INFO(488, MISC_PIN, 0, 0, 0),
+ UMS9621_U0RXD_MISC = SPRD_PIN_INFO(489, MISC_PIN, 0, 0, 0),
+ UMS9621_U0CTS_MISC = SPRD_PIN_INFO(490, MISC_PIN, 0, 0, 0),
+ UMS9621_U0RTS_MISC = SPRD_PIN_INFO(491, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS0DI_MISC = SPRD_PIN_INFO(492, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS0DO_MISC = SPRD_PIN_INFO(493, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS0CLK_MISC = SPRD_PIN_INFO(494, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS0LRCK_MISC = SPRD_PIN_INFO(495, MISC_PIN, 0, 0, 0),
+ UMS9621_PWMC_MISC = SPRD_PIN_INFO(496, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS4DO_MISC = SPRD_PIN_INFO(497, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS4DI_MISC = SPRD_PIN_INFO(498, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS4CLK_MISC = SPRD_PIN_INFO(499, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS4LRCK_MISC = SPRD_PIN_INFO(500, MISC_PIN, 0, 0, 0),
+ UMS9621_U4TXD_MISC = SPRD_PIN_INFO(501, MISC_PIN, 0, 0, 0),
+ UMS9621_U4RXD_MISC = SPRD_PIN_INFO(502, MISC_PIN, 0, 0, 0),
+ UMS9621_U4CTS_MISC = SPRD_PIN_INFO(503, MISC_PIN, 0, 0, 0),
+ UMS9621_U4RTS_MISC = SPRD_PIN_INFO(504, MISC_PIN, 0, 0, 0),
+
+};
+
+static struct sprd_pins_info sprd_ums9621_pins_info[] = {
+
+ SPRD_PINCTRL_PIN(UMS9621_SIM_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_SIM_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF6_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF5_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF4_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF3_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF2_INF3_LOOP),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF2_INF4_LOOP),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF1_INF4_LOOP),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF1_INF3_LOOP),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF8_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF7_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF4_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF3_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF1_INF2_LOOP),
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF0_INF2_LOOP),
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF0_INF1_LOOP),
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF6_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF5_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_SPI_INF3_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_SPI_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_SPI_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_SPI_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF7_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF6_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF5_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF4_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF3_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF9_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF8_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_HOT_PLUG_DET_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_HOT_PLUG_DET_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_HOT_PLUG_DET_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_PIN_CTRL_REG0_FUNC_CFG),
+
+ SPRD_PINCTRL_PIN(UMS9621_PIN_CTRL_REG1_FUNC_CFG),
+
+ SPRD_PINCTRL_PIN(UMS9621_UART_USB_PHY_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_CH_EIC_DPAD3),
+ SPRD_PINCTRL_PIN(UMS9621_CH_EIC_DPAD2),
+ SPRD_PINCTRL_PIN(UMS9621_CH_EIC_DPAD1),
+ SPRD_PINCTRL_PIN(UMS9621_CH_EIC_DPAD0),
+
+ SPRD_PINCTRL_PIN(UMS9621_CH_EIC_DPAD7),
+ SPRD_PINCTRL_PIN(UMS9621_CH_EIC_DPAD6),
+ SPRD_PINCTRL_PIN(UMS9621_CH_EIC_DPAD5),
+ SPRD_PINCTRL_PIN(UMS9621_CH_EIC_DPAD4),
+
+ SPRD_PINCTRL_PIN(UMS9621_CORE_OUT_WDGRST_SOUR_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_VBC_IIS_INF_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_VAD_DIN_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_TF_DET_SW),
+ SPRD_PINCTRL_PIN(UMS9621_CORE_IN_TF_DET_MUX),
+ SPRD_PINCTRL_PIN(UMS9621_SIM1_DET_SW),
+ SPRD_PINCTRL_PIN(UMS9621_CORE_IN_SIM1_DET_MUX),
+ SPRD_PINCTRL_PIN(UMS9621_SIM0_DET_SW),
+ SPRD_PINCTRL_PIN(UMS9621_CORE_IN_SIM0_DET_MUX),
+
+ SPRD_PINCTRL_PIN(UMS9621_SD1_CMD),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_D0),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_D1),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_CLK),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_D2),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_D3),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_RST),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_CMD),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D0),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D3),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D2),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D5),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_CLK),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_DS),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D1),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D4),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D6),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D7),
+ SPRD_PINCTRL_PIN(UMS9621_DNS_D0),
+ SPRD_PINCTRL_PIN(UMS9621_DNS_D1),
+ SPRD_PINCTRL_PIN(UMS9621_LCM0_RSTN),
+ SPRD_PINCTRL_PIN(UMS9621_DSI0_TE),
+ SPRD_PINCTRL_PIN(UMS9621_PWMA),
+ SPRD_PINCTRL_PIN(UMS9621_EXTINT0),
+ SPRD_PINCTRL_PIN(UMS9621_EXTINT1),
+ SPRD_PINCTRL_PIN(UMS9621_SDA3),
+ SPRD_PINCTRL_PIN(UMS9621_SCL3),
+ SPRD_PINCTRL_PIN(UMS9621_DCDC_ARM1_EN),
+ SPRD_PINCTRL_PIN(UMS9621_PTEST),
+ SPRD_PINCTRL_PIN(UMS9621_EXT_RST_B),
+ SPRD_PINCTRL_PIN(UMS9621_ADI_SCLK),
+ SPRD_PINCTRL_PIN(UMS9621_CLK_32K),
+ SPRD_PINCTRL_PIN(UMS9621_ANA_INT1),
+ SPRD_PINCTRL_PIN(UMS9621_ANA_INT0),
+ SPRD_PINCTRL_PIN(UMS9621_ANA_INT2),
+ SPRD_PINCTRL_PIN(UMS9621_ADI_D),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_SCLK),
+ SPRD_PINCTRL_PIN(UMS9621_DCDC_ARM0_EN),
+ SPRD_PINCTRL_PIN(UMS9621_DCDC_ARM2_EN),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_ADD0),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_ADD1),
+ SPRD_PINCTRL_PIN(UMS9621_XTL_EN0),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_ADSYNC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DAD0),
+ SPRD_PINCTRL_PIN(UMS9621_XTL_EN1),
+ SPRD_PINCTRL_PIN(UMS9621_XTL_EN2),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DASYNC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DAD1),
+ SPRD_PINCTRL_PIN(UMS9621_CHIP_SLEEP),
+ SPRD_PINCTRL_PIN(UMS9621_CHG_TYPE),
+ SPRD_PINCTRL_PIN(UMS9621_SIMCLK0),
+ SPRD_PINCTRL_PIN(UMS9621_SIMDA0),
+ SPRD_PINCTRL_PIN(UMS9621_SIMRST0),
+ SPRD_PINCTRL_PIN(UMS9621_SIMCLK1),
+ SPRD_PINCTRL_PIN(UMS9621_SIMDA1),
+ SPRD_PINCTRL_PIN(UMS9621_SIMRST1),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_CMD),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_D_0),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_D_1),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_CLK),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_D_2),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_D_3),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_CLK),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_D1),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_CMD),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_D0),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_D2),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_D3),
+ SPRD_PINCTRL_PIN(UMS9621_SIM_DET0),
+ SPRD_PINCTRL_PIN(UMS9621_SIM_DET1),
+ SPRD_PINCTRL_PIN(UMS9621_TF_DET),
+ SPRD_PINCTRL_PIN(UMS9621_BAT_DET),
+ SPRD_PINCTRL_PIN(UMS9621_SCL4),
+ SPRD_PINCTRL_PIN(UMS9621_SDA4),
+ SPRD_PINCTRL_PIN(UMS9621_CLK_AUX1),
+ SPRD_PINCTRL_PIN(UMS9621_IIS1DI),
+ SPRD_PINCTRL_PIN(UMS9621_IIS1DO),
+ SPRD_PINCTRL_PIN(UMS9621_IIS1CLK),
+ SPRD_PINCTRL_PIN(UMS9621_IIS1LRCK),
+ SPRD_PINCTRL_PIN(UMS9621_IIS3DI),
+ SPRD_PINCTRL_PIN(UMS9621_IIS3DO),
+ SPRD_PINCTRL_PIN(UMS9621_IIS3LRCK),
+ SPRD_PINCTRL_PIN(UMS9621_IIS3CLK),
+ SPRD_PINCTRL_PIN(UMS9621_CLK_AUX2),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_0),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_1),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_2),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_3),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_4),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_5),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_6),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_7),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_8),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_9),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_10),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_11),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_12),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_13),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_14),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_15),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE0_SCK),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE0_SDA),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE1_SCK),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE1_SDA),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE2_SCK),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE2_SDA),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE3_SCK),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE3_SDA),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE4_SCK),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE4_SDA),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE5_SCK),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE5_SDA),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE6_SCK),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE6_SDA),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE7_SCK),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE7_SDA),
+ SPRD_PINCTRL_PIN(UMS9621_LVDSRF_ADDAC0_ON),
+ SPRD_PINCTRL_PIN(UMS9621_LVDSRF_ADDAC1_ON),
+ SPRD_PINCTRL_PIN(UMS9621_LVDSRF_ADDAC2_ON),
+ SPRD_PINCTRL_PIN(UMS9621_LVDSRF_ADDAC3_ON),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SDA0),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SDA1),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SDA2),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SDA3),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SCK),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SEN),
+ SPRD_PINCTRL_PIN(UMS9621_SCL6),
+ SPRD_PINCTRL_PIN(UMS9621_SDA6),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_TDO),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_TDI),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_TMS),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_TCK),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_RTCK),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_CLK2),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_DATA2),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_CLK0),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_DATA0),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_CLK1),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_DATA1),
+ SPRD_PINCTRL_PIN(UMS9621_U2TXD),
+ SPRD_PINCTRL_PIN(UMS9621_U2RXD),
+ SPRD_PINCTRL_PIN(UMS9621_U1TXD),
+ SPRD_PINCTRL_PIN(UMS9621_U1RXD),
+ SPRD_PINCTRL_PIN(UMS9621_U7TXD),
+ SPRD_PINCTRL_PIN(UMS9621_U7RXD),
+ SPRD_PINCTRL_PIN(UMS9621_U6TXD),
+ SPRD_PINCTRL_PIN(UMS9621_U6RXD),
+ SPRD_PINCTRL_PIN(UMS9621_MTCK_ARM),
+ SPRD_PINCTRL_PIN(UMS9621_MTMS_ARM),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_TDO),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_RTCK),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_TDI),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_TCK),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_TMS),
+ SPRD_PINCTRL_PIN(UMS9621_CMMCLK0),
+ SPRD_PINCTRL_PIN(UMS9621_CMMCLK1),
+ SPRD_PINCTRL_PIN(UMS9621_CMMCLK2),
+ SPRD_PINCTRL_PIN(UMS9621_CMMCLK3),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST0),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST1),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST2),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST3),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST4),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST5),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD0),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD1),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD2),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD3),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD4),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD5),
+ SPRD_PINCTRL_PIN(UMS9621_SCL0),
+ SPRD_PINCTRL_PIN(UMS9621_SDA0),
+ SPRD_PINCTRL_PIN(UMS9621_SCL1),
+ SPRD_PINCTRL_PIN(UMS9621_SDA1),
+ SPRD_PINCTRL_PIN(UMS9621_SCL8),
+ SPRD_PINCTRL_PIN(UMS9621_SDA8),
+ SPRD_PINCTRL_PIN(UMS9621_SCL9),
+ SPRD_PINCTRL_PIN(UMS9621_SDA9),
+ SPRD_PINCTRL_PIN(UMS9621_SPI2_CSN),
+ SPRD_PINCTRL_PIN(UMS9621_SPI2_DO),
+ SPRD_PINCTRL_PIN(UMS9621_SPI2_DI),
+ SPRD_PINCTRL_PIN(UMS9621_SPI2_CLK),
+ SPRD_PINCTRL_PIN(UMS9621_SPI3_CSN),
+ SPRD_PINCTRL_PIN(UMS9621_SPI3_CLK),
+ SPRD_PINCTRL_PIN(UMS9621_SPI3_DI),
+ SPRD_PINCTRL_PIN(UMS9621_SPI3_DO),
+ SPRD_PINCTRL_PIN(UMS9621_SPI0_CSN),
+ SPRD_PINCTRL_PIN(UMS9621_SPI0_DO),
+ SPRD_PINCTRL_PIN(UMS9621_SPI0_DI),
+ SPRD_PINCTRL_PIN(UMS9621_SPI0_CLK),
+ SPRD_PINCTRL_PIN(UMS9621_SCL2),
+ SPRD_PINCTRL_PIN(UMS9621_SDA2),
+ SPRD_PINCTRL_PIN(UMS9621_KEYOUT1),
+ SPRD_PINCTRL_PIN(UMS9621_KEYOUT0),
+ SPRD_PINCTRL_PIN(UMS9621_KEYOUT2),
+ SPRD_PINCTRL_PIN(UMS9621_EXTINT9),
+ SPRD_PINCTRL_PIN(UMS9621_EXTINT10),
+ SPRD_PINCTRL_PIN(UMS9621_KEYIN0),
+ SPRD_PINCTRL_PIN(UMS9621_KEYIN1),
+ SPRD_PINCTRL_PIN(UMS9621_KEYIN2),
+ SPRD_PINCTRL_PIN(UMS9621_U5TXD),
+ SPRD_PINCTRL_PIN(UMS9621_U5RXD),
+ SPRD_PINCTRL_PIN(UMS9621_CLK_AUX0),
+ SPRD_PINCTRL_PIN(UMS9621_U0TXD),
+ SPRD_PINCTRL_PIN(UMS9621_U0RXD),
+ SPRD_PINCTRL_PIN(UMS9621_U0CTS),
+ SPRD_PINCTRL_PIN(UMS9621_U0RTS),
+ SPRD_PINCTRL_PIN(UMS9621_IIS0DI),
+ SPRD_PINCTRL_PIN(UMS9621_IIS0DO),
+ SPRD_PINCTRL_PIN(UMS9621_IIS0CLK),
+ SPRD_PINCTRL_PIN(UMS9621_IIS0LRCK),
+ SPRD_PINCTRL_PIN(UMS9621_PWMC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS4DO),
+ SPRD_PINCTRL_PIN(UMS9621_IIS4DI),
+ SPRD_PINCTRL_PIN(UMS9621_IIS4CLK),
+ SPRD_PINCTRL_PIN(UMS9621_IIS4LRCK),
+ SPRD_PINCTRL_PIN(UMS9621_U4TXD),
+ SPRD_PINCTRL_PIN(UMS9621_U4RXD),
+ SPRD_PINCTRL_PIN(UMS9621_U4CTS),
+ SPRD_PINCTRL_PIN(UMS9621_U4RTS),
+
+ SPRD_PINCTRL_PIN(UMS9621_SD1_CMD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_D0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_D1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_D2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_D3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_RST_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_CMD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D5_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_DS_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D4_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D6_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D7_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DNS_D0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DNS_D1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_LCM0_RSTN_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DSI0_TE_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_PWMA_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EXTINT0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EXTINT1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SDA3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SCL3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DCDC_ARM1_EN_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_PTEST_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EXT_RST_B_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_ADI_SCLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CLK_32K_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_ANA_INT1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_ANA_INT0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_ANA_INT2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_ADI_D_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_SCLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DCDC_ARM0_EN_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DCDC_ARM2_EN_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_ADD0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_ADD1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_XTL_EN0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_ADSYNC_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DAD0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_XTL_EN1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_XTL_EN2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DASYNC_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DAD1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CHIP_SLEEP_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CHG_TYPE_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SIMCLK0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SIMDA0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SIMRST0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SIMCLK1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SIMDA1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SIMRST1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_CMD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_D_0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_D_1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_D_2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_D_3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_D1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_CMD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_D0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_D2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_D3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SIM_DET0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SIM_DET1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_TF_DET_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_BAT_DET_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SCL4_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SDA4_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CLK_AUX1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS1DI_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS1DO_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS1CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS1LRCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS3DI_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS3DO_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS3LRCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS3CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CLK_AUX2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_4_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_5_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_6_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_7_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_8_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_9_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_10_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_11_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_12_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_13_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_14_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_15_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE0_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE0_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE1_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE1_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE2_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE2_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE3_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE3_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE4_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE4_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE5_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE5_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE6_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE6_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE7_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE7_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_LVDSRF_ADDAC0_ON_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_LVDSRF_ADDAC1_ON_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_LVDSRF_ADDAC2_ON_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_LVDSRF_ADDAC3_ON_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SDA0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SDA1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SDA2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SDA3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SEN_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SCL6_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SDA6_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_TDO_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_TDI_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_TMS_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_TCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_RTCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_CLK2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_DATA2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_CLK0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_DATA0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_CLK1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_DATA1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U2TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U2RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U1TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U1RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U7TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U7RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U6TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U6RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_MTCK_ARM_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_MTMS_ARM_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_TDO_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_RTCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_TDI_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_TCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_TMS_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMMCLK0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMMCLK1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMMCLK2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMMCLK3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST4_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST5_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD4_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD5_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SCL0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SDA0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SCL1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SDA1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SCL8_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SDA8_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SCL9_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SDA9_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI2_CSN_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI2_DO_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI2_DI_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI2_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI3_CSN_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI3_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI3_DI_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI3_DO_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI0_CSN_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI0_DO_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI0_DI_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI0_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SCL2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SDA2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_KEYOUT1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_KEYOUT0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_KEYOUT2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EXTINT9_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EXTINT10_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_KEYIN0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_KEYIN1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_KEYIN2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U5TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U5RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CLK_AUX0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U0TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U0RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U0CTS_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U0RTS_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS0DI_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS0DO_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS0CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS0LRCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_PWMC_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS4DO_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS4DI_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS4CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS4LRCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U4TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U4RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U4CTS_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U4RTS_MISC),
+};
+
+static const struct sprd_pinctrl_priv_data ums9621_data = {
+ .common_offset = PINCTRL_REG_OFFSET,
+ .misc_offset = PINCTRL_REG_MISC_OFFSET,
+};
+
+static int sprd_pinctrl_probe(struct platform_device *pdev)
+{
+ return sprd_pinctrl_core_probe(pdev, sprd_ums9621_pins_info,
+ ARRAY_SIZE(sprd_ums9621_pins_info));
+}
+
+static const struct of_device_id sprd_pinctrl_of_match[] = {
+ { .compatible = "sprd,ums9621-pinctrl", .data = &ums9621_data},
+ { }
+};
+MODULE_DEVICE_TABLE(of, sprd_pinctrl_of_match);
+
+static struct platform_driver sprd_pinctrl_driver = {
+ .driver = {
+ .name = "sprd-pinctrl",
+ .of_match_table = sprd_pinctrl_of_match,
+ },
+ .probe = sprd_pinctrl_probe,
+ .remove = sprd_pinctrl_remove,
+ .shutdown = sprd_pinctrl_shutdown,
+};
+module_platform_driver(sprd_pinctrl_driver);
+
+MODULE_DESCRIPTION("UNISOC Pin Controller Driver");
+MODULE_AUTHOR("zhirong qiu <zhirong.qiu@unisoc.com>");
+MODULE_LICENSE("GPL");
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH V3 3/6] pinctrl: sprd: Move common and misc offset parameters to private data
2023-10-27 7:14 ` [PATCH V3 3/6] pinctrl: sprd: Move common and misc offset parameters to private data Linhua Xu
@ 2023-10-27 11:24 ` Andy Shevchenko
0 siblings, 0 replies; 13+ messages in thread
From: Andy Shevchenko @ 2023-10-27 11:24 UTC (permalink / raw)
To: Linhua Xu
Cc: Linus Walleij, Orson Zhai, Baolin Wang, Chunyan Zhang,
linux-kernel, linux-gpio, lh xu, Zhirong Qiu, Xiongpeng Wu
On Fri, Oct 27, 2023 at 03:14:23PM +0800, Linhua Xu wrote:
> From: Linhua Xu <Linhua.Xu@unisoc.com>
>
> For UNISOC pin controller, the offset values of the common
> register and misc register will be different. So add SoC
> structure in sprd_pinctrl_of_match() and parse it in sprd-pinctrl_core.
...
> + priv_data = of_device_get_match_data(&pdev->dev);
> + if (!priv_data)
> + return -EINVAL;
I believe there is the idea to make that API local to the device property core,
so use device_get_match_data() instead.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V3 1/6] pinctrl: sprd: Modify pull-up parameters
2023-10-27 7:14 ` [PATCH V3 1/6] pinctrl: sprd: Modify pull-up parameters Linhua Xu
@ 2023-10-27 11:29 ` Andy Shevchenko
0 siblings, 0 replies; 13+ messages in thread
From: Andy Shevchenko @ 2023-10-27 11:29 UTC (permalink / raw)
To: Linhua Xu
Cc: Linus Walleij, Orson Zhai, Baolin Wang, Chunyan Zhang,
linux-kernel, linux-gpio, lh xu, Zhirong Qiu, Xiongpeng Wu
On Fri, Oct 27, 2023 at 03:14:21PM +0800, Linhua Xu wrote:
> From: Linhua Xu <Linhua.Xu@unisoc.com>
>
> For UNISOC pin controller, there are three different configurations of
> pull-up drive current. Modify the 20K pull-up resistor configuration and
> add the 1.8K pull-up resistor configuration.
> Fixes:<1fb4b907e808> ("pinctrl: sprd: Add Spreadtrum pin control driver")
>
> Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
I guess I already pointed out that there must not be blank lines in the tag
block, besides that read "Submitting Patches" document to see how properly
format the Fixes: tag.
...
> -#define PULL_UP_4_7K (BIT(12) | BIT(7))
> +#define PULL_UP_1_8K (BIT(12) | BIT(7))
> +#define PULL_UP_4_7K BIT(12)
> #define PULL_UP_20K BIT(7)
> #define PULL_UP_MASK 0x21
> #define PULL_UP_SHIFT 7
Basically these two repeat the above 1.8K case.
But I see that you try to take care in the next patch about them.
Still, the better is to use those _MASKs and _SHIFTs in the code.
See below.
...
> if ((reg & (SLEEP_PULL_DOWN | SLEEP_PULL_UP)) ||
> - (reg & (PULL_DOWN | PULL_UP_4_7K | PULL_UP_20K)))
> + (reg & (PULL_DOWN | PULL_UP_4_7K | PULL_UP_20K | PULL_UP_1_8K)))
if ((reg & (SLEEP_PULL_DOWN | SLEEP_PULL_UP)) ||
(reg & (PULL_DOWN | (PULL_UP_MASK << PULL_UP_SHIFT))))
> return -EINVAL;
...
> mask = PULL_DOWN | PULL_UP_20K |
> - PULL_UP_4_7K;
> + PULL_UP_4_7K | PULL_UP_1_8K;
mask = PULL_DOWN | (PULL_UP_MASK << PULL_UP_SHIFT);
Ditto.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V3 2/6] pinctrl: sprd: Fix the incorrect mask and shift definition
2023-10-27 7:14 ` [PATCH V3 2/6] pinctrl: sprd: Fix the incorrect mask and shift definition Linhua Xu
@ 2023-10-27 11:32 ` Andy Shevchenko
0 siblings, 0 replies; 13+ messages in thread
From: Andy Shevchenko @ 2023-10-27 11:32 UTC (permalink / raw)
To: Linhua Xu
Cc: Linus Walleij, Orson Zhai, Baolin Wang, Chunyan Zhang,
linux-kernel, linux-gpio, lh xu, Zhirong Qiu, Xiongpeng Wu
On Fri, Oct 27, 2023 at 03:14:22PM +0800, Linhua Xu wrote:
> From: Linhua Xu <Linhua.Xu@unisoc.com>
>
> Pull-up and pull-down are mutually exclusive. When setting one of them,
> the bit of the other needs to be clear. Now, there are cases where pull-up
> and pull-down are set at the same time in the code, thus fix them.
...
> Fixes:<1fb4b907e808> ("pinctrl: sprd: Add Spreadtrum pin control driver")
>
> Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
Same comment about the Fixes: tag.
...
> -#define SLEEP_PULL_DOWN_MASK 0x1
> +#define SLEEP_PULL_DOWN_MASK GENMASK(1, 0)
> #define SLEEP_PULL_DOWN_SHIFT 2
No, this is an incorrect (prone to errors and confusion) change.
You need to introduce new mask for both of them and use in the code.
#define SLEEP_PULL_UP_DOWN_MASK GENMASK(1, 0)
#define SLEEP_PULL_UP_DOWN_SHIFT 2
...
> -#define PULL_DOWN_MASK 0x1
> +#define PULL_DOWN_MASK (GENMASK(1, 0) | BIT(6))
> #define PULL_DOWN_SHIFT 6
Ditto.
#define PULL_UP_DOWN_MASK (GENMASK(1, 0) | BIT(6))
#define PULL_UP_DOWN_SHIFT 6
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V3 4/6] pinctrl: sprd: Increase the range of register values
2023-10-27 7:14 ` [PATCH V3 4/6] pinctrl: sprd: Increase the range of register values Linhua Xu
@ 2023-10-27 11:39 ` kernel test robot
0 siblings, 0 replies; 13+ messages in thread
From: kernel test robot @ 2023-10-27 11:39 UTC (permalink / raw)
To: Linhua Xu, Linus Walleij
Cc: oe-kbuild-all, Orson Zhai, Baolin Wang, Chunyan Zhang,
linux-kernel, linux-gpio, Andy Shevchenko, lh xu, Linhua Xu,
Zhirong Qiu, Xiongpeng Wu
Hi Linhua,
kernel test robot noticed the following build warnings:
[auto build test WARNING on linusw-pinctrl/devel]
[also build test WARNING on linusw-pinctrl/for-next linus/master v6.6-rc7 next-20231026]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Linhua-Xu/pinctrl-sprd-Modify-pull-up-parameters/20231027-151737
base: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git devel
patch link: https://lore.kernel.org/r/20231027071426.17724-5-Linhua.xu%40unisoc.com
patch subject: [PATCH V3 4/6] pinctrl: sprd: Increase the range of register values
config: m68k-allyesconfig (https://download.01.org/0day-ci/archive/20231027/202310271959.VUpjvnai-lkp@intel.com/config)
compiler: m68k-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231027/202310271959.VUpjvnai-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202310271959.VUpjvnai-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from drivers/pinctrl/sprd/pinctrl-sprd.c:29:
>> drivers/pinctrl/sprd/pinctrl-sprd.h:21: warning: "BIT_MASK" redefined
21 | #define BIT_MASK GENMASK(7, 0)
|
In file included from include/linux/ratelimit_types.h:5,
from include/linux/printk.h:9,
from include/asm-generic/bug.h:22,
from arch/m68k/include/asm/bug.h:32,
from include/linux/bug.h:5,
from include/linux/thread_info.h:13,
from include/asm-generic/preempt.h:5,
from ./arch/m68k/include/generated/asm/preempt.h:1,
from include/linux/preempt.h:79,
from include/linux/spinlock.h:56,
from include/linux/wait.h:9,
from include/linux/wait_bit.h:8,
from include/linux/fs.h:6,
from include/linux/debugfs.h:15,
from drivers/pinctrl/sprd/pinctrl-sprd.c:7:
include/linux/bits.h:9: note: this is the location of the previous definition
9 | #define BIT_MASK(nr) (UL(1) << ((nr) % BITS_PER_LONG))
|
vim +/BIT_MASK +21 drivers/pinctrl/sprd/pinctrl-sprd.h
18
19 #define NUM_MASK GENMASK(10, 0)
20 #define TYPE_MASK GENMASK(3, 0)
> 21 #define BIT_MASK GENMASK(7, 0)
22 #define WIDTH_MASK GENMASK(3, 0)
23 #define REG_MASK GENMASK(5, 0)
24
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V3 5/6] pinctrl: sprd: Add pinctrl support for UMS512
2023-10-27 7:14 ` [PATCH V3 5/6] pinctrl: sprd: Add pinctrl support for UMS512 Linhua Xu
@ 2023-10-27 11:40 ` Andy Shevchenko
0 siblings, 0 replies; 13+ messages in thread
From: Andy Shevchenko @ 2023-10-27 11:40 UTC (permalink / raw)
To: Linhua Xu
Cc: Linus Walleij, Orson Zhai, Baolin Wang, Chunyan Zhang,
linux-kernel, linux-gpio, lh xu, Zhirong Qiu, Xiongpeng Wu
On Fri, Oct 27, 2023 at 03:14:25PM +0800, Linhua Xu wrote:
> From: Linhua Xu <Linhua.Xu@unisoc.com>
>
> Add the pin control driver for UNISOC UMS512 platform.
...
> +#include <linux/kernel.h>
array_size.h is pending for v6.7-rc1.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V3 6/6] pinctrl: sprd: Add pinctrl support for UMS9621
2023-10-27 7:14 ` [PATCH V3 6/6] pinctrl: sprd: Add pinctrl support for UMS9621 Linhua Xu
@ 2023-10-27 11:42 ` Andy Shevchenko
0 siblings, 0 replies; 13+ messages in thread
From: Andy Shevchenko @ 2023-10-27 11:42 UTC (permalink / raw)
To: Linhua Xu
Cc: Linus Walleij, Orson Zhai, Baolin Wang, Chunyan Zhang,
linux-kernel, linux-gpio, lh xu, Zhirong Qiu, Xiongpeng Wu
On Fri, Oct 27, 2023 at 03:14:26PM +0800, Linhua Xu wrote:
> From: Linhua Xu <Linhua.Xu@unisoc.com>
>
> Add the pin control driver for UNISOC UMS9621 platform.
...
> +#include <linux/kernel.h>
array_size.h
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2023-10-27 11:53 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-10-27 7:14 [PATCH V3 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linhua Xu
2023-10-27 7:14 ` [PATCH V3 1/6] pinctrl: sprd: Modify pull-up parameters Linhua Xu
2023-10-27 11:29 ` Andy Shevchenko
2023-10-27 7:14 ` [PATCH V3 2/6] pinctrl: sprd: Fix the incorrect mask and shift definition Linhua Xu
2023-10-27 11:32 ` Andy Shevchenko
2023-10-27 7:14 ` [PATCH V3 3/6] pinctrl: sprd: Move common and misc offset parameters to private data Linhua Xu
2023-10-27 11:24 ` Andy Shevchenko
2023-10-27 7:14 ` [PATCH V3 4/6] pinctrl: sprd: Increase the range of register values Linhua Xu
2023-10-27 11:39 ` kernel test robot
2023-10-27 7:14 ` [PATCH V3 5/6] pinctrl: sprd: Add pinctrl support for UMS512 Linhua Xu
2023-10-27 11:40 ` Andy Shevchenko
2023-10-27 7:14 ` [PATCH V3 6/6] pinctrl: sprd: Add pinctrl support for UMS9621 Linhua Xu
2023-10-27 11:42 ` Andy Shevchenko
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