* [PATCH v2 0/8] Add T-Head TH1520 SoC pin control
@ 2024-01-03 13:28 Emil Renner Berthing
2024-01-03 13:28 ` [PATCH v2 1/8] dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings Emil Renner Berthing
` (9 more replies)
0 siblings, 10 replies; 25+ messages in thread
From: Emil Renner Berthing @ 2024-01-03 13:28 UTC (permalink / raw)
To: linux-kernel, linux-gpio, devicetree, linux-riscv
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt,
Drew Fustini
This adds a pin control driver for the T-Head TH1520 RISC-V SoC used on
the Lichee Pi 4A and BeagleV Ahead boards and updates the device trees
to make use of it.
It can be easily tested using my th1520 branch at
https://github.com/esmil/linux.git
..which also adds the MMC, PWM, ethernet and USB drivers that have
been posted but are not upstream yet.
Jisheng: I've added this driver to the generic TH1520 entry in
MAINTAINERS like you did with your USB driver. Let me know if that's not
ok and I'll create a separate entry for this driver with me as
maintainer.
Drew: The last patch is purely based on reading the schematics. It'd be
great if you could give it a spin on real hardware.
Changes since v1
- Keep pinmux data for each pin so we can mux by type instead of directly
using the mux index. Eg. use function = "uart" etc. (Linus)
- Drop the strong pull-up property and prevent Linux from combining the strong
pull-up with the regular pull up/down. This also means we can't report such
usage if it set up by earlier stages, but that problem is deferred until we
encounter it (Linus)
- Reference pinmux-node.yaml properly (Rob)
- Specify valid pin names for each group (Rob)
- Enable bus clock (Emil)
- Implement gpio_request_enable() and gpio_set_direction() for automatic
GPIO handling (Emil)
- Drop patch adding gpio-ranges to the gpio-dwapb bindings that is
merged in gpio/for-next. (Emil)
- Patch 6/8 adding GPIO line names for the Lichee Pi 4M module (Emil)
- Various code nits (Andy)
/Emil
Emil Renner Berthing (8):
dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings
pinctrl: Add driver for the T-Head TH1520 SoC
riscv: dts: thead: Add TH1520 pin control nodes
riscv: dts: thead: Add TH1520 GPIO ranges
riscv: dts: thead: Adjust TH1520 GPIO labels
riscv: dts: thead: Add Lichee Pi 4M GPIO line names
riscv: dts: thead: Add TH1520 pinctrl settings for UART0
riscv: dtb: thead: Add BeagleV Ahead LEDs
.../pinctrl/thead,th1520-pinctrl.yaml | 372 ++++++++
MAINTAINERS | 1 +
.../boot/dts/thead/th1520-beaglev-ahead.dts | 87 ++
.../dts/thead/th1520-lichee-module-4a.dtsi | 43 +
.../boot/dts/thead/th1520-lichee-pi-4a.dts | 28 +
arch/riscv/boot/dts/thead/th1520.dtsi | 62 +-
drivers/pinctrl/Kconfig | 9 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-th1520.c | 891 ++++++++++++++++++
9 files changed, 1478 insertions(+), 16 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml
create mode 100644 drivers/pinctrl/pinctrl-th1520.c
--
2.43.0
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH v2 1/8] dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings 2024-01-03 13:28 [PATCH v2 0/8] Add T-Head TH1520 SoC pin control Emil Renner Berthing @ 2024-01-03 13:28 ` Emil Renner Berthing 2024-01-15 17:36 ` Rob Herring 2024-01-03 13:28 ` [PATCH v2 2/8] pinctrl: Add driver for the T-Head TH1520 SoC Emil Renner Berthing ` (8 subsequent siblings) 9 siblings, 1 reply; 25+ messages in thread From: Emil Renner Berthing @ 2024-01-03 13:28 UTC (permalink / raw) To: linux-kernel, linux-gpio, devicetree, linux-riscv Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini Add bindings for the pin controllers on the T-Head TH1520 RISC-V SoC. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> --- .../pinctrl/thead,th1520-pinctrl.yaml | 372 ++++++++++++++++++ 1 file changed, 372 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml new file mode 100644 index 000000000000..d3ad7a7cfdd1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml @@ -0,0 +1,372 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-Head TH1520 SoC pin controller + +maintainers: + - Emil Renner Berthing <emil.renner.berthing@canonical.com> + +description: | + Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC. + + The TH1520 has 3 groups of pads each controlled from different memory ranges. + Confusingly the memory ranges are named + PADCTRL_AOSYS -> PAD Group 1 + PADCTRL1_APSYS -> PAD Group 2 + PADCTRL0_APSYS -> PAD Group 3 + + Each pad can be muxed individually to up to 6 different functions. For most + pads only a few of those 6 configurations are valid though, and a few pads in + group 1 does not support muxing at all. + + Pinconf is fairly regular except for a few pads in group 1 that either can't + be configured or has some special functions. The rest have configurable drive + strength, input enable, schmitt trigger, slew rate, pull-up and pull-down in + addition to a special strong pull up. + + Certain pads in group 1 can be muxed to AUDIO_PA0 - AUDIO_PA30 functions and + are then meant to be used by the audio co-processor. Each such pad can then + be further muxed to either audio GPIO or one of 4 functions such as UART, I2C + and I2S. If the audio pad is muxed to one of the 4 functions then pinconf is + also configured in different registers. All of this is done from a different + AUDIO_IOCTRL memory range and is left to the audio co-processor for now. + +properties: + compatible: + enum: + - thead,th1520-group1-pinctrl + - thead,th1520-group2-pinctrl + - thead,th1520-group3-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +patternProperties: + '-[0-9]+$': + type: object + + additionalProperties: false + + patternProperties: + '-pins$': + type: object + $ref: /schemas/pinctrl/pincfg-node.yaml + + additionalProperties: false + + description: + A pinctrl node should contain at least one subnode describing one + or more pads and their associated pinmux and pinconf settings. + + properties: + pins: + $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/pins + description: List of pads that properties in the node apply to. + + function: + $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/function + enum: [ gpio, pwm, uart, ir, i2c, spi, qspi, sdio, audio, i2s, + gmac0, gmac1, dpu0, dpu1, isp, hdmi, bootsel, debug, + clock, jtag, iso7816, efuse, reset ] + description: The mux function to select for the given pins. + + bias-disable: true + + bias-pull-up: + oneOf: + - type: boolean + description: Enable the regular 48kOhm pull-up + - enum: [ 2100, 48000 ] + description: Enable the strong 2.1kOhm pull-up or regular 48kOhm pull-up + + bias-pull-down: + oneOf: + - type: boolean + - const: 44000 + description: Enable the regular 44kOhm pull-down + + drive-strength: + enum: [ 1, 2, 3, 5, 7, 8, 10, 12, 13, 15, 16, 18, 20, 21, 23, 25 ] + description: Drive strength in mA + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + maximum: 1 + + required: + - pins + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + - if: + properties: + compatible: + const: thead,th1520-group1-pinctrl + then: + patternProperties: + '-[0-9]+$': + patternProperties: + '-pins$': + properties: + pins: + items: + enum: + - OSC_CLK_IN + - OSC_CLK_OUT + - SYS_RST_N + - RTC_CLK_IN + - RTC_CLK_OUT + - TEST_MODE + - DEBUG_MODE + - POR_SEL + - I2C_AON_SCL + - I2C_AON_SDA + - CPU_JTG_TCLK + - CPU_JTG_TMS + - CPU_JTG_TDI + - CPU_JTG_TDO + - CPU_JTG_TRST + - AOGPIO_7 + - AOGPIO_8 + - AOGPIO_9 + - AOGPIO_10 + - AOGPIO_11 + - AOGPIO_12 + - AOGPIO_13 + - AOGPIO_14 + - AOGPIO_15 + - AUDIO_PA0 + - AUDIO_PA1 + - AUDIO_PA2 + - AUDIO_PA3 + - AUDIO_PA4 + - AUDIO_PA5 + - AUDIO_PA6 + - AUDIO_PA7 + - AUDIO_PA8 + - AUDIO_PA9 + - AUDIO_PA10 + - AUDIO_PA11 + - AUDIO_PA12 + - AUDIO_PA13 + - AUDIO_PA14 + - AUDIO_PA15 + - AUDIO_PA16 + - AUDIO_PA17 + - AUDIO_PA27 + - AUDIO_PA28 + - AUDIO_PA29 + - AUDIO_PA30 + - if: + properties: + compatible: + const: thead,th1520-group2-pinctrl + then: + patternProperties: + '-[0-9]+$': + patternProperties: + '-pins$': + properties: + pins: + items: + enum: + - QSPI1_SCLK + - QSPI1_CSN0 + - QSPI1_D0_MOSI + - QSPI1_D1_MISO + - QSPI1_D2_WP + - QSPI1_D3_HOLD + - I2C0_SCL + - I2C0_SDA + - I2C1_SCL + - I2C1_SDA + - UART1_TXD + - UART1_RXD + - UART4_TXD + - UART4_RXD + - UART4_CTSN + - UART4_RTSN + - UART3_TXD + - UART3_RXD + - GPIO0_18 + - GPIO0_19 + - GPIO0_20 + - GPIO0_21 + - GPIO0_22 + - GPIO0_23 + - GPIO0_24 + - GPIO0_25 + - GPIO0_26 + - GPIO0_27 + - GPIO0_28 + - GPIO0_29 + - GPIO0_30 + - GPIO0_31 + - GPIO1_0 + - GPIO1_1 + - GPIO1_2 + - GPIO1_3 + - GPIO1_4 + - GPIO1_5 + - GPIO1_6 + - GPIO1_7 + - GPIO1_8 + - GPIO1_9 + - GPIO1_10 + - GPIO1_11 + - GPIO1_12 + - GPIO1_13 + - GPIO1_14 + - GPIO1_15 + - GPIO1_16 + - CLK_OUT_0 + - CLK_OUT_1 + - CLK_OUT_2 + - CLK_OUT_3 + - GPIO1_21 + - GPIO1_22 + - GPIO1_23 + - GPIO1_24 + - GPIO1_25 + - GPIO1_26 + - GPIO1_27 + - GPIO1_28 + - GPIO1_29 + - GPIO1_30 + - if: + properties: + compatible: + const: thead,th1520-group3-pinctrl + then: + patternProperties: + '-[0-9]+$': + patternProperties: + '-pins$': + properties: + pins: + items: + enum: + - UART0_TXD + - UART0_RXD + - QSPI0_SCLK + - QSPI0_CSN0 + - QSPI0_CSN1 + - QSPI0_D0_MOSI + - QSPI0_D1_MISO + - QSPI0_D2_WP + - QSPI1_D3_HOLD + - I2C2_SCL + - I2C2_SDA + - I2C3_SCL + - I2C3_SDA + - GPIO2_13 + - SPI_SCLK + - SPI_CSN + - SPI_MOSI + - SPI_MISO + - GPIO2_18 + - GPIO2_19 + - GPIO2_20 + - GPIO2_21 + - GPIO2_22 + - GPIO2_23 + - GPIO2_24 + - GPIO2_25 + - SDIO0_WPRTN + - SDIO0_DETN + - SDIO1_WPRTN + - SDIO1_DETN + - GPIO2_30 + - GPIO2_31 + - GPIO3_0 + - GPIO3_1 + - GPIO3_2 + - GPIO3_3 + - HDMI_SCL + - HDMI_SDA + - HDMI_CEC + - GMAC0_TX_CLK + - GMAC0_RX_CLK + - GMAC0_TXEN + - GMAC0_TXD0 + - GMAC0_TXD1 + - GMAC0_TXD2 + - GMAC0_TXD3 + - GMAC0_RXDV + - GMAC0_RXD0 + - GMAC0_RXD1 + - GMAC0_RXD2 + - GMAC0_RXD3 + - GMAC0_MDC + - GMAC0_MDIO + - GMAC0_COL + - GMAC0_CRS + +examples: + - | + padctrl0_apsys: pinctrl@ec007000 { + compatible = "thead,th1520-group3-pinctrl"; + reg = <0xec007000 0x1000>; + clocks = <&apb_clk>; + + uart0_pins: uart0-0 { + tx-pins { + pins = "UART0_TXD"; + function = "uart"; + bias-disable; + drive-strength = <3>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pins = "UART0_RXD"; + function = "uart"; + bias-disable; + drive-strength = <1>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + }; + + padctrl1_apsys: pinctrl@e7f3c000 { + compatible = "thead,th1520-group2-pinctrl"; + reg = <0xe7f3c000 0x1000>; + clocks = <&apb_clk>; + + i2c5_pins: i2c5-0 { + i2c-pins { + pins = "QSPI1_CSN0", /* I2C5_SCL */ + "QSPI1_D0_MOSI"; /* I2C5_SDA */ + function = "i2c"; + bias-pull-up = <2100>; + drive-strength = <7>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + }; -- 2.43.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v2 1/8] dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings 2024-01-03 13:28 ` [PATCH v2 1/8] dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings Emil Renner Berthing @ 2024-01-15 17:36 ` Rob Herring 2024-05-17 12:48 ` Emil Renner Berthing 0 siblings, 1 reply; 25+ messages in thread From: Rob Herring @ 2024-01-15 17:36 UTC (permalink / raw) To: Emil Renner Berthing Cc: linux-kernel, linux-gpio, devicetree, linux-riscv, Linus Walleij, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini On Wed, Jan 03, 2024 at 02:28:38PM +0100, Emil Renner Berthing wrote: > Add bindings for the pin controllers on the T-Head TH1520 RISC-V SoC. > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > --- > .../pinctrl/thead,th1520-pinctrl.yaml | 372 ++++++++++++++++++ > 1 file changed, 372 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml > new file mode 100644 > index 000000000000..d3ad7a7cfdd1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml > @@ -0,0 +1,372 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: T-Head TH1520 SoC pin controller > + > +maintainers: > + - Emil Renner Berthing <emil.renner.berthing@canonical.com> > + > +description: | > + Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC. > + > + The TH1520 has 3 groups of pads each controlled from different memory ranges. > + Confusingly the memory ranges are named > + PADCTRL_AOSYS -> PAD Group 1 > + PADCTRL1_APSYS -> PAD Group 2 > + PADCTRL0_APSYS -> PAD Group 3 > + > + Each pad can be muxed individually to up to 6 different functions. For most > + pads only a few of those 6 configurations are valid though, and a few pads in > + group 1 does not support muxing at all. > + > + Pinconf is fairly regular except for a few pads in group 1 that either can't > + be configured or has some special functions. The rest have configurable drive > + strength, input enable, schmitt trigger, slew rate, pull-up and pull-down in > + addition to a special strong pull up. > + > + Certain pads in group 1 can be muxed to AUDIO_PA0 - AUDIO_PA30 functions and > + are then meant to be used by the audio co-processor. Each such pad can then > + be further muxed to either audio GPIO or one of 4 functions such as UART, I2C > + and I2S. If the audio pad is muxed to one of the 4 functions then pinconf is > + also configured in different registers. All of this is done from a different > + AUDIO_IOCTRL memory range and is left to the audio co-processor for now. It is still not clear to me if each instance is a different programming model or the same with just different connections. The latter should be the same compatible string. That needs to be answered in *this* patch, not a reply. > + > +properties: > + compatible: > + enum: > + - thead,th1520-group1-pinctrl > + - thead,th1520-group2-pinctrl > + - thead,th1520-group3-pinctrl > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > +patternProperties: > + '-[0-9]+$': > + type: object > + > + additionalProperties: false > + > + patternProperties: > + '-pins$': > + type: object > + $ref: /schemas/pinctrl/pincfg-node.yaml > + > + additionalProperties: false > + > + description: > + A pinctrl node should contain at least one subnode describing one > + or more pads and their associated pinmux and pinconf settings. > + > + properties: > + pins: > + $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/pins > + description: List of pads that properties in the node apply to. > + > + function: > + $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/function > + enum: [ gpio, pwm, uart, ir, i2c, spi, qspi, sdio, audio, i2s, > + gmac0, gmac1, dpu0, dpu1, isp, hdmi, bootsel, debug, > + clock, jtag, iso7816, efuse, reset ] > + description: The mux function to select for the given pins. > + > + bias-disable: true > + > + bias-pull-up: > + oneOf: > + - type: boolean > + description: Enable the regular 48kOhm pull-up > + - enum: [ 2100, 48000 ] > + description: Enable the strong 2.1kOhm pull-up or regular 48kOhm pull-up > + > + bias-pull-down: > + oneOf: > + - type: boolean > + - const: 44000 > + description: Enable the regular 44kOhm pull-down > + > + drive-strength: > + enum: [ 1, 2, 3, 5, 7, 8, 10, 12, 13, 15, 16, 18, 20, 21, 23, 25 ] > + description: Drive strength in mA > + > + input-enable: true > + > + input-disable: true > + > + input-schmitt-enable: true > + > + input-schmitt-disable: true > + > + slew-rate: > + maximum: 1 > + > + required: > + - pins > + > +required: > + - compatible > + - reg > + - clocks > + > +additionalProperties: false > + > +allOf: > + - $ref: pinctrl.yaml# > + - if: > + properties: > + compatible: > + const: thead,th1520-group1-pinctrl > + then: > + patternProperties: > + '-[0-9]+$': > + patternProperties: > + '-pins$': > + properties: > + pins: > + items: > + enum: > + - OSC_CLK_IN > + - OSC_CLK_OUT > + - SYS_RST_N > + - RTC_CLK_IN > + - RTC_CLK_OUT > + - TEST_MODE > + - DEBUG_MODE > + - POR_SEL > + - I2C_AON_SCL > + - I2C_AON_SDA > + - CPU_JTG_TCLK > + - CPU_JTG_TMS > + - CPU_JTG_TDI > + - CPU_JTG_TDO > + - CPU_JTG_TRST > + - AOGPIO_7 > + - AOGPIO_8 > + - AOGPIO_9 > + - AOGPIO_10 > + - AOGPIO_11 > + - AOGPIO_12 > + - AOGPIO_13 > + - AOGPIO_14 > + - AOGPIO_15 > + - AUDIO_PA0 > + - AUDIO_PA1 > + - AUDIO_PA2 > + - AUDIO_PA3 > + - AUDIO_PA4 > + - AUDIO_PA5 > + - AUDIO_PA6 > + - AUDIO_PA7 > + - AUDIO_PA8 > + - AUDIO_PA9 > + - AUDIO_PA10 > + - AUDIO_PA11 > + - AUDIO_PA12 > + - AUDIO_PA13 > + - AUDIO_PA14 > + - AUDIO_PA15 > + - AUDIO_PA16 > + - AUDIO_PA17 > + - AUDIO_PA27 > + - AUDIO_PA28 > + - AUDIO_PA29 > + - AUDIO_PA30 > + - if: > + properties: > + compatible: > + const: thead,th1520-group2-pinctrl > + then: > + patternProperties: > + '-[0-9]+$': > + patternProperties: > + '-pins$': > + properties: > + pins: > + items: > + enum: > + - QSPI1_SCLK > + - QSPI1_CSN0 > + - QSPI1_D0_MOSI > + - QSPI1_D1_MISO > + - QSPI1_D2_WP > + - QSPI1_D3_HOLD > + - I2C0_SCL > + - I2C0_SDA > + - I2C1_SCL > + - I2C1_SDA > + - UART1_TXD > + - UART1_RXD > + - UART4_TXD > + - UART4_RXD > + - UART4_CTSN > + - UART4_RTSN > + - UART3_TXD > + - UART3_RXD > + - GPIO0_18 > + - GPIO0_19 > + - GPIO0_20 > + - GPIO0_21 > + - GPIO0_22 > + - GPIO0_23 > + - GPIO0_24 > + - GPIO0_25 > + - GPIO0_26 > + - GPIO0_27 > + - GPIO0_28 > + - GPIO0_29 > + - GPIO0_30 > + - GPIO0_31 > + - GPIO1_0 > + - GPIO1_1 > + - GPIO1_2 > + - GPIO1_3 > + - GPIO1_4 > + - GPIO1_5 > + - GPIO1_6 > + - GPIO1_7 > + - GPIO1_8 > + - GPIO1_9 > + - GPIO1_10 > + - GPIO1_11 > + - GPIO1_12 > + - GPIO1_13 > + - GPIO1_14 > + - GPIO1_15 > + - GPIO1_16 > + - CLK_OUT_0 > + - CLK_OUT_1 > + - CLK_OUT_2 > + - CLK_OUT_3 > + - GPIO1_21 > + - GPIO1_22 > + - GPIO1_23 > + - GPIO1_24 > + - GPIO1_25 > + - GPIO1_26 > + - GPIO1_27 > + - GPIO1_28 > + - GPIO1_29 > + - GPIO1_30 > + - if: > + properties: > + compatible: > + const: thead,th1520-group3-pinctrl > + then: > + patternProperties: > + '-[0-9]+$': > + patternProperties: > + '-pins$': > + properties: > + pins: > + items: > + enum: > + - UART0_TXD > + - UART0_RXD > + - QSPI0_SCLK > + - QSPI0_CSN0 > + - QSPI0_CSN1 > + - QSPI0_D0_MOSI > + - QSPI0_D1_MISO > + - QSPI0_D2_WP > + - QSPI1_D3_HOLD > + - I2C2_SCL > + - I2C2_SDA > + - I2C3_SCL > + - I2C3_SDA > + - GPIO2_13 > + - SPI_SCLK > + - SPI_CSN > + - SPI_MOSI > + - SPI_MISO > + - GPIO2_18 > + - GPIO2_19 > + - GPIO2_20 > + - GPIO2_21 > + - GPIO2_22 > + - GPIO2_23 > + - GPIO2_24 > + - GPIO2_25 > + - SDIO0_WPRTN > + - SDIO0_DETN > + - SDIO1_WPRTN > + - SDIO1_DETN > + - GPIO2_30 > + - GPIO2_31 > + - GPIO3_0 > + - GPIO3_1 > + - GPIO3_2 > + - GPIO3_3 > + - HDMI_SCL > + - HDMI_SDA > + - HDMI_CEC > + - GMAC0_TX_CLK > + - GMAC0_RX_CLK > + - GMAC0_TXEN > + - GMAC0_TXD0 > + - GMAC0_TXD1 > + - GMAC0_TXD2 > + - GMAC0_TXD3 > + - GMAC0_RXDV > + - GMAC0_RXD0 > + - GMAC0_RXD1 > + - GMAC0_RXD2 > + - GMAC0_RXD3 > + - GMAC0_MDC > + - GMAC0_MDIO > + - GMAC0_COL > + - GMAC0_CRS > + > +examples: > + - | > + padctrl0_apsys: pinctrl@ec007000 { > + compatible = "thead,th1520-group3-pinctrl"; > + reg = <0xec007000 0x1000>; > + clocks = <&apb_clk>; > + > + uart0_pins: uart0-0 { > + tx-pins { > + pins = "UART0_TXD"; > + function = "uart"; > + bias-disable; > + drive-strength = <3>; > + input-disable; > + input-schmitt-disable; > + slew-rate = <0>; > + }; > + > + rx-pins { > + pins = "UART0_RXD"; > + function = "uart"; > + bias-disable; > + drive-strength = <1>; > + input-enable; > + input-schmitt-enable; > + slew-rate = <0>; > + }; > + }; > + }; > + > + padctrl1_apsys: pinctrl@e7f3c000 { > + compatible = "thead,th1520-group2-pinctrl"; > + reg = <0xe7f3c000 0x1000>; > + clocks = <&apb_clk>; > + > + i2c5_pins: i2c5-0 { > + i2c-pins { > + pins = "QSPI1_CSN0", /* I2C5_SCL */ > + "QSPI1_D0_MOSI"; /* I2C5_SDA */ > + function = "i2c"; > + bias-pull-up = <2100>; > + drive-strength = <7>; > + input-enable; > + input-schmitt-enable; > + slew-rate = <0>; > + }; > + }; > + }; > -- > 2.43.0 > ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 1/8] dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings 2024-01-15 17:36 ` Rob Herring @ 2024-05-17 12:48 ` Emil Renner Berthing 2024-07-01 12:33 ` Emil Renner Berthing 2024-07-03 13:53 ` Rob Herring 0 siblings, 2 replies; 25+ messages in thread From: Emil Renner Berthing @ 2024-05-17 12:48 UTC (permalink / raw) To: Rob Herring, Emil Renner Berthing Cc: linux-kernel, linux-gpio, devicetree, linux-riscv, Linus Walleij, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini Rob Herring wrote: > On Wed, Jan 03, 2024 at 02:28:38PM +0100, Emil Renner Berthing wrote: > > Add bindings for the pin controllers on the T-Head TH1520 RISC-V SoC. > > > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > --- > > .../pinctrl/thead,th1520-pinctrl.yaml | 372 ++++++++++++++++++ > > 1 file changed, 372 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml > > new file mode 100644 > > index 000000000000..d3ad7a7cfdd1 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml > > @@ -0,0 +1,372 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: T-Head TH1520 SoC pin controller > > + > > +maintainers: > > + - Emil Renner Berthing <emil.renner.berthing@canonical.com> > > + > > +description: | > > + Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC. > > + > > + The TH1520 has 3 groups of pads each controlled from different memory ranges. > > + Confusingly the memory ranges are named > > + PADCTRL_AOSYS -> PAD Group 1 > > + PADCTRL1_APSYS -> PAD Group 2 > > + PADCTRL0_APSYS -> PAD Group 3 > > + > > + Each pad can be muxed individually to up to 6 different functions. For most > > + pads only a few of those 6 configurations are valid though, and a few pads in > > + group 1 does not support muxing at all. > > + > > + Pinconf is fairly regular except for a few pads in group 1 that either can't > > + be configured or has some special functions. The rest have configurable drive > > + strength, input enable, schmitt trigger, slew rate, pull-up and pull-down in > > + addition to a special strong pull up. > > + > > + Certain pads in group 1 can be muxed to AUDIO_PA0 - AUDIO_PA30 functions and > > + are then meant to be used by the audio co-processor. Each such pad can then > > + be further muxed to either audio GPIO or one of 4 functions such as UART, I2C > > + and I2S. If the audio pad is muxed to one of the 4 functions then pinconf is > > + also configured in different registers. All of this is done from a different > > + AUDIO_IOCTRL memory range and is left to the audio co-processor for now. > > It is still not clear to me if each instance is a different programming > model or the same with just different connections. The latter should > be the same compatible string. That needs to be answered in *this* > patch, not a reply. Hi Rob, Sorry for the late response. I honestly don't know exactly what you mean by differenty programming models and what the difference is, so I'll need a bit of help with what you want me to write here. Any driver for the TH1520 SoC (not just Linux) would need some way to discern between the 3 pin controllers so they know how many pins to control and what pinmux settings are valid. Basically they'd need the data in the three th1520_group{1,2,3}_pins arrays in the driver and a way to know which of them to use. https://lore.kernel.org/linux-riscv/20240103132852.298964-3-emil.renner.berthing@canonical.com/ Another solution would be to just have one compatible value, and then let the driver figure out which of the 3 pin controllers it's probing from the base physical memory address. That would work fine. A third solution would be to encode the data in those three arrays into the device tree, but I thought we didn't want to encode register information in device trees. /Emil ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 1/8] dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings 2024-05-17 12:48 ` Emil Renner Berthing @ 2024-07-01 12:33 ` Emil Renner Berthing 2024-07-03 13:53 ` Rob Herring 1 sibling, 0 replies; 25+ messages in thread From: Emil Renner Berthing @ 2024-07-01 12:33 UTC (permalink / raw) To: Rob Herring Cc: linux-kernel, linux-gpio, devicetree, linux-riscv, Linus Walleij, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini Emil Renner Berthing wrote: > Rob Herring wrote: > > On Wed, Jan 03, 2024 at 02:28:38PM +0100, Emil Renner Berthing wrote: > > > Add bindings for the pin controllers on the T-Head TH1520 RISC-V SoC. > > > > > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > > --- > > > .../pinctrl/thead,th1520-pinctrl.yaml | 372 ++++++++++++++++++ > > > 1 file changed, 372 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml > > > new file mode 100644 > > > index 000000000000..d3ad7a7cfdd1 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml > > > @@ -0,0 +1,372 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: T-Head TH1520 SoC pin controller > > > + > > > +maintainers: > > > + - Emil Renner Berthing <emil.renner.berthing@canonical.com> > > > + > > > +description: | > > > + Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC. > > > + > > > + The TH1520 has 3 groups of pads each controlled from different memory ranges. > > > + Confusingly the memory ranges are named > > > + PADCTRL_AOSYS -> PAD Group 1 > > > + PADCTRL1_APSYS -> PAD Group 2 > > > + PADCTRL0_APSYS -> PAD Group 3 > > > + > > > + Each pad can be muxed individually to up to 6 different functions. For most > > > + pads only a few of those 6 configurations are valid though, and a few pads in > > > + group 1 does not support muxing at all. > > > + > > > + Pinconf is fairly regular except for a few pads in group 1 that either can't > > > + be configured or has some special functions. The rest have configurable drive > > > + strength, input enable, schmitt trigger, slew rate, pull-up and pull-down in > > > + addition to a special strong pull up. > > > + > > > + Certain pads in group 1 can be muxed to AUDIO_PA0 - AUDIO_PA30 functions and > > > + are then meant to be used by the audio co-processor. Each such pad can then > > > + be further muxed to either audio GPIO or one of 4 functions such as UART, I2C > > > + and I2S. If the audio pad is muxed to one of the 4 functions then pinconf is > > > + also configured in different registers. All of this is done from a different > > > + AUDIO_IOCTRL memory range and is left to the audio co-processor for now. > > > > It is still not clear to me if each instance is a different programming > > model or the same with just different connections. The latter should > > be the same compatible string. That needs to be answered in *this* > > patch, not a reply. > > Hi Rob, > > Sorry for the late response. I honestly don't know exactly what you mean by > differenty programming models and what the difference is, so I'll need a bit of > help with what you want me to write here. > > Any driver for the TH1520 SoC (not just Linux) would need some way to discern > between the 3 pin controllers so they know how many pins to control and what > pinmux settings are valid. Basically they'd need the data in the three > th1520_group{1,2,3}_pins arrays in the driver and a way to know which of them > to use. > > https://lore.kernel.org/linux-riscv/20240103132852.298964-3-emil.renner.berthing@canonical.com/ > > Another solution would be to just have one compatible value, and then let the > driver figure out which of the 3 pin controllers it's probing from the base > physical memory address. That would work fine. > > A third solution would be to encode the data in those three arrays into the > device tree, but I thought we didn't want to encode register information in > device trees. Hi Rob, Any chance you could give me some advice on this, or should I just send it again as is? Other patchsets depend on this. Eg.: https://lore.kernel.org/all/20240618-i2c-th1520-v3-0-3042590a16b1@bootlin.com/ /Emil ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 1/8] dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings 2024-05-17 12:48 ` Emil Renner Berthing 2024-07-01 12:33 ` Emil Renner Berthing @ 2024-07-03 13:53 ` Rob Herring 2024-07-03 19:19 ` Emil Renner Berthing 1 sibling, 1 reply; 25+ messages in thread From: Rob Herring @ 2024-07-03 13:53 UTC (permalink / raw) To: Emil Renner Berthing Cc: linux-kernel, linux-gpio, devicetree, linux-riscv, Linus Walleij, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini On Fri, May 17, 2024 at 07:48:17AM -0500, Emil Renner Berthing wrote: > Rob Herring wrote: > > On Wed, Jan 03, 2024 at 02:28:38PM +0100, Emil Renner Berthing wrote: > > > Add bindings for the pin controllers on the T-Head TH1520 RISC-V SoC. > > > > > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > > --- > > > .../pinctrl/thead,th1520-pinctrl.yaml | 372 ++++++++++++++++++ > > > 1 file changed, 372 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml > > > new file mode 100644 > > > index 000000000000..d3ad7a7cfdd1 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml > > > @@ -0,0 +1,372 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: T-Head TH1520 SoC pin controller > > > + > > > +maintainers: > > > + - Emil Renner Berthing <emil.renner.berthing@canonical.com> > > > + > > > +description: | > > > + Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC. > > > + > > > + The TH1520 has 3 groups of pads each controlled from different memory ranges. > > > + Confusingly the memory ranges are named > > > + PADCTRL_AOSYS -> PAD Group 1 > > > + PADCTRL1_APSYS -> PAD Group 2 > > > + PADCTRL0_APSYS -> PAD Group 3 > > > + > > > + Each pad can be muxed individually to up to 6 different functions. For most > > > + pads only a few of those 6 configurations are valid though, and a few pads in > > > + group 1 does not support muxing at all. > > > + > > > + Pinconf is fairly regular except for a few pads in group 1 that either can't > > > + be configured or has some special functions. The rest have configurable drive > > > + strength, input enable, schmitt trigger, slew rate, pull-up and pull-down in > > > + addition to a special strong pull up. > > > + > > > + Certain pads in group 1 can be muxed to AUDIO_PA0 - AUDIO_PA30 functions and > > > + are then meant to be used by the audio co-processor. Each such pad can then > > > + be further muxed to either audio GPIO or one of 4 functions such as UART, I2C > > > + and I2S. If the audio pad is muxed to one of the 4 functions then pinconf is > > > + also configured in different registers. All of this is done from a different > > > + AUDIO_IOCTRL memory range and is left to the audio co-processor for now. > > > > It is still not clear to me if each instance is a different programming > > model or the same with just different connections. The latter should > > be the same compatible string. That needs to be answered in *this* > > patch, not a reply. > > Hi Rob, > > Sorry for the late response. I honestly don't know exactly what you mean by > differenty programming models and what the difference is, so I'll need a bit of > help with what you want me to write here. Is the register interface of each instance the same? Looks like it is from the driver. So normally that's 3 instances of the same compatible. > Any driver for the TH1520 SoC (not just Linux) would need some way to discern > between the 3 pin controllers so they know how many pins to control and what > pinmux settings are valid. Basically they'd need the data in the three > th1520_group{1,2,3}_pins arrays in the driver and a way to know which of them > to use. > > https://lore.kernel.org/linux-riscv/20240103132852.298964-3-emil.renner.berthing@canonical.com/ Why do you need to know how many pins? The DT says configure a pin and you just configure it. It's not the kernel's job to validate that the DT is correct. Aren't the pin names globally unique? So you just look up the pin name across all the arrays. Or you can just look up one pin from each instance to find which th1520_groupN_pins array goes with the instance. Or just have 1 array. Rob ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 1/8] dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings 2024-07-03 13:53 ` Rob Herring @ 2024-07-03 19:19 ` Emil Renner Berthing 0 siblings, 0 replies; 25+ messages in thread From: Emil Renner Berthing @ 2024-07-03 19:19 UTC (permalink / raw) To: Rob Herring, Emil Renner Berthing Cc: linux-kernel, linux-gpio, devicetree, linux-riscv, Linus Walleij, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini Rob Herring wrote: > On Fri, May 17, 2024 at 07:48:17AM -0500, Emil Renner Berthing wrote: > > Rob Herring wrote: > > > On Wed, Jan 03, 2024 at 02:28:38PM +0100, Emil Renner Berthing wrote: > > > > Add bindings for the pin controllers on the T-Head TH1520 RISC-V SoC. > > > > > > > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > > > --- > > > > .../pinctrl/thead,th1520-pinctrl.yaml | 372 ++++++++++++++++++ > > > > 1 file changed, 372 insertions(+) > > > > create mode 100644 Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml > > > > > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml > > > > new file mode 100644 > > > > index 000000000000..d3ad7a7cfdd1 > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml > > > > @@ -0,0 +1,372 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > +%YAML 1.2 > > > > +--- > > > > +$id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: T-Head TH1520 SoC pin controller > > > > + > > > > +maintainers: > > > > + - Emil Renner Berthing <emil.renner.berthing@canonical.com> > > > > + > > > > +description: | > > > > + Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC. > > > > + > > > > + The TH1520 has 3 groups of pads each controlled from different memory ranges. > > > > + Confusingly the memory ranges are named > > > > + PADCTRL_AOSYS -> PAD Group 1 > > > > + PADCTRL1_APSYS -> PAD Group 2 > > > > + PADCTRL0_APSYS -> PAD Group 3 > > > > + > > > > + Each pad can be muxed individually to up to 6 different functions. For most > > > > + pads only a few of those 6 configurations are valid though, and a few pads in > > > > + group 1 does not support muxing at all. > > > > + > > > > + Pinconf is fairly regular except for a few pads in group 1 that either can't > > > > + be configured or has some special functions. The rest have configurable drive > > > > + strength, input enable, schmitt trigger, slew rate, pull-up and pull-down in > > > > + addition to a special strong pull up. > > > > + > > > > + Certain pads in group 1 can be muxed to AUDIO_PA0 - AUDIO_PA30 functions and > > > > + are then meant to be used by the audio co-processor. Each such pad can then > > > > + be further muxed to either audio GPIO or one of 4 functions such as UART, I2C > > > > + and I2S. If the audio pad is muxed to one of the 4 functions then pinconf is > > > > + also configured in different registers. All of this is done from a different > > > > + AUDIO_IOCTRL memory range and is left to the audio co-processor for now. > > > > > > It is still not clear to me if each instance is a different programming > > > model or the same with just different connections. The latter should > > > be the same compatible string. That needs to be answered in *this* > > > patch, not a reply. > > > > Hi Rob, > > > > Sorry for the late response. I honestly don't know exactly what you mean by > > differenty programming models and what the difference is, so I'll need a bit of > > help with what you want me to write here. > > Is the register interface of each instance the same? Looks like it is > from the driver. So normally that's 3 instances of the same compatible. > > > Any driver for the TH1520 SoC (not just Linux) would need some way to discern > > between the 3 pin controllers so they know how many pins to control and what > > pinmux settings are valid. Basically they'd need the data in the three > > th1520_group{1,2,3}_pins arrays in the driver and a way to know which of them > > to use. > > > > https://lore.kernel.org/linux-riscv/20240103132852.298964-3-emil.renner.berthing@canonical.com/ > > Why do you need to know how many pins? The DT says configure a pin and > you just configure it. It's not the kernel's job to validate that the DT > is correct. > > Aren't the pin names globally unique? So you just look up the pin name > across all the arrays. Or you can just look up one pin from each > instance to find which th1520_groupN_pins array goes with the instance. > Or just have 1 array. Just to be clear, do you mean to add just one node for all 3 instances like this? padctrl: pinctrl@ffe7f3c000 { compatible = "thead,th1520-pinctrl"; reg = <0xff 0xe7f3c000 0x0 0x1000>, <0xff 0xec007000 0x0 0x1000>, <0xff 0xfff4a000 0x0 0x2000>; reg-names = "group2", "group3", "group1"; clocks = <&apb_clk>, <&apb_clk>, <&aonsys_clk>; clock-names = "group2", "group3", "group1"; }; That will work since we can then register all pins at the same time. But I can't see how it will work when keeping the 3 different nodes since each instance needs to register the pins they control at probe time. So there will need to be some way to tell the 3 different nodes apart. /Emil ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 2/8] pinctrl: Add driver for the T-Head TH1520 SoC 2024-01-03 13:28 [PATCH v2 0/8] Add T-Head TH1520 SoC pin control Emil Renner Berthing 2024-01-03 13:28 ` [PATCH v2 1/8] dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings Emil Renner Berthing @ 2024-01-03 13:28 ` Emil Renner Berthing 2024-01-27 23:02 ` Linus Walleij 2024-05-11 6:06 ` Andy Shevchenko 2024-01-03 13:28 ` [PATCH v2 3/8] riscv: dts: thead: Add TH1520 pin control nodes Emil Renner Berthing ` (7 subsequent siblings) 9 siblings, 2 replies; 25+ messages in thread From: Emil Renner Berthing @ 2024-01-03 13:28 UTC (permalink / raw) To: linux-kernel, linux-gpio, devicetree, linux-riscv Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini Add pinctrl driver for the T-Head TH1520 RISC-V SoC. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> --- MAINTAINERS | 1 + drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-th1520.c | 891 +++++++++++++++++++++++++++++++ 4 files changed, 902 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-th1520.c diff --git a/MAINTAINERS b/MAINTAINERS index f5c2450fa4ec..bcd4a241b45f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18626,6 +18626,7 @@ M: Fu Wei <wefu@redhat.com> L: linux-riscv@lists.infradead.org S: Maintained F: arch/riscv/boot/dts/thead/ +F: drivers/pinctrl/pinctrl-th1520.c RNBD BLOCK DRIVERS M: Md. Haris Iqbal <haris.iqbal@ionos.com> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 1de4e1edede0..44426fe0f848 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -469,6 +469,15 @@ config PINCTRL_TB10X depends on OF && ARC_PLAT_TB10X select GPIOLIB +config PINCTRL_TH1520 + tristate "Pinctrl driver for the T-Head TH1520 SoC" + depends on ARCH_THEAD || COMPILE_TEST + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + select PINMUX + help + This selects the pinctrl driver for T-Head TH1520 RISC-V SoC. + config PINCTRL_ZYNQ bool "Pinctrl driver for Xilinx Zynq" depends on ARCH_ZYNQ diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 37575deb7a69..74350d667add 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o +obj-$(CONFIG_PINCTRL_TH1520) += pinctrl-th1520.o obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o diff --git a/drivers/pinctrl/pinctrl-th1520.c b/drivers/pinctrl/pinctrl-th1520.c new file mode 100644 index 000000000000..7c533438f2fd --- /dev/null +++ b/drivers/pinctrl/pinctrl-th1520.c @@ -0,0 +1,891 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Pinctrl driver for the T-Head TH1520 SoC + * + * Copyright (C) 2023 Emil Renner Berthing <emil.renner.berthing@canonical.com> + */ + +#include <linux/array_size.h> +#include <linux/bits.h> +#include <linux/cleanup.h> +#include <linux/clk.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/spinlock.h> + +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include "core.h" +#include "pinmux.h" +#include "pinconf.h" + +#define TH1520_PADCFG_IE BIT(9) +#define TH1520_PADCFG_SL BIT(8) +#define TH1520_PADCFG_ST BIT(7) +#define TH1520_PADCFG_SPU BIT(6) +#define TH1520_PADCFG_PS BIT(5) +#define TH1520_PADCFG_PE BIT(4) +#define TH1520_PADCFG_BIAS (TH1520_PADCFG_SPU | TH1520_PADCFG_PS | TH1520_PADCFG_PE) +#define TH1520_PADCFG_DS GENMASK(3, 0) + +#define TH1520_PULL_DOWN_OHM 44000 /* typ. 44kOhm */ +#define TH1520_PULL_UP_OHM 48000 /* typ. 48kOhm */ +#define TH1520_PULL_STRONG_OHM 2100 /* typ. 2.1kOhm */ + +#define TH1520_PAD_NO_PADCFG BIT(30) +#define TH1520_PAD_MUXDATA GENMASK(29, 0) + +struct th1520_pad_group { + const char *name; + const struct pinctrl_pin_desc *pins; + unsigned int npins; +}; + +struct th1520_pinctrl { + struct pinctrl_desc desc; + struct mutex mutex; /* serialize adding functions */ + raw_spinlock_t lock; /* serialize register access */ + void __iomem *base; + struct pinctrl_dev *pctl; +}; + +static void __iomem *th1520_padcfg(struct th1520_pinctrl *thp, + unsigned int pin) +{ + return thp->base + 4 * (pin / 2); +} + +static unsigned int th1520_padcfg_shift(unsigned int pin) +{ + return 16 * (pin & BIT(0)); +} + +static void __iomem *th1520_muxcfg(struct th1520_pinctrl *thp, + unsigned int pin) +{ + return thp->base + 0x400 + 4 * (pin / 8); +} + +static unsigned int th1520_muxcfg_shift(unsigned int pin) +{ + return 4 * (pin & GENMASK(2, 0)); +} + +enum th1520_muxtype { + TH1520_MUX_____, + TH1520_MUX_GPIO, + TH1520_MUX_PWM, + TH1520_MUX_UART, + TH1520_MUX_IR, + TH1520_MUX_I2C, + TH1520_MUX_SPI, + TH1520_MUX_QSPI, + TH1520_MUX_SDIO, + TH1520_MUX_AUD, + TH1520_MUX_I2S, + TH1520_MUX_MAC0, + TH1520_MUX_MAC1, + TH1520_MUX_DPU0, + TH1520_MUX_DPU1, + TH1520_MUX_ISP, + TH1520_MUX_HDMI, + TH1520_MUX_BSEL, + TH1520_MUX_DBG, + TH1520_MUX_CLK, + TH1520_MUX_JTAG, + TH1520_MUX_ISO, + TH1520_MUX_FUSE, + TH1520_MUX_RST, +}; + +static const char *const th1520_muxtype_string[] = { + [TH1520_MUX_GPIO] = "gpio", + [TH1520_MUX_PWM] = "pwm", + [TH1520_MUX_UART] = "uart", + [TH1520_MUX_IR] = "ir", + [TH1520_MUX_I2C] = "i2c", + [TH1520_MUX_SPI] = "spi", + [TH1520_MUX_QSPI] = "qspi", + [TH1520_MUX_SDIO] = "sdio", + [TH1520_MUX_AUD] = "audio", + [TH1520_MUX_I2S] = "i2s", + [TH1520_MUX_MAC0] = "gmac0", + [TH1520_MUX_MAC1] = "gmac1", + [TH1520_MUX_DPU0] = "dpu0", + [TH1520_MUX_DPU1] = "dpu1", + [TH1520_MUX_ISP] = "isp", + [TH1520_MUX_HDMI] = "hdmi", + [TH1520_MUX_BSEL] = "bootsel", + [TH1520_MUX_DBG] = "debug", + [TH1520_MUX_CLK] = "clock", + [TH1520_MUX_JTAG] = "jtag", + [TH1520_MUX_ISO] = "iso7816", + [TH1520_MUX_FUSE] = "efuse", + [TH1520_MUX_RST] = "reset", +}; + +static enum th1520_muxtype th1520_muxtype_get(const char *str) +{ + enum th1520_muxtype mt; + + for (mt = TH1520_MUX_GPIO; mt < ARRAY_SIZE(th1520_muxtype_string); mt++) { + if (!strcmp(str, th1520_muxtype_string[mt])) + return mt; + } + return TH1520_MUX_____; +} + +#define TH1520_PAD(_nr, _name, m0, m1, m2, m3, m4, m5, _flags) \ + { .number = _nr, .name = #_name, .drv_data = (void *)((_flags) | \ + (TH1520_MUX_##m0 << 0) | (TH1520_MUX_##m1 << 5) | (TH1520_MUX_##m2 << 10) | \ + (TH1520_MUX_##m3 << 15) | (TH1520_MUX_##m4 << 20) | (TH1520_MUX_##m5 << 25)) } + +static const struct pinctrl_pin_desc th1520_group1_pins[] = { + TH1520_PAD(0, OSC_CLK_IN, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG), + TH1520_PAD(1, OSC_CLK_OUT, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG), + TH1520_PAD(2, SYS_RST_N, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG), + TH1520_PAD(3, RTC_CLK_IN, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG), + TH1520_PAD(4, RTC_CLK_OUT, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG), + /* skip number 5 so we can calculate register offsets and shifts from the pin number */ + TH1520_PAD(6, TEST_MODE, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG), + TH1520_PAD(7, DEBUG_MODE, DBG, ____, ____, GPIO, ____, ____, TH1520_PAD_NO_PADCFG), + TH1520_PAD(8, POR_SEL, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG), + TH1520_PAD(9, I2C_AON_SCL, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(10, I2C_AON_SDA, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(11, CPU_JTG_TCLK, JTAG, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(12, CPU_JTG_TMS, JTAG, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(13, CPU_JTG_TDI, JTAG, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(14, CPU_JTG_TDO, JTAG, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(15, CPU_JTG_TRST, JTAG, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(16, AOGPIO_7, CLK, AUD, ____, GPIO, ____, ____, 0), + TH1520_PAD(17, AOGPIO_8, UART, AUD, IR, GPIO, ____, ____, 0), + TH1520_PAD(18, AOGPIO_9, UART, AUD, IR, GPIO, ____, ____, 0), + TH1520_PAD(19, AOGPIO_10, CLK, AUD, ____, GPIO, ____, ____, 0), + TH1520_PAD(20, AOGPIO_11, GPIO, AUD, ____, ____, ____, ____, 0), + TH1520_PAD(21, AOGPIO_12, GPIO, AUD, ____, ____, ____, ____, 0), + TH1520_PAD(22, AOGPIO_13, GPIO, AUD, ____, ____, ____, ____, 0), + TH1520_PAD(23, AOGPIO_14, GPIO, AUD, ____, ____, ____, ____, 0), + TH1520_PAD(24, AOGPIO_15, GPIO, AUD, ____, ____, ____, ____, 0), + TH1520_PAD(25, AUDIO_PA0, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(26, AUDIO_PA1, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(27, AUDIO_PA2, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(28, AUDIO_PA3, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(29, AUDIO_PA4, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(30, AUDIO_PA5, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(31, AUDIO_PA6, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(32, AUDIO_PA7, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(33, AUDIO_PA8, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(34, AUDIO_PA9, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(35, AUDIO_PA10, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(36, AUDIO_PA11, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(37, AUDIO_PA12, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(38, AUDIO_PA13, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(39, AUDIO_PA14, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(40, AUDIO_PA15, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(41, AUDIO_PA16, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(42, AUDIO_PA17, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(43, AUDIO_PA27, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(44, AUDIO_PA28, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(45, AUDIO_PA29, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(46, AUDIO_PA30, AUD, RST, ____, GPIO, ____, ____, 0), +}; + +static const struct pinctrl_pin_desc th1520_group2_pins[] = { + TH1520_PAD(0, QSPI1_SCLK, QSPI, ISO, ____, GPIO, FUSE, ____, 0), + TH1520_PAD(1, QSPI1_CSN0, QSPI, ____, I2C, GPIO, FUSE, ____, 0), + TH1520_PAD(2, QSPI1_D0_MOSI, QSPI, ISO, I2C, GPIO, FUSE, ____, 0), + TH1520_PAD(3, QSPI1_D1_MISO, QSPI, ISO, ____, GPIO, FUSE, ____, 0), + TH1520_PAD(4, QSPI1_D2_WP, QSPI, ISO, UART, GPIO, FUSE, ____, 0), + TH1520_PAD(5, QSPI1_D3_HOLD, QSPI, ISO, UART, GPIO, ____, ____, 0), + TH1520_PAD(6, I2C0_SCL, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(7, I2C0_SDA, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(8, I2C1_SCL, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(9, I2C1_SDA, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(10, UART1_TXD, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(11, UART1_RXD, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(12, UART4_TXD, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(13, UART4_RXD, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(14, UART4_CTSN, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(15, UART4_RTSN, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(16, UART3_TXD, DBG, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(17, UART3_RXD, DBG, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(18, GPIO0_18, GPIO, I2C, ____, ____, ____, ____, 0), + TH1520_PAD(19, GPIO0_19, GPIO, I2C, ____, ____, ____, ____, 0), + TH1520_PAD(20, GPIO0_20, GPIO, UART, IR, ____, ____, ____, 0), + TH1520_PAD(21, GPIO0_21, GPIO, UART, IR, ____, DPU0, DPU1, 0), + TH1520_PAD(22, GPIO0_22, GPIO, JTAG, I2C, ____, DPU0, DPU1, 0), + TH1520_PAD(23, GPIO0_23, GPIO, JTAG, I2C, ____, DPU0, DPU1, 0), + TH1520_PAD(24, GPIO0_24, GPIO, JTAG, QSPI, ____, DPU0, DPU1, 0), + TH1520_PAD(25, GPIO0_25, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(26, GPIO0_26, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(27, GPIO0_27, GPIO, ____, I2C, ____, DPU0, DPU1, 0), + TH1520_PAD(28, GPIO0_28, GPIO, ____, I2C, ____, DPU0, DPU1, 0), + TH1520_PAD(29, GPIO0_29, GPIO, ____, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(30, GPIO0_30, GPIO, ____, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(31, GPIO0_31, GPIO, ____, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(32, GPIO1_0, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(33, GPIO1_1, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(34, GPIO1_2, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(35, GPIO1_3, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(36, GPIO1_4, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(37, GPIO1_5, GPIO, ____, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(38, GPIO1_6, GPIO, ____, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(39, GPIO1_7, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(40, GPIO1_8, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(41, GPIO1_9, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(42, GPIO1_10, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(43, GPIO1_11, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(44, GPIO1_12, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(45, GPIO1_13, GPIO, UART, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(46, GPIO1_14, GPIO, UART, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(47, GPIO1_15, GPIO, UART, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(48, GPIO1_16, GPIO, UART, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(49, CLK_OUT_0, BSEL, CLK, ____, GPIO, ____, ____, 0), + TH1520_PAD(50, CLK_OUT_1, BSEL, CLK, ____, GPIO, ____, ____, 0), + TH1520_PAD(51, CLK_OUT_2, BSEL, CLK, ____, GPIO, ____, ____, 0), + TH1520_PAD(52, CLK_OUT_3, BSEL, CLK, ____, GPIO, ____, ____, 0), + TH1520_PAD(53, GPIO1_21, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(54, GPIO1_22, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(55, GPIO1_23, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(56, GPIO1_24, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(57, GPIO1_25, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(58, GPIO1_26, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(59, GPIO1_27, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(60, GPIO1_28, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(61, GPIO1_29, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(62, GPIO1_30, GPIO, ____, ISP, ____, ____, ____, 0), +}; + +static const struct pinctrl_pin_desc th1520_group3_pins[] = { + TH1520_PAD(0, UART0_TXD, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(1, UART0_RXD, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(2, QSPI0_SCLK, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(3, QSPI0_CSN0, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(4, QSPI0_CSN1, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(5, QSPI0_D0_MOSI, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(6, QSPI0_D1_MISO, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(7, QSPI0_D2_WP, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(8, QSPI1_D3_HOLD, QSPI, ____, I2S, GPIO, ____, ____, 0), + TH1520_PAD(9, I2C2_SCL, I2C, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(10, I2C2_SDA, I2C, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(11, I2C3_SCL, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(12, I2C3_SDA, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(13, GPIO2_13, GPIO, SPI, ____, ____, ____, ____, 0), + TH1520_PAD(14, SPI_SCLK, SPI, UART, IR, GPIO, ____, ____, 0), + TH1520_PAD(15, SPI_CSN, SPI, UART, IR, GPIO, ____, ____, 0), + TH1520_PAD(16, SPI_MOSI, SPI, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(17, SPI_MISO, SPI, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(18, GPIO2_18, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(19, GPIO2_19, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(20, GPIO2_20, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(21, GPIO2_21, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(22, GPIO2_22, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(23, GPIO2_23, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(24, GPIO2_24, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(25, GPIO2_25, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(26, SDIO0_WPRTN, SDIO, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(27, SDIO0_DETN, SDIO, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(28, SDIO1_WPRTN, SDIO, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(29, SDIO1_DETN, SDIO, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(30, GPIO2_30, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(31, GPIO2_31, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(32, GPIO3_0, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(33, GPIO3_1, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(34, GPIO3_2, GPIO, PWM, ____, ____, ____, ____, 0), + TH1520_PAD(35, GPIO3_3, GPIO, PWM, ____, ____, ____, ____, 0), + TH1520_PAD(36, HDMI_SCL, HDMI, PWM, ____, GPIO, ____, ____, 0), + TH1520_PAD(37, HDMI_SDA, HDMI, PWM, ____, GPIO, ____, ____, 0), + TH1520_PAD(38, HDMI_CEC, HDMI, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(39, GMAC0_TX_CLK, MAC0, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(40, GMAC0_RX_CLK, MAC0, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(41, GMAC0_TXEN, MAC0, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(42, GMAC0_TXD0, MAC0, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(43, GMAC0_TXD1, MAC0, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(44, GMAC0_TXD2, MAC0, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(45, GMAC0_TXD3, MAC0, I2C, ____, GPIO, ____, ____, 0), + TH1520_PAD(46, GMAC0_RXDV, MAC0, I2C, ____, GPIO, ____, ____, 0), + TH1520_PAD(47, GMAC0_RXD0, MAC0, I2C, ____, GPIO, ____, ____, 0), + TH1520_PAD(48, GMAC0_RXD1, MAC0, I2C, ____, GPIO, ____, ____, 0), + TH1520_PAD(49, GMAC0_RXD2, MAC0, SPI, ____, GPIO, ____, ____, 0), + TH1520_PAD(50, GMAC0_RXD3, MAC0, SPI, ____, GPIO, ____, ____, 0), + TH1520_PAD(51, GMAC0_MDC, MAC0, SPI, MAC1, GPIO, ____, ____, 0), + TH1520_PAD(52, GMAC0_MDIO, MAC0, SPI, MAC1, GPIO, ____, ____, 0), + TH1520_PAD(53, GMAC0_COL, MAC0, PWM, ____, GPIO, ____, ____, 0), + TH1520_PAD(54, GMAC0_CRS, MAC0, PWM, ____, GPIO, ____, ____, 0), +}; + +static const struct th1520_pad_group th1520_group1 = { + .name = "th1520-group1", + .pins = th1520_group1_pins, + .npins = ARRAY_SIZE(th1520_group1_pins), +}; + +static const struct th1520_pad_group th1520_group2 = { + .name = "th1520-group2", + .pins = th1520_group2_pins, + .npins = ARRAY_SIZE(th1520_group2_pins), +}; + +static const struct th1520_pad_group th1520_group3 = { + .name = "th1520-group3", + .pins = th1520_group3_pins, + .npins = ARRAY_SIZE(th1520_group3_pins), +}; + +static int th1520_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + + return thp->desc.npins; +} + +static const char *th1520_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int gsel) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + + return thp->desc.pins[gsel].name; +} + +static int th1520_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int gsel, + const unsigned int **pins, + unsigned int *npins) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + + *pins = &thp->desc.pins[gsel].number; + *npins = 1; + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void th1520_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + void __iomem *padcfg = th1520_padcfg(thp, pin); + void __iomem *muxcfg = th1520_muxcfg(thp, pin); + u32 pad; + u32 mux; + + scoped_guard(raw_spinlock_irqsave, &thp->lock) { + pad = readl_relaxed(padcfg); + mux = readl_relaxed(muxcfg); + } + + seq_printf(s, "[PADCFG_%03u:0x%x=0x%07x MUXCFG_%03u:0x%x=0x%08x]", + 1 + pin / 2, 0x000 + 4 * (pin / 2), pad, + 1 + pin / 8, 0x400 + 4 * (pin / 8), mux); +} +#else +#define th1520_pin_dbg_show NULL +#endif + +static void th1520_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned int nmaps) +{ + unsigned long *seen = NULL; + unsigned int i; + + for (i = 0; i < nmaps; i++) { + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN && + map[i].data.configs.configs != seen) { + seen = map[i].data.configs.configs; + kfree(seen); + } + } + + kfree(map); +} + +static int th1520_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **maps, + unsigned int *num_maps) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + struct device_node *child; + struct pinctrl_map *map; + unsigned long *configs; + unsigned int nconfigs; + unsigned int nmaps; + int ret; + + nmaps = 0; + for_each_available_child_of_node(np, child) { + int npins = of_property_count_strings(child, "pins"); + + if (npins <= 0) { + of_node_put(child); + dev_err(thp->pctl->dev, "no pins selected for %pOFn.%pOFn\n", + np, child); + return -EINVAL; + } + nmaps += npins; + if (of_property_present(child, "function")) + nmaps += npins; + } + + map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL); + if (!map) + return -ENOMEM; + + nmaps = 0; + mutex_lock(&thp->mutex); + for_each_available_child_of_node(np, child) { + unsigned int rollback = nmaps; + enum th1520_muxtype muxtype; + struct property *prop; + const char *funcname; + const char **pgnames; + const char *pinname; + int npins; + + ret = pinconf_generic_parse_dt_config(child, pctldev, &configs, &nconfigs); + if (ret) { + dev_err(thp->pctl->dev, "%pOFn.%pOFn: error parsing pin config\n", + np, child); + goto put_child; + } + + if (!of_property_read_string(child, "function", &funcname)) { + muxtype = th1520_muxtype_get(funcname); + if (!muxtype) { + dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown function '%s'\n", + np, child, funcname); + ret = -EINVAL; + goto free_configs; + } + + funcname = devm_kasprintf(thp->pctl->dev, GFP_KERNEL, "%pOFn.%pOFn", + np, child); + if (!funcname) { + ret = -ENOMEM; + goto free_configs; + } + + npins = of_property_count_strings(child, "pins"); + pgnames = devm_kcalloc(thp->pctl->dev, npins, sizeof(*pgnames), GFP_KERNEL); + if (!pgnames) { + ret = -ENOMEM; + goto free_configs; + } + } else { + funcname = NULL; + } + + npins = 0; + of_property_for_each_string(child, "pins", prop, pinname) { + unsigned int i; + + for (i = 0; i < thp->desc.npins; i++) { + if (!strcmp(pinname, thp->desc.pins[i].name)) + break; + } + if (i == thp->desc.npins) { + nmaps = rollback; + dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown pin '%s'\n", + np, child, pinname); + goto free_configs; + } + + if (nconfigs) { + map[nmaps].type = PIN_MAP_TYPE_CONFIGS_PIN; + map[nmaps].data.configs.group_or_pin = thp->desc.pins[i].name; + map[nmaps].data.configs.configs = configs; + map[nmaps].data.configs.num_configs = nconfigs; + nmaps += 1; + } + if (funcname) { + pgnames[npins++] = thp->desc.pins[i].name; + map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP; + map[nmaps].data.mux.function = funcname; + map[nmaps].data.mux.group = thp->desc.pins[i].name; + nmaps += 1; + } + } + + if (funcname) { + ret = pinmux_generic_add_function(pctldev, funcname, pgnames, + npins, (void *)muxtype); + if (ret < 0) { + dev_err(thp->pctl->dev, "error adding function %s\n", funcname); + goto put_child; + } + } + } + + *maps = map; + *num_maps = nmaps; + mutex_unlock(&thp->mutex); + return 0; + +free_configs: + kfree(configs); +put_child: + of_node_put(child); + th1520_pinctrl_dt_free_map(pctldev, map, nmaps); + mutex_unlock(&thp->mutex); + return ret; +} + +static const struct pinctrl_ops th1520_pinctrl_ops = { + .get_groups_count = th1520_pinctrl_get_groups_count, + .get_group_name = th1520_pinctrl_get_group_name, + .get_group_pins = th1520_pinctrl_get_group_pins, + .pin_dbg_show = th1520_pin_dbg_show, + .dt_node_to_map = th1520_pinctrl_dt_node_to_map, + .dt_free_map = th1520_pinctrl_dt_free_map, +}; + +static const u8 th1520_drive_strength_in_mA[16] = { + 1, 2, 3, 5, 7, 8, 10, 12, 13, 15, 16, 18, 20, 21, 23, 25, +}; + +static u16 th1520_drive_strength_from_mA(u32 arg) +{ + u16 ds; + + for (ds = 0; ds < TH1520_PADCFG_DS; ds++) { + if (arg <= th1520_drive_strength_in_mA[ds]) + return ds; + } + return TH1520_PADCFG_DS; +} + +static int th1520_padcfg_rmw(struct th1520_pinctrl *thp, unsigned int pin, + u32 mask, u32 value) +{ + void __iomem *padcfg = th1520_padcfg(thp, pin); + unsigned int shift = th1520_padcfg_shift(pin); + u32 tmp; + + mask <<= shift; + value <<= shift; + + scoped_guard(raw_spinlock_irqsave, &thp->lock) { + tmp = readl_relaxed(padcfg); + tmp = (tmp & ~mask) | value; + writel_relaxed(tmp, padcfg); + } + return 0; +} + +static int th1520_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + const struct pin_desc *desc = pin_desc_get(pctldev, pin); + bool enabled; + int param; + u32 value; + u32 arg; + + if ((uintptr_t)desc->drv_data & TH1520_PAD_NO_PADCFG) + return -ENOTSUPP; + + value = readl_relaxed(th1520_padcfg(thp, pin)); + value = (value >> th1520_padcfg_shift(pin)) & GENMASK(9, 0); + + param = pinconf_to_config_param(*config); + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + enabled = !(value & (TH1520_PADCFG_SPU | TH1520_PADCFG_PE)); + arg = 0; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + enabled = (value & TH1520_PADCFG_BIAS) == TH1520_PADCFG_PE; + arg = enabled ? TH1520_PULL_DOWN_OHM : 0; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (value & TH1520_PADCFG_SPU) { + enabled = true; + arg = TH1520_PULL_STRONG_OHM; + } else if ((value & (TH1520_PADCFG_PE | TH1520_PADCFG_PS)) == + (TH1520_PADCFG_PE | TH1520_PADCFG_PS)) { + enabled = true; + arg = TH1520_PULL_UP_OHM; + } else { + enabled = false; + arg = 0; + } + break; + case PIN_CONFIG_DRIVE_STRENGTH: + enabled = true; + arg = th1520_drive_strength_in_mA[value & TH1520_PADCFG_DS]; + break; + case PIN_CONFIG_INPUT_ENABLE: + enabled = value & TH1520_PADCFG_IE; + arg = enabled ? 1 : 0; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + enabled = value & TH1520_PADCFG_ST; + arg = enabled ? 1 : 0; + break; + case PIN_CONFIG_SLEW_RATE: + enabled = value & TH1520_PADCFG_SL; + arg = enabled ? 1 : 0; + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return enabled ? 0 : -EINVAL; +} + +static int th1520_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int gsel, unsigned long *config) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + unsigned int pin = thp->desc.pins[gsel].number; + + return th1520_pinconf_get(pctldev, pin, config); +} + +static int th1520_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + const struct pin_desc *desc = pin_desc_get(pctldev, pin); + unsigned int i; + u16 mask, value; + + if ((uintptr_t)desc->drv_data & TH1520_PAD_NO_PADCFG) + return -ENOTSUPP; + + mask = 0; + value = 0; + for (i = 0; i < num_configs; i++) { + int param = pinconf_to_config_param(configs[i]); + u32 arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + mask |= TH1520_PADCFG_BIAS; + value &= ~TH1520_PADCFG_BIAS; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg == 0) + return -ENOTSUPP; + mask |= TH1520_PADCFG_BIAS; + value &= ~TH1520_PADCFG_BIAS; + value |= TH1520_PADCFG_PE; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (arg == 0) + return -ENOTSUPP; + mask |= TH1520_PADCFG_BIAS; + value &= ~TH1520_PADCFG_BIAS; + if (arg == TH1520_PULL_STRONG_OHM) + value |= TH1520_PADCFG_SPU; + else + value |= TH1520_PADCFG_PE | TH1520_PADCFG_PS; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + mask |= TH1520_PADCFG_DS; + value &= ~TH1520_PADCFG_DS; + value |= th1520_drive_strength_from_mA(arg); + break; + case PIN_CONFIG_INPUT_ENABLE: + mask |= TH1520_PADCFG_IE; + if (arg) + value |= TH1520_PADCFG_IE; + else + value &= ~TH1520_PADCFG_IE; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + mask |= TH1520_PADCFG_ST; + if (arg) + value |= TH1520_PADCFG_ST; + else + value &= ~TH1520_PADCFG_ST; + break; + case PIN_CONFIG_SLEW_RATE: + mask |= TH1520_PADCFG_SL; + if (arg) + value |= TH1520_PADCFG_SL; + else + value &= ~TH1520_PADCFG_SL; + break; + default: + return -ENOTSUPP; + } + } + + return th1520_padcfg_rmw(thp, pin, mask, value); +} + +static int th1520_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int gsel, + unsigned long *configs, + unsigned int num_configs) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + unsigned int pin = thp->desc.pins[gsel].number; + + return th1520_pinconf_set(pctldev, pin, configs, num_configs); +} + +#ifdef CONFIG_DEBUG_FS +static void th1520_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + u32 value = readl_relaxed(th1520_padcfg(thp, pin)); + + value = (value >> th1520_padcfg_shift(pin)) & GENMASK(9, 0); + + seq_printf(s, " [0x%03x]", value); +} +#else +#define th1520_pinconf_dbg_show NULL +#endif + +static const struct pinconf_ops th1520_pinconf_ops = { + .pin_config_get = th1520_pinconf_get, + .pin_config_group_get = th1520_pinconf_group_get, + .pin_config_set = th1520_pinconf_set, + .pin_config_group_set = th1520_pinconf_group_set, + .pin_config_dbg_show = th1520_pinconf_dbg_show, + .is_generic = true, +}; + +static int th1520_pinmux_set(struct th1520_pinctrl *thp, unsigned int pin, + unsigned long muxdata, enum th1520_muxtype muxtype) +{ + void __iomem *muxcfg = th1520_muxcfg(thp, pin); + unsigned int shift = th1520_muxcfg_shift(pin); + u32 mask, value, tmp; + + for (value = 0; muxdata; muxdata >>= 5, value++) { + if ((muxdata & GENMASK(4, 0)) == muxtype) + break; + } + if (!muxdata) { + dev_err(thp->pctl->dev, "invalid mux %s for pin %s\n", + th1520_muxtype_string[muxtype], pin_get_name(thp->pctl, pin)); + return -EINVAL; + } + + mask = GENMASK(3, 0) << shift; + value = value << shift; + + scoped_guard(raw_spinlock_irqsave, &thp->lock) { + tmp = readl_relaxed(muxcfg); + tmp = (tmp & ~mask) | value; + writel_relaxed(tmp, muxcfg); + } + return 0; +} + +static int th1520_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int fsel, unsigned int gsel) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + const struct function_desc *func = pinmux_generic_get_function(pctldev, fsel); + + return th1520_pinmux_set(thp, thp->desc.pins[gsel].number, + (uintptr_t)thp->desc.pins[gsel].drv_data & TH1520_PAD_MUXDATA, + (uintptr_t)func->data); +} + +static int th1520_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + const struct pin_desc *desc = pin_desc_get(pctldev, offset); + + return th1520_pinmux_set(thp, offset, + (uintptr_t)desc->drv_data & TH1520_PAD_MUXDATA, + TH1520_MUX_GPIO); +} + +static int th1520_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset, bool input) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + + return th1520_padcfg_rmw(thp, offset, TH1520_PADCFG_IE, + input ? TH1520_PADCFG_IE : 0); +} + +static const struct pinmux_ops th1520_pinmux_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = th1520_pinmux_set_mux, + .gpio_request_enable = th1520_gpio_request_enable, + .gpio_set_direction = th1520_gpio_set_direction, + .strict = true, +}; + +static int th1520_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct th1520_pad_group *group = device_get_match_data(dev); + struct th1520_pinctrl *thp; + struct clk *clk; + int ret; + + thp = devm_kzalloc(dev, sizeof(*thp), GFP_KERNEL); + if (!thp) + return -ENOMEM; + + thp->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(thp->base)) + return PTR_ERR(thp->base); + + clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "error getting clock\n"); + + thp->desc.name = group->name; + thp->desc.pins = group->pins; + thp->desc.npins = group->npins; + thp->desc.pctlops = &th1520_pinctrl_ops; + thp->desc.pmxops = &th1520_pinmux_ops; + thp->desc.confops = &th1520_pinconf_ops; + thp->desc.owner = THIS_MODULE; + mutex_init(&thp->mutex); + raw_spin_lock_init(&thp->lock); + + ret = devm_pinctrl_register_and_init(dev, &thp->desc, thp, &thp->pctl); + if (ret) + return dev_err_probe(dev, ret, "could not register pinctrl driver\n"); + + return pinctrl_enable(thp->pctl); +} + +static const struct of_device_id th1520_pinctrl_of_match[] = { + { .compatible = "thead,th1520-group1-pinctrl", .data = &th1520_group1 }, + { .compatible = "thead,th1520-group2-pinctrl", .data = &th1520_group2 }, + { .compatible = "thead,th1520-group3-pinctrl", .data = &th1520_group3 }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, th1520_pinctrl_of_match); + +static struct platform_driver th1520_pinctrl_driver = { + .probe = th1520_pinctrl_probe, + .driver = { + .name = "pinctrl-th1520", + .of_match_table = th1520_pinctrl_of_match, + }, +}; +module_platform_driver(th1520_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for the T-Head TH1520 SoC"); +MODULE_AUTHOR("Emil Renner Berthing <emil.renner.berthing@canonical.com>"); +MODULE_LICENSE("GPL"); -- 2.43.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v2 2/8] pinctrl: Add driver for the T-Head TH1520 SoC 2024-01-03 13:28 ` [PATCH v2 2/8] pinctrl: Add driver for the T-Head TH1520 SoC Emil Renner Berthing @ 2024-01-27 23:02 ` Linus Walleij 2024-05-11 6:06 ` Andy Shevchenko 1 sibling, 0 replies; 25+ messages in thread From: Linus Walleij @ 2024-01-27 23:02 UTC (permalink / raw) To: Emil Renner Berthing Cc: linux-kernel, linux-gpio, devicetree, linux-riscv, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini On Wed, Jan 3, 2024 at 2:29 PM Emil Renner Berthing <emil.renner.berthing@canonical.com> wrote: > Add pinctrl driver for the T-Head TH1520 RISC-V SoC. > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> This driver looks mostly fine but I am waiting for the bindings to be hashed out. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 2/8] pinctrl: Add driver for the T-Head TH1520 SoC 2024-01-03 13:28 ` [PATCH v2 2/8] pinctrl: Add driver for the T-Head TH1520 SoC Emil Renner Berthing 2024-01-27 23:02 ` Linus Walleij @ 2024-05-11 6:06 ` Andy Shevchenko 1 sibling, 0 replies; 25+ messages in thread From: Andy Shevchenko @ 2024-05-11 6:06 UTC (permalink / raw) To: Emil Renner Berthing Cc: linux-kernel, linux-gpio, devicetree, linux-riscv, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini Wed, Jan 03, 2024 at 02:28:39PM +0100, Emil Renner Berthing kirjoitti: > Add pinctrl driver for the T-Head TH1520 RISC-V SoC. ... > +#include <linux/array_size.h> > +#include <linux/bits.h> > +#include <linux/cleanup.h> > +#include <linux/clk.h> > +#include <linux/device.h> > +#include <linux/io.h> > +#include <linux/mod_devicetable.h> > +#include <linux/module.h> > +#include <linux/mutex.h> > +#include <linux/of.h> > +#include <linux/platform_device.h> > +#include <linux/seq_file.h> > +#include <linux/spinlock.h> + types.h ... > +#define TH1520_PAD(_nr, _name, m0, m1, m2, m3, m4, m5, _flags) \ > + { .number = _nr, .name = #_name, .drv_data = (void *)((_flags) | \ > + (TH1520_MUX_##m0 << 0) | (TH1520_MUX_##m1 << 5) | (TH1520_MUX_##m2 << 10) | \ > + (TH1520_MUX_##m3 << 15) | (TH1520_MUX_##m4 << 20) | (TH1520_MUX_##m5 << 25)) } It's better to read in a form of #define TH1520_PAD(_nr, _name, m0, m1, m2, m3, m4, m5, _flags) \ { \ .number = _nr, \ .name = #_name, \ .drv_data = (void *)((_flags) | \ (TH1520_MUX_##m0 << 0) | (TH1520_MUX_##m1 << 5) | (TH1520_MUX_##m2 << 10) | \ (TH1520_MUX_##m3 << 15) | (TH1520_MUX_##m4 << 20) | (TH1520_MUX_##m5 << 25)) \ } ... > +static void th1520_pin_dbg_show(struct pinctrl_dev *pctldev, > + struct seq_file *s, unsigned int pin) static void th1520_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int pin) (it even satisfies 80 characters limit) ... > + nmaps = 0; > + for_each_available_child_of_node(np, child) { You want to use _scoped() variant. > + int npins = of_property_count_strings(child, "pins"); > + > + if (npins <= 0) { Better to decouple definition and assignment int npins; npins = of_property_count_strings(child, "pins"); if (npins <= 0) { Besides that, if npins can hold an error code... > + of_node_put(child); > + dev_err(thp->pctl->dev, "no pins selected for %pOFn.%pOFn\n", > + np, child); > + return -EINVAL; ...why is it being shadowed? > + } > + nmaps += npins; > + if (of_property_present(child, "function")) > + nmaps += npins; > + } > + map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL); > + if (!map) > + return -ENOMEM; > + > + nmaps = 0; > + mutex_lock(&thp->mutex); > + for_each_available_child_of_node(np, child) { You want to use _scoped() variant. > + unsigned int rollback = nmaps; > + enum th1520_muxtype muxtype; > + struct property *prop; > + const char *funcname; > + const char **pgnames; > + const char *pinname; > + int npins; > + > + ret = pinconf_generic_parse_dt_config(child, pctldev, &configs, &nconfigs); > + if (ret) { > + dev_err(thp->pctl->dev, "%pOFn.%pOFn: error parsing pin config\n", > + np, child); > + goto put_child; > + } > + if (!of_property_read_string(child, "function", &funcname)) { Why not traditional pattern, i.e. "errors first"? if (of_property_read_string(child, "function", &funcname)) { funcname = NULL; } else { ... } > + muxtype = th1520_muxtype_get(funcname); > + if (!muxtype) { > + dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown function '%s'\n", > + np, child, funcname); > + ret = -EINVAL; > + goto free_configs; > + } > + > + funcname = devm_kasprintf(thp->pctl->dev, GFP_KERNEL, "%pOFn.%pOFn", > + np, child); With help of struct device *dev = thp->pctl->dev; this and other lines in this function become shorter and easier to read. > + if (!funcname) { > + ret = -ENOMEM; > + goto free_configs; > + } > + > + npins = of_property_count_strings(child, "pins"); > + pgnames = devm_kcalloc(thp->pctl->dev, npins, sizeof(*pgnames), GFP_KERNEL); > + if (!pgnames) { > + ret = -ENOMEM; > + goto free_configs; > + } > + } else { > + funcname = NULL; > + } > + > + npins = 0; > + of_property_for_each_string(child, "pins", prop, pinname) { > + unsigned int i; > + > + for (i = 0; i < thp->desc.npins; i++) { > + if (!strcmp(pinname, thp->desc.pins[i].name)) > + break; > + } > + if (i == thp->desc.npins) { > + nmaps = rollback; > + dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown pin '%s'\n", > + np, child, pinname); > + goto free_configs; > + } > + > + if (nconfigs) { > + map[nmaps].type = PIN_MAP_TYPE_CONFIGS_PIN; > + map[nmaps].data.configs.group_or_pin = thp->desc.pins[i].name; > + map[nmaps].data.configs.configs = configs; > + map[nmaps].data.configs.num_configs = nconfigs; > + nmaps += 1; ++ ? > + } > + if (funcname) { > + pgnames[npins++] = thp->desc.pins[i].name; > + map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP; > + map[nmaps].data.mux.function = funcname; > + map[nmaps].data.mux.group = thp->desc.pins[i].name; > + nmaps += 1; ++ ? > + } > + } > + > + if (funcname) { > + ret = pinmux_generic_add_function(pctldev, funcname, pgnames, > + npins, (void *)muxtype); > + if (ret < 0) { > + dev_err(thp->pctl->dev, "error adding function %s\n", funcname); > + goto put_child; > + } > + } > + } > + > + *maps = map; > + *num_maps = nmaps; > + mutex_unlock(&thp->mutex); > + return 0; > + > +free_configs: > + kfree(configs); > +put_child: > + of_node_put(child); > + th1520_pinctrl_dt_free_map(pctldev, map, nmaps); > + mutex_unlock(&thp->mutex); > + return ret; > +} ... > + if ((uintptr_t)desc->drv_data & TH1520_PAD_NO_PADCFG) You have a lot of explicit castings here and there, can you reduce the usage count of them? > + return -ENOTSUPP; ... > + if ((uintptr_t)desc->drv_data & TH1520_PAD_NO_PADCFG) At least this one can be moved to a helper (macro?). > + return -ENOTSUPP; -- With Best Regards, Andy Shevchenko ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 3/8] riscv: dts: thead: Add TH1520 pin control nodes 2024-01-03 13:28 [PATCH v2 0/8] Add T-Head TH1520 SoC pin control Emil Renner Berthing 2024-01-03 13:28 ` [PATCH v2 1/8] dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings Emil Renner Berthing 2024-01-03 13:28 ` [PATCH v2 2/8] pinctrl: Add driver for the T-Head TH1520 SoC Emil Renner Berthing @ 2024-01-03 13:28 ` Emil Renner Berthing 2024-01-08 17:34 ` Conor Dooley 2024-01-03 13:28 ` [PATCH v2 4/8] riscv: dts: thead: Add TH1520 GPIO ranges Emil Renner Berthing ` (6 subsequent siblings) 9 siblings, 1 reply; 25+ messages in thread From: Emil Renner Berthing @ 2024-01-03 13:28 UTC (permalink / raw) To: linux-kernel, linux-gpio, devicetree, linux-riscv Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini Add nodes for pin controllers on the T-Head TH1520 RISC-V SoC. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> --- .../boot/dts/thead/th1520-beaglev-ahead.dts | 4 ++++ .../dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++ arch/riscv/boot/dts/thead/th1520.dtsi | 24 +++++++++++++++++++ 3 files changed, 32 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts index 70e8042c8304..6c56318a8705 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -44,6 +44,10 @@ &osc_32k { clock-frequency = <32768>; }; +&aonsys_clk { + clock-frequency = <73728000>; +}; + &apb_clk { clock-frequency = <62500000>; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index a802ab110429..9865925be372 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -25,6 +25,10 @@ &osc_32k { clock-frequency = <32768>; }; +&aonsys_clk { + clock-frequency = <73728000>; +}; + &apb_clk { clock-frequency = <62500000>; }; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index ba4d2c673ac8..e65a306ff575 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -134,6 +134,12 @@ osc_32k: 32k-oscillator { #clock-cells = <0>; }; + aonsys_clk: aonsys-clk { + compatible = "fixed-clock"; + clock-output-names = "aonsys_clk"; + #clock-cells = <0>; + }; + apb_clk: apb-clk-clock { compatible = "fixed-clock"; clock-output-names = "apb_clk"; @@ -242,6 +248,12 @@ portd: gpio-controller@0 { }; }; + padctrl1_apsys: pinctrl@ffe7f3c000 { + compatible = "thead,th1520-group2-pinctrl"; + reg = <0xff 0xe7f3c000 0x0 0x1000>; + clocks = <&apb_clk>; + }; + gpio0: gpio@ffec005000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xec005000 0x0 0x1000>; @@ -278,6 +290,12 @@ portb: gpio-controller@0 { }; }; + padctrl0_apsys: pinctrl@ffec007000 { + compatible = "thead,th1520-group3-pinctrl"; + reg = <0xff 0xec007000 0x0 0x1000>; + clocks = <&apb_clk>; + }; + uart2: serial@ffec010000 { compatible = "snps,dw-apb-uart"; reg = <0xff 0xec010000 0x0 0x4000>; @@ -414,6 +432,12 @@ porte: gpio-controller@0 { }; }; + padctrl_aosys: pinctrl@fffff4a000 { + compatible = "thead,th1520-group1-pinctrl"; + reg = <0xff 0xfff4a000 0x0 0x2000>; + clocks = <&aonsys_clk>; + }; + ao_gpio1: gpio@fffff52000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xfff52000 0x0 0x1000>; -- 2.43.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v2 3/8] riscv: dts: thead: Add TH1520 pin control nodes 2024-01-03 13:28 ` [PATCH v2 3/8] riscv: dts: thead: Add TH1520 pin control nodes Emil Renner Berthing @ 2024-01-08 17:34 ` Conor Dooley 2024-01-09 12:02 ` Emil Renner Berthing 0 siblings, 1 reply; 25+ messages in thread From: Conor Dooley @ 2024-01-08 17:34 UTC (permalink / raw) To: Emil Renner Berthing Cc: linux-kernel, linux-gpio, devicetree, linux-riscv, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini [-- Attachment #1: Type: text/plain, Size: 1955 bytes --] On Wed, Jan 03, 2024 at 02:28:40PM +0100, Emil Renner Berthing wrote: > Add nodes for pin controllers on the T-Head TH1520 RISC-V SoC. > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > --- > .../boot/dts/thead/th1520-beaglev-ahead.dts | 4 ++++ > .../dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++ > arch/riscv/boot/dts/thead/th1520.dtsi | 24 +++++++++++++++++++ > 3 files changed, 32 insertions(+) > > diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > index 70e8042c8304..6c56318a8705 100644 > --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > @@ -44,6 +44,10 @@ &osc_32k { > clock-frequency = <32768>; > }; > > +&aonsys_clk { > + clock-frequency = <73728000>; > +}; > + > &apb_clk { > clock-frequency = <62500000>; > }; > diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > index a802ab110429..9865925be372 100644 > --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > @@ -25,6 +25,10 @@ &osc_32k { > clock-frequency = <32768>; > }; > > +&aonsys_clk { > + clock-frequency = <73728000>; > +}; > + > &apb_clk { > clock-frequency = <62500000>; > }; > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi > index ba4d2c673ac8..e65a306ff575 100644 > --- a/arch/riscv/boot/dts/thead/th1520.dtsi > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi > @@ -134,6 +134,12 @@ osc_32k: 32k-oscillator { > #clock-cells = <0>; > }; > > + aonsys_clk: aonsys-clk { > + compatible = "fixed-clock"; > + clock-output-names = "aonsys_clk"; > + #clock-cells = <0>; > + }; Did this stuff sneak into this commit accidentally? [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 3/8] riscv: dts: thead: Add TH1520 pin control nodes 2024-01-08 17:34 ` Conor Dooley @ 2024-01-09 12:02 ` Emil Renner Berthing 2024-01-09 13:04 ` Conor Dooley 0 siblings, 1 reply; 25+ messages in thread From: Emil Renner Berthing @ 2024-01-09 12:02 UTC (permalink / raw) To: Conor Dooley, Emil Renner Berthing Cc: linux-kernel, linux-gpio, devicetree, linux-riscv, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini Conor Dooley wrote: > On Wed, Jan 03, 2024 at 02:28:40PM +0100, Emil Renner Berthing wrote: > > Add nodes for pin controllers on the T-Head TH1520 RISC-V SoC. > > > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > --- > > .../boot/dts/thead/th1520-beaglev-ahead.dts | 4 ++++ > > .../dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++ > > arch/riscv/boot/dts/thead/th1520.dtsi | 24 +++++++++++++++++++ > > 3 files changed, 32 insertions(+) > > > > diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > > index 70e8042c8304..6c56318a8705 100644 > > --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > > +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > > @@ -44,6 +44,10 @@ &osc_32k { > > clock-frequency = <32768>; > > }; > > > > +&aonsys_clk { > > + clock-frequency = <73728000>; > > +}; > > + > > &apb_clk { > > clock-frequency = <62500000>; > > }; > > diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > > index a802ab110429..9865925be372 100644 > > --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > > +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > > @@ -25,6 +25,10 @@ &osc_32k { > > clock-frequency = <32768>; > > }; > > > > +&aonsys_clk { > > + clock-frequency = <73728000>; > > +}; > > + > > &apb_clk { > > clock-frequency = <62500000>; > > }; > > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi > > index ba4d2c673ac8..e65a306ff575 100644 > > --- a/arch/riscv/boot/dts/thead/th1520.dtsi > > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi > > @@ -134,6 +134,12 @@ osc_32k: 32k-oscillator { > > #clock-cells = <0>; > > }; > > > > + aonsys_clk: aonsys-clk { > > + compatible = "fixed-clock"; > > + clock-output-names = "aonsys_clk"; > > + #clock-cells = <0>; > > + }; > > Did this stuff sneak into this commit accidentally? Not really by accident no. It turns out the clock tree has gates for the bus clock of each pinctrl block and I think it's better to add this clock dependency to the bindings and driver up front. Since there is not yet any clock driver the initial device tree for the TH1520 included the dummy apb_clk that two of the pinctrl blocks derive their clock from, but not the "aonsys" clock needed by the "always-on" pinctrl. I thought it was better to add this dummy clock with the only (so far) user of it, but if you have a better idea, let me know. /Emil ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 3/8] riscv: dts: thead: Add TH1520 pin control nodes 2024-01-09 12:02 ` Emil Renner Berthing @ 2024-01-09 13:04 ` Conor Dooley 2024-01-09 14:28 ` Emil Renner Berthing 0 siblings, 1 reply; 25+ messages in thread From: Conor Dooley @ 2024-01-09 13:04 UTC (permalink / raw) To: Emil Renner Berthing Cc: Conor Dooley, linux-kernel, linux-gpio, devicetree, linux-riscv, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini [-- Attachment #1: Type: text/plain, Size: 3402 bytes --] On Tue, Jan 09, 2024 at 04:02:01AM -0800, Emil Renner Berthing wrote: > Conor Dooley wrote: > > On Wed, Jan 03, 2024 at 02:28:40PM +0100, Emil Renner Berthing wrote: > > > Add nodes for pin controllers on the T-Head TH1520 RISC-V SoC. > > > > > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > > --- > > > .../boot/dts/thead/th1520-beaglev-ahead.dts | 4 ++++ > > > .../dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++ > > > arch/riscv/boot/dts/thead/th1520.dtsi | 24 +++++++++++++++++++ > > > 3 files changed, 32 insertions(+) > > > > > > diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > > > index 70e8042c8304..6c56318a8705 100644 > > > --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > > > +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > > > @@ -44,6 +44,10 @@ &osc_32k { > > > clock-frequency = <32768>; > > > }; > > > > > > +&aonsys_clk { > > > + clock-frequency = <73728000>; > > > +}; > > > + > > > &apb_clk { > > > clock-frequency = <62500000>; > > > }; > > > diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > > > index a802ab110429..9865925be372 100644 > > > --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > > > +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > > > @@ -25,6 +25,10 @@ &osc_32k { > > > clock-frequency = <32768>; > > > }; > > > > > > +&aonsys_clk { > > > + clock-frequency = <73728000>; > > > +}; > > > + > > > &apb_clk { > > > clock-frequency = <62500000>; > > > }; > > > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi > > > index ba4d2c673ac8..e65a306ff575 100644 > > > --- a/arch/riscv/boot/dts/thead/th1520.dtsi > > > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi > > > @@ -134,6 +134,12 @@ osc_32k: 32k-oscillator { > > > #clock-cells = <0>; > > > }; > > > > > > + aonsys_clk: aonsys-clk { > > > + compatible = "fixed-clock"; > > > + clock-output-names = "aonsys_clk"; > > > + #clock-cells = <0>; > > > + }; > > > > Did this stuff sneak into this commit accidentally? > > Not really by accident no. It turns out the clock tree has gates for the bus > clock of each pinctrl block and I think it's better to add this clock > dependency to the bindings and driver up front. Maybe if I had looked a wee bit more deeply I would've noticed that it was used there, but it's always good to mention the rationale in the commit message so that it's more obvious why you're doin it. > Since there is not yet any clock driver the initial device tree for the TH1520 > included the dummy apb_clk that two of the pinctrl blocks derive their clock > from, but not the "aonsys" clock needed by the "always-on" pinctrl. I thought > it was better to add this dummy clock with the only (so far) user of it, but if > you have a better idea, let me know. No, that's fine. I was just wondering why there was an unmentioned set of clocks being added. If they're stubbed fixed clocks I dunno if it makes sense to add them to the board.dts/module.dtsi files though. Where do the initial values come from for the rates? Out of reset values or set by firmware that may vary from board to board? Cheers, Conor. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 3/8] riscv: dts: thead: Add TH1520 pin control nodes 2024-01-09 13:04 ` Conor Dooley @ 2024-01-09 14:28 ` Emil Renner Berthing 2024-01-09 17:34 ` Conor Dooley 0 siblings, 1 reply; 25+ messages in thread From: Emil Renner Berthing @ 2024-01-09 14:28 UTC (permalink / raw) To: Conor Dooley, Emil Renner Berthing Cc: Conor Dooley, linux-kernel, linux-gpio, devicetree, linux-riscv, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini Conor Dooley wrote: > On Tue, Jan 09, 2024 at 04:02:01AM -0800, Emil Renner Berthing wrote: > > Conor Dooley wrote: > > > On Wed, Jan 03, 2024 at 02:28:40PM +0100, Emil Renner Berthing wrote: > > > > Add nodes for pin controllers on the T-Head TH1520 RISC-V SoC. > > > > > > > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > > > --- > > > > .../boot/dts/thead/th1520-beaglev-ahead.dts | 4 ++++ > > > > .../dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++ > > > > arch/riscv/boot/dts/thead/th1520.dtsi | 24 +++++++++++++++++++ > > > > 3 files changed, 32 insertions(+) > > > > > > > > diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > > > > index 70e8042c8304..6c56318a8705 100644 > > > > --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > > > > +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > > > > @@ -44,6 +44,10 @@ &osc_32k { > > > > clock-frequency = <32768>; > > > > }; > > > > > > > > +&aonsys_clk { > > > > + clock-frequency = <73728000>; > > > > +}; > > > > + > > > > &apb_clk { > > > > clock-frequency = <62500000>; > > > > }; > > > > diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > > > > index a802ab110429..9865925be372 100644 > > > > --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > > > > +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > > > > @@ -25,6 +25,10 @@ &osc_32k { > > > > clock-frequency = <32768>; > > > > }; > > > > > > > > +&aonsys_clk { > > > > + clock-frequency = <73728000>; > > > > +}; > > > > + > > > > &apb_clk { > > > > clock-frequency = <62500000>; > > > > }; > > > > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi > > > > index ba4d2c673ac8..e65a306ff575 100644 > > > > --- a/arch/riscv/boot/dts/thead/th1520.dtsi > > > > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi > > > > @@ -134,6 +134,12 @@ osc_32k: 32k-oscillator { > > > > #clock-cells = <0>; > > > > }; > > > > > > > > + aonsys_clk: aonsys-clk { > > > > + compatible = "fixed-clock"; > > > > + clock-output-names = "aonsys_clk"; > > > > + #clock-cells = <0>; > > > > + }; > > > > > > Did this stuff sneak into this commit accidentally? > > > > Not really by accident no. It turns out the clock tree has gates for the bus > > clock of each pinctrl block and I think it's better to add this clock > > dependency to the bindings and driver up front. > > Maybe if I had looked a wee bit more deeply I would've noticed that it > was used there, but it's always good to mention the rationale in the > commit message so that it's more obvious why you're doin it. You absolutely right. I forgot to update the commit message. > > Since there is not yet any clock driver the initial device tree for the TH1520 > > included the dummy apb_clk that two of the pinctrl blocks derive their clock > > from, but not the "aonsys" clock needed by the "always-on" pinctrl. I thought > > it was better to add this dummy clock with the only (so far) user of it, but if > > you have a better idea, let me know. > > No, that's fine. I was just wondering why there was an unmentioned set > of clocks being added. If they're stubbed fixed clocks I dunno if it > makes sense to add them to the board.dts/module.dtsi files though. Where > do the initial values come from for the rates? Out of reset values or > set by firmware that may vary from board to board? The vendor u-boot sets the PLLs different from the reset values. For now I think it's the same code for every board using the Lichee Pi 4A module (and probably also for the BeagleV Ahead), but it might still make sense to move the freqency to the board instead of the module device tree. /Emil ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 3/8] riscv: dts: thead: Add TH1520 pin control nodes 2024-01-09 14:28 ` Emil Renner Berthing @ 2024-01-09 17:34 ` Conor Dooley 2024-01-09 18:30 ` Drew Fustini 0 siblings, 1 reply; 25+ messages in thread From: Conor Dooley @ 2024-01-09 17:34 UTC (permalink / raw) To: Emil Renner Berthing Cc: Conor Dooley, linux-kernel, linux-gpio, devicetree, linux-riscv, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini [-- Attachment #1: Type: text/plain, Size: 4356 bytes --] On Tue, Jan 09, 2024 at 06:28:19AM -0800, Emil Renner Berthing wrote: > Conor Dooley wrote: > > On Tue, Jan 09, 2024 at 04:02:01AM -0800, Emil Renner Berthing wrote: > > > Conor Dooley wrote: > > > > On Wed, Jan 03, 2024 at 02:28:40PM +0100, Emil Renner Berthing wrote: > > > > > Add nodes for pin controllers on the T-Head TH1520 RISC-V SoC. > > > > > > > > > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > > > > --- > > > > > .../boot/dts/thead/th1520-beaglev-ahead.dts | 4 ++++ > > > > > .../dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++ > > > > > arch/riscv/boot/dts/thead/th1520.dtsi | 24 +++++++++++++++++++ > > > > > 3 files changed, 32 insertions(+) > > > > > > > > > > diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > > > > > index 70e8042c8304..6c56318a8705 100644 > > > > > --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > > > > > +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > > > > > @@ -44,6 +44,10 @@ &osc_32k { > > > > > clock-frequency = <32768>; > > > > > }; > > > > > > > > > > +&aonsys_clk { > > > > > + clock-frequency = <73728000>; > > > > > +}; > > > > > + > > > > > &apb_clk { > > > > > clock-frequency = <62500000>; > > > > > }; > > > > > diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > > > > > index a802ab110429..9865925be372 100644 > > > > > --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > > > > > +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > > > > > @@ -25,6 +25,10 @@ &osc_32k { > > > > > clock-frequency = <32768>; > > > > > }; > > > > > > > > > > +&aonsys_clk { > > > > > + clock-frequency = <73728000>; > > > > > +}; > > > > > + > > > > > &apb_clk { > > > > > clock-frequency = <62500000>; > > > > > }; > > > > > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi > > > > > index ba4d2c673ac8..e65a306ff575 100644 > > > > > --- a/arch/riscv/boot/dts/thead/th1520.dtsi > > > > > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi > > > > > @@ -134,6 +134,12 @@ osc_32k: 32k-oscillator { > > > > > #clock-cells = <0>; > > > > > }; > > > > > > > > > > + aonsys_clk: aonsys-clk { > > > > > + compatible = "fixed-clock"; > > > > > + clock-output-names = "aonsys_clk"; > > > > > + #clock-cells = <0>; > > > > > + }; > > > > > > > > Did this stuff sneak into this commit accidentally? > > > > > > Not really by accident no. It turns out the clock tree has gates for the bus > > > clock of each pinctrl block and I think it's better to add this clock > > > dependency to the bindings and driver up front. > > > > Maybe if I had looked a wee bit more deeply I would've noticed that it > > was used there, but it's always good to mention the rationale in the > > commit message so that it's more obvious why you're doin it. > > You absolutely right. I forgot to update the commit message. > > > > Since there is not yet any clock driver the initial device tree for the TH1520 > > > included the dummy apb_clk that two of the pinctrl blocks derive their clock > > > from, but not the "aonsys" clock needed by the "always-on" pinctrl. I thought > > > it was better to add this dummy clock with the only (so far) user of it, but if > > > you have a better idea, let me know. > > > > No, that's fine. I was just wondering why there was an unmentioned set > > of clocks being added. If they're stubbed fixed clocks I dunno if it > > makes sense to add them to the board.dts/module.dtsi files though. Where > > do the initial values come from for the rates? Out of reset values or > > set by firmware that may vary from board to board? > > The vendor u-boot sets the PLLs different from the reset values. For now I > think it's the same code for every board using the Lichee Pi 4A module (and > probably also for the BeagleV Ahead), but it might still make sense to move the > freqency to the board instead of the module device tree. Yeah, think so. Only temporarily though, do you have a clue if anyone is working on the actual clock driver stuff? Seems pretty Deadge? https://lore.kernel.org/linux-clk/?q=th1520 Cheers, Conor. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 3/8] riscv: dts: thead: Add TH1520 pin control nodes 2024-01-09 17:34 ` Conor Dooley @ 2024-01-09 18:30 ` Drew Fustini 0 siblings, 0 replies; 25+ messages in thread From: Drew Fustini @ 2024-01-09 18:30 UTC (permalink / raw) To: Conor Dooley Cc: Emil Renner Berthing, Conor Dooley, linux-kernel, linux-gpio, devicetree, linux-riscv, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini On Tue, Jan 09, 2024 at 05:34:11PM +0000, Conor Dooley wrote: > On Tue, Jan 09, 2024 at 06:28:19AM -0800, Emil Renner Berthing wrote: > > Conor Dooley wrote: > > > On Tue, Jan 09, 2024 at 04:02:01AM -0800, Emil Renner Berthing wrote: > > > > Conor Dooley wrote: > > > > > On Wed, Jan 03, 2024 at 02:28:40PM +0100, Emil Renner Berthing wrote: > > > > > > Add nodes for pin controllers on the T-Head TH1520 RISC-V SoC. > > > > > > > > > > > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > > > > > --- > > > > > > .../boot/dts/thead/th1520-beaglev-ahead.dts | 4 ++++ > > > > > > .../dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++ > > > > > > arch/riscv/boot/dts/thead/th1520.dtsi | 24 +++++++++++++++++++ > > > > > > 3 files changed, 32 insertions(+) > > > > > > > > > > > > diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > > > > > > index 70e8042c8304..6c56318a8705 100644 > > > > > > --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > > > > > > +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > > > > > > @@ -44,6 +44,10 @@ &osc_32k { > > > > > > clock-frequency = <32768>; > > > > > > }; > > > > > > > > > > > > +&aonsys_clk { > > > > > > + clock-frequency = <73728000>; > > > > > > +}; > > > > > > + > > > > > > &apb_clk { > > > > > > clock-frequency = <62500000>; > > > > > > }; > > > > > > diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > > > > > > index a802ab110429..9865925be372 100644 > > > > > > --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > > > > > > +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > > > > > > @@ -25,6 +25,10 @@ &osc_32k { > > > > > > clock-frequency = <32768>; > > > > > > }; > > > > > > > > > > > > +&aonsys_clk { > > > > > > + clock-frequency = <73728000>; > > > > > > +}; > > > > > > + > > > > > > &apb_clk { > > > > > > clock-frequency = <62500000>; > > > > > > }; > > > > > > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi > > > > > > index ba4d2c673ac8..e65a306ff575 100644 > > > > > > --- a/arch/riscv/boot/dts/thead/th1520.dtsi > > > > > > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi > > > > > > @@ -134,6 +134,12 @@ osc_32k: 32k-oscillator { > > > > > > #clock-cells = <0>; > > > > > > }; > > > > > > > > > > > > + aonsys_clk: aonsys-clk { > > > > > > + compatible = "fixed-clock"; > > > > > > + clock-output-names = "aonsys_clk"; > > > > > > + #clock-cells = <0>; > > > > > > + }; > > > > > > > > > > Did this stuff sneak into this commit accidentally? > > > > > > > > Not really by accident no. It turns out the clock tree has gates for the bus > > > > clock of each pinctrl block and I think it's better to add this clock > > > > dependency to the bindings and driver up front. > > > > > > Maybe if I had looked a wee bit more deeply I would've noticed that it > > > was used there, but it's always good to mention the rationale in the > > > commit message so that it's more obvious why you're doin it. > > > > You absolutely right. I forgot to update the commit message. > > > > > > Since there is not yet any clock driver the initial device tree for the TH1520 > > > > included the dummy apb_clk that two of the pinctrl blocks derive their clock > > > > from, but not the "aonsys" clock needed by the "always-on" pinctrl. I thought > > > > it was better to add this dummy clock with the only (so far) user of it, but if > > > > you have a better idea, let me know. > > > > > > No, that's fine. I was just wondering why there was an unmentioned set > > > of clocks being added. If they're stubbed fixed clocks I dunno if it > > > makes sense to add them to the board.dts/module.dtsi files though. Where > > > do the initial values come from for the rates? Out of reset values or > > > set by firmware that may vary from board to board? > > > > The vendor u-boot sets the PLLs different from the reset values. For now I > > think it's the same code for every board using the Lichee Pi 4A module (and > > probably also for the BeagleV Ahead), but it might still make sense to move the > > freqency to the board instead of the module device tree. > > Yeah, think so. Only temporarily though, do you have a clue if anyone is > working on the actual clock driver stuff? Seems pretty Deadge? > https://lore.kernel.org/linux-clk/?q=th1520 Yes, I am working on it. Jisheng passed me his work-in-progress based on that original patch you linked to. I've been trying to work out an issue with the emmc clock but it seems timely to share what I currently have. I will post an RFC today. Thanks, Drew ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 4/8] riscv: dts: thead: Add TH1520 GPIO ranges 2024-01-03 13:28 [PATCH v2 0/8] Add T-Head TH1520 SoC pin control Emil Renner Berthing ` (2 preceding siblings ...) 2024-01-03 13:28 ` [PATCH v2 3/8] riscv: dts: thead: Add TH1520 pin control nodes Emil Renner Berthing @ 2024-01-03 13:28 ` Emil Renner Berthing 2024-01-03 13:28 ` [PATCH v2 5/8] riscv: dts: thead: Adjust TH1520 GPIO labels Emil Renner Berthing ` (5 subsequent siblings) 9 siblings, 0 replies; 25+ messages in thread From: Emil Renner Berthing @ 2024-01-03 13:28 UTC (permalink / raw) To: linux-kernel, linux-gpio, devicetree, linux-riscv Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini Add gpio-ranges properties to the TH1520 device tree, so user space can change basic pinconf settings for GPIOs and are not allowed to use pads already used by other functions. Adjust number of GPIOs available for the different controllers. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> --- arch/riscv/boot/dts/thead/th1520.dtsi | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index e65a306ff575..5eb841ba5124 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -223,6 +223,7 @@ portc: gpio-controller@0 { gpio-controller; #gpio-cells = <2>; ngpios = <32>; + gpio-ranges = <&padctrl0_apsys 0 0 32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; @@ -240,7 +241,8 @@ portd: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; - ngpios = <32>; + ngpios = <23>; + gpio-ranges = <&padctrl0_apsys 0 32 23>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; @@ -265,6 +267,7 @@ porta: gpio-controller@0 { gpio-controller; #gpio-cells = <2>; ngpios = <32>; + gpio-ranges = <&padctrl1_apsys 0 0 32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; @@ -282,7 +285,8 @@ portb: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; - ngpios = <32>; + ngpios = <31>; + gpio-ranges = <&padctrl1_apsys 0 32 31>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; @@ -424,7 +428,8 @@ porte: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; - ngpios = <32>; + ngpios = <16>; + gpio-ranges = <&padctrl_aosys 0 9 16>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; @@ -448,7 +453,8 @@ portf: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; - ngpios = <32>; + ngpios = <23>; + gpio-ranges = <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; -- 2.43.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 5/8] riscv: dts: thead: Adjust TH1520 GPIO labels 2024-01-03 13:28 [PATCH v2 0/8] Add T-Head TH1520 SoC pin control Emil Renner Berthing ` (3 preceding siblings ...) 2024-01-03 13:28 ` [PATCH v2 4/8] riscv: dts: thead: Add TH1520 GPIO ranges Emil Renner Berthing @ 2024-01-03 13:28 ` Emil Renner Berthing 2024-01-03 13:28 ` [PATCH v2 6/8] riscv: dts: thead: Add Lichee Pi 4M GPIO line names Emil Renner Berthing ` (4 subsequent siblings) 9 siblings, 0 replies; 25+ messages in thread From: Emil Renner Berthing @ 2024-01-03 13:28 UTC (permalink / raw) To: linux-kernel, linux-gpio, devicetree, linux-riscv Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini Adjust labels for the TH1520 GPIO controllers such that GPIOs can be referenced by the names used by the documentation. Eg. GPIO0_X -> <&gpio0 X Y> GPIO1_X -> <&gpio1 X Y> GPIO2_X -> <&gpio2 X Y> GPIO3_X -> <&gpio3 X Y> GPIO4_X -> <&gpio4 X Y> AOGPIO_X -> <&aogpio X Y> Remove labels for the parent GPIO devices that shouldn't need to be referenced. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> --- .../boot/dts/thead/th1520-beaglev-ahead.dts | 2 ++ .../boot/dts/thead/th1520-lichee-pi-4a.dts | 2 ++ arch/riscv/boot/dts/thead/th1520.dtsi | 24 +++++++++---------- 3 files changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts index 6c56318a8705..f1e8eaed487c 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -17,6 +17,8 @@ aliases { gpio1 = &gpio1; gpio2 = &gpio2; gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &aogpio; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts index 9a3884a73e13..0ae2c20d5641 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -14,6 +14,8 @@ aliases { gpio1 = &gpio1; gpio2 = &gpio2; gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &aogpio; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 5eb841ba5124..60225f122112 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -212,13 +212,13 @@ uart3: serial@ffe7f04000 { status = "disabled"; }; - gpio2: gpio@ffe7f34000 { + gpio@ffe7f34000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xe7f34000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; - portc: gpio-controller@0 { + gpio2: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; @@ -231,13 +231,13 @@ portc: gpio-controller@0 { }; }; - gpio3: gpio@ffe7f38000 { + gpio@ffe7f38000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xe7f38000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; - portd: gpio-controller@0 { + gpio3: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; @@ -256,13 +256,13 @@ padctrl1_apsys: pinctrl@ffe7f3c000 { clocks = <&apb_clk>; }; - gpio0: gpio@ffec005000 { + gpio@ffec005000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xec005000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; - porta: gpio-controller@0 { + gpio0: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; @@ -275,13 +275,13 @@ porta: gpio-controller@0 { }; }; - gpio1: gpio@ffec006000 { + gpio@ffec006000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xec006000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; - portb: gpio-controller@0 { + gpio1: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; @@ -418,13 +418,13 @@ timer7: timer@ffffc3303c { status = "disabled"; }; - ao_gpio0: gpio@fffff41000 { + gpio@fffff41000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xfff41000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; - porte: gpio-controller@0 { + aogpio: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; @@ -443,13 +443,13 @@ padctrl_aosys: pinctrl@fffff4a000 { clocks = <&aonsys_clk>; }; - ao_gpio1: gpio@fffff52000 { + gpio@fffff52000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xfff52000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; - portf: gpio-controller@0 { + gpio4: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; -- 2.43.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 6/8] riscv: dts: thead: Add Lichee Pi 4M GPIO line names 2024-01-03 13:28 [PATCH v2 0/8] Add T-Head TH1520 SoC pin control Emil Renner Berthing ` (4 preceding siblings ...) 2024-01-03 13:28 ` [PATCH v2 5/8] riscv: dts: thead: Adjust TH1520 GPIO labels Emil Renner Berthing @ 2024-01-03 13:28 ` Emil Renner Berthing 2024-01-03 13:28 ` [PATCH v2 7/8] riscv: dts: thead: Add TH1520 pinctrl settings for UART0 Emil Renner Berthing ` (3 subsequent siblings) 9 siblings, 0 replies; 25+ messages in thread From: Emil Renner Berthing @ 2024-01-03 13:28 UTC (permalink / raw) To: linux-kernel, linux-gpio, devicetree, linux-riscv Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini Add names for the GPIO00-GPIO14 lines of the SO-DIMM module. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> --- .../dts/thead/th1520-lichee-module-4a.dtsi | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 9865925be372..f674e5acd0f9 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -37,6 +37,45 @@ &uart_sclk { clock-frequency = <100000000>; }; +&aogpio { + gpio-line-names = "", "", "", + "GPIO00", + "GPIO04"; +}; + &dmac0 { status = "okay"; }; + +&gpio0 { + gpio-line-names = "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", + "GPIO07", + "GPIO08", + "", + "GPIO01", + "GPIO02"; +}; + +&gpio1 { + gpio-line-names = "", "", "", + "GPIO11", + "GPIO12", + "GPIO13", + "GPIO14", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", + "GPIO06"; +}; + +&gpio2 { + gpio-line-names = "GPIO03", + "GPIO05"; +}; + +&gpio3 { + gpio-line-names = "", "", + "GPIO09", + "GPIO10"; +}; -- 2.43.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 7/8] riscv: dts: thead: Add TH1520 pinctrl settings for UART0 2024-01-03 13:28 [PATCH v2 0/8] Add T-Head TH1520 SoC pin control Emil Renner Berthing ` (5 preceding siblings ...) 2024-01-03 13:28 ` [PATCH v2 6/8] riscv: dts: thead: Add Lichee Pi 4M GPIO line names Emil Renner Berthing @ 2024-01-03 13:28 ` Emil Renner Berthing 2024-01-03 13:28 ` [PATCH v2 8/8] riscv: dtb: thead: Add BeagleV Ahead LEDs Emil Renner Berthing ` (2 subsequent siblings) 9 siblings, 0 replies; 25+ messages in thread From: Emil Renner Berthing @ 2024-01-03 13:28 UTC (permalink / raw) To: linux-kernel, linux-gpio, devicetree, linux-riscv Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini Add pinctrl settings for UART0 used as the default debug console on both the Lichee Pi 4A and BeagleV Ahead boards. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> --- .../boot/dts/thead/th1520-beaglev-ahead.dts | 26 +++++++++++++++++++ .../boot/dts/thead/th1520-lichee-pi-4a.dts | 26 +++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts index f1e8eaed487c..c697a50ca9b1 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -62,6 +62,32 @@ &dmac0 { status = "okay"; }; +&padctrl0_apsys { + uart0_pins: uart0-0 { + tx-pins { + pins = "UART0_TXD"; + function = "uart"; + bias-disable; + drive-strength = <3>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pins = "UART0_RXD"; + function = "uart"; + bias-disable; + drive-strength = <1>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; +}; + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; status = "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts index 0ae2c20d5641..932838c55f90 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -29,6 +29,32 @@ chosen { }; }; +&padctrl0_apsys { + uart0_pins: uart0-0 { + tx-pins { + pins = "UART0_TXD"; + function = "uart"; + bias-disable; + drive-strength = <3>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pins = "UART0_RXD"; + function = "uart"; + bias-disable; + drive-strength = <1>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; +}; + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; status = "okay"; }; -- 2.43.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 8/8] riscv: dtb: thead: Add BeagleV Ahead LEDs 2024-01-03 13:28 [PATCH v2 0/8] Add T-Head TH1520 SoC pin control Emil Renner Berthing ` (6 preceding siblings ...) 2024-01-03 13:28 ` [PATCH v2 7/8] riscv: dts: thead: Add TH1520 pinctrl settings for UART0 Emil Renner Berthing @ 2024-01-03 13:28 ` Emil Renner Berthing 2024-02-06 19:25 ` [PATCH v2 0/8] Add T-Head TH1520 SoC pin control Conor Dooley 2024-05-06 14:28 ` Thomas Bonnefille 9 siblings, 0 replies; 25+ messages in thread From: Emil Renner Berthing @ 2024-01-03 13:28 UTC (permalink / raw) To: linux-kernel, linux-gpio, devicetree, linux-riscv Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini Add nodes for the 5 user controllable LEDs on the BeagleV Ahead board. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> --- .../boot/dts/thead/th1520-beaglev-ahead.dts | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts index c697a50ca9b1..0b309c770202 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -7,6 +7,8 @@ /dts-v1/; #include "th1520.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> / { model = "BeagleV Ahead"; @@ -34,7 +36,42 @@ chosen { memory@0 { device_type = "memory"; reg = <0x0 0x00000000 0x1 0x00000000>; + }; + leds { + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + compatible = "gpio-leds"; + + led-1 { + gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_BLUE>; + label = "led1"; + }; + + led-2 { + gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_BLUE>; + label = "led2"; + }; + + led-3 { + gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_BLUE>; + label = "led3"; + }; + + led-4 { + gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_BLUE>; + label = "led4"; + }; + + led-5 { + gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_BLUE>; + label = "led5"; + }; }; }; @@ -62,6 +99,24 @@ &dmac0 { status = "okay"; }; +&padctrl_aosys { + led_pins: led-0 { + led-pins { + pins = "AUDIO_PA8", /* GPIO4_8 */ + "AUDIO_PA9", /* GPIO4_9 */ + "AUDIO_PA10", /* GPIO4_10 */ + "AUDIO_PA11", /* GPIO4_11 */ + "AUDIO_PA12"; /* GPIO4_12 */ + function = "gpio"; + bias-disable; + drive-strength = <3>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; +}; + &padctrl0_apsys { uart0_pins: uart0-0 { tx-pins { -- 2.43.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v2 0/8] Add T-Head TH1520 SoC pin control 2024-01-03 13:28 [PATCH v2 0/8] Add T-Head TH1520 SoC pin control Emil Renner Berthing ` (7 preceding siblings ...) 2024-01-03 13:28 ` [PATCH v2 8/8] riscv: dtb: thead: Add BeagleV Ahead LEDs Emil Renner Berthing @ 2024-02-06 19:25 ` Conor Dooley 2024-05-06 14:28 ` Thomas Bonnefille 9 siblings, 0 replies; 25+ messages in thread From: Conor Dooley @ 2024-02-06 19:25 UTC (permalink / raw) To: Emil Renner Berthing Cc: linux-kernel, linux-gpio, devicetree, linux-riscv, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Guo Ren, Fu Wei, Paul Walmsley, Palmer Dabbelt, Drew Fustini [-- Attachment #1: Type: text/plain, Size: 399 bytes --] On Wed, Jan 03, 2024 at 02:28:37PM +0100, Emil Renner Berthing wrote: > This adds a pin control driver for the T-Head TH1520 RISC-V SoC used on > the Lichee Pi 4A and BeagleV Ahead boards and updates the device trees > to make use of it. I'm gonna mark the bits of this that apply to me as "superseded", albeit somewhat preemptive, since you'll need to resubmit the bindings patch. Cheers, Conor. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 0/8] Add T-Head TH1520 SoC pin control 2024-01-03 13:28 [PATCH v2 0/8] Add T-Head TH1520 SoC pin control Emil Renner Berthing ` (8 preceding siblings ...) 2024-02-06 19:25 ` [PATCH v2 0/8] Add T-Head TH1520 SoC pin control Conor Dooley @ 2024-05-06 14:28 ` Thomas Bonnefille 9 siblings, 0 replies; 25+ messages in thread From: Thomas Bonnefille @ 2024-05-06 14:28 UTC (permalink / raw) To: emil.renner.berthing Cc: conor+dt, devicetree, dfustini, guoren, jszhang, krzysztof.kozlowski+dt, linus.walleij, linux-gpio, linux-kernel, linux-riscv, palmer, paul.walmsley, robh+dt, wefu, Thomas Petazzoni, Miquel Raynal Hello, Thanks for this series, it works with the I2C and the PWM. Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com> Thomas ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 0/8] pinctrl: Add T-Head TH1520 SoC pin controllers
@ 2024-09-15 2:40 Drew Fustini
2024-09-15 2:40 ` [PATCH v2 3/8] riscv: dts: thead: Add TH1520 pin control nodes Drew Fustini
0 siblings, 1 reply; 25+ messages in thread
From: Drew Fustini @ 2024-09-15 2:40 UTC (permalink / raw)
To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Emil Renner Berthing,
Thomas Bonnefille, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini
This adds a pin control driver created by Emil for the T-Head TH1520
RISC-V SoC used on the Lichee Pi 4A and BeagleV Ahead boards and updates
the device trees to make use of it.
Emil's series from January used separate compatibles for each pin
controller instance. Rob did not think this was appropriate because the
programming model is the same for each instance.
This series takes a different approach by adding a thead,pad-group
device tree property to select the pad group for a given pin controller
instance.
Changes in v2:
- Add thead,pad-group device tree property
- Change driver to use the thead,pad-group property instead of the unit
address to identify the pad group of the pin controller being probed
- Return -EINVAL if no pin group can be determined during probe. In v1,
there was a bug that instead returned an unitialized variable
- Link to v1: https://lore.kernel.org/r/20240902-th1520-pinctrl-v1-0-639bf83ef50a@tenstorrent.com
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
Emil Renner Berthing (8):
dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings
pinctrl: Add driver for the T-Head TH1520 SoC
riscv: dts: thead: Add TH1520 pin control nodes
riscv: dts: thead: Add TH1520 GPIO ranges
riscv: dts: thead: Adjust TH1520 GPIO labels
riscv: dts: thead: Add Lichee Pi 4M GPIO line names
riscv: dts: thead: Add TH1520 pinctrl settings for UART0
riscv: dtb: thead: Add BeagleV Ahead LEDs
.../bindings/pinctrl/thead,th1520-pinctrl.yaml | 176 ++++
MAINTAINERS | 2 +
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 87 ++
.../boot/dts/thead/th1520-lichee-module-4a.dtsi | 43 +
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 28 +
arch/riscv/boot/dts/thead/th1520.dtsi | 65 +-
drivers/pinctrl/Kconfig | 13 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-th1520.c | 911 +++++++++++++++++++++
9 files changed, 1310 insertions(+), 16 deletions(-)
---
base-commit: 5be63fc19fcaa4c236b307420483578a56986a37
change-id: 20240902-th1520-pinctrl-d71de44acc66
Best regards,
--
Drew Fustini <dfustini@tenstorrent.com>
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH v2 3/8] riscv: dts: thead: Add TH1520 pin control nodes 2024-09-15 2:40 [PATCH v2 0/8] pinctrl: Add T-Head TH1520 SoC pin controllers Drew Fustini @ 2024-09-15 2:40 ` Drew Fustini 0 siblings, 0 replies; 25+ messages in thread From: Drew Fustini @ 2024-09-15 2:40 UTC (permalink / raw) To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Emil Renner Berthing, Thomas Bonnefille, Paul Walmsley, Palmer Dabbelt, Albert Ou Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini From: Emil Renner Berthing <emil.renner.berthing@canonical.com> Add nodes for pin controllers on the T-Head TH1520 RISC-V SoC. Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Drew Fustini <dfustini@tenstorrent.com> --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ++++ .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++ arch/riscv/boot/dts/thead/th1520.dtsi | 27 ++++++++++++++++++++++ 3 files changed, 35 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts index d9b4de9e4757..be85e3aee56e 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -44,6 +44,10 @@ &osc_32k { clock-frequency = <32768>; }; +&aonsys_clk { + clock-frequency = <73728000>; +}; + &apb_clk { clock-frequency = <62500000>; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 1365d3a512a3..530648ad64f6 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -25,6 +25,10 @@ &osc_32k { clock-frequency = <32768>; }; +&aonsys_clk { + clock-frequency = <73728000>; +}; + &apb_clk { clock-frequency = <62500000>; }; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 3c9974062c20..9367754eede8 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -215,6 +215,12 @@ osc_32k: 32k-oscillator { #clock-cells = <0>; }; + aonsys_clk: aonsys-clk { + compatible = "fixed-clock"; + clock-output-names = "aonsys_clk"; + #clock-cells = <0>; + }; + apb_clk: apb-clk-clock { compatible = "fixed-clock"; clock-output-names = "apb_clk"; @@ -357,6 +363,13 @@ portd: gpio-controller@0 { }; }; + padctrl1_apsys: pinctrl@ffe7f3c000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xff 0xe7f3c000 0x0 0x1000>; + clocks = <&apb_clk>; + thead,pad-group = <2>; + }; + gpio0: gpio@ffec005000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xec005000 0x0 0x1000>; @@ -393,6 +406,13 @@ portb: gpio-controller@0 { }; }; + padctrl0_apsys: pinctrl@ffec007000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xff 0xec007000 0x0 0x1000>; + clocks = <&apb_clk>; + thead,pad-group = <3>; + }; + uart2: serial@ffec010000 { compatible = "snps,dw-apb-uart"; reg = <0xff 0xec010000 0x0 0x4000>; @@ -529,6 +549,13 @@ porte: gpio-controller@0 { }; }; + padctrl_aosys: pinctrl@fffff4a000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xff 0xfff4a000 0x0 0x2000>; + thead,pad-group = <1>; + clocks = <&aonsys_clk>; + }; + ao_gpio1: gpio@fffff52000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xfff52000 0x0 0x1000>; -- 2.34.1 ^ permalink raw reply related [flat|nested] 25+ messages in thread
end of thread, other threads:[~2024-09-15 2:42 UTC | newest] Thread overview: 25+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-01-03 13:28 [PATCH v2 0/8] Add T-Head TH1520 SoC pin control Emil Renner Berthing 2024-01-03 13:28 ` [PATCH v2 1/8] dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings Emil Renner Berthing 2024-01-15 17:36 ` Rob Herring 2024-05-17 12:48 ` Emil Renner Berthing 2024-07-01 12:33 ` Emil Renner Berthing 2024-07-03 13:53 ` Rob Herring 2024-07-03 19:19 ` Emil Renner Berthing 2024-01-03 13:28 ` [PATCH v2 2/8] pinctrl: Add driver for the T-Head TH1520 SoC Emil Renner Berthing 2024-01-27 23:02 ` Linus Walleij 2024-05-11 6:06 ` Andy Shevchenko 2024-01-03 13:28 ` [PATCH v2 3/8] riscv: dts: thead: Add TH1520 pin control nodes Emil Renner Berthing 2024-01-08 17:34 ` Conor Dooley 2024-01-09 12:02 ` Emil Renner Berthing 2024-01-09 13:04 ` Conor Dooley 2024-01-09 14:28 ` Emil Renner Berthing 2024-01-09 17:34 ` Conor Dooley 2024-01-09 18:30 ` Drew Fustini 2024-01-03 13:28 ` [PATCH v2 4/8] riscv: dts: thead: Add TH1520 GPIO ranges Emil Renner Berthing 2024-01-03 13:28 ` [PATCH v2 5/8] riscv: dts: thead: Adjust TH1520 GPIO labels Emil Renner Berthing 2024-01-03 13:28 ` [PATCH v2 6/8] riscv: dts: thead: Add Lichee Pi 4M GPIO line names Emil Renner Berthing 2024-01-03 13:28 ` [PATCH v2 7/8] riscv: dts: thead: Add TH1520 pinctrl settings for UART0 Emil Renner Berthing 2024-01-03 13:28 ` [PATCH v2 8/8] riscv: dtb: thead: Add BeagleV Ahead LEDs Emil Renner Berthing 2024-02-06 19:25 ` [PATCH v2 0/8] Add T-Head TH1520 SoC pin control Conor Dooley 2024-05-06 14:28 ` Thomas Bonnefille -- strict thread matches above, loose matches on Subject: below -- 2024-09-15 2:40 [PATCH v2 0/8] pinctrl: Add T-Head TH1520 SoC pin controllers Drew Fustini 2024-09-15 2:40 ` [PATCH v2 3/8] riscv: dts: thead: Add TH1520 pin control nodes Drew Fustini
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