[PATCH 0/6] Add support for the RZ/V2H Interrupt Control Unit

[PATCH 0/6] Add support for the RZ/V2H Interrupt Control Unit

[Fabrizio Castro]

Dear All,

This series adds whatever is required for supporting NMI, IRQ, and
TINT interrupts to the Renesas RZ/V2H SoC.

Thanks,
Fab

Fabrizio Castro (6):
  dt-bindings: pinctrl: renesas: rzg2l-pinctrl: Add interrupt-parent
  pinctrl: renesas: rzg2l: Remove RZG2L_TINT_IRQ_START_INDEX
  dt-bindings: interrupt-controller: Add Renesas RZ/V2H(P) Interrupt
    Controller
  clk: renesas: r9a09g057: Add clock and reset entries for ICU
  irqchip: Add RZ/V2H(P) Interrupt Control Unit (ICU) driver
  arm64: dts: renesas: r9a09g057: Add ICU node

 .../renesas,rzv2h-icu.yaml                    | 278 ++++++++++
 .../pinctrl/renesas,rzg2l-pinctrl.yaml        |   4 +
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi    |  88 +++
 drivers/clk/renesas/r9a09g057-cpg.c           |   2 +
 drivers/irqchip/Kconfig                       |   7 +
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-renesas-rzv2h.c           | 517 ++++++++++++++++++
 drivers/pinctrl/renesas/pinctrl-rzg2l.c       |   8 +-
 drivers/soc/renesas/Kconfig                   |   1 +
 .../interrupt-controller/icu-rzv2h.h          |  48 ++
 10 files changed, 952 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
 create mode 100644 drivers/irqchip/irq-renesas-rzv2h.c
 create mode 100644 include/dt-bindings/interrupt-controller/icu-rzv2h.h

-- 
2.34.1

[PATCH 1/6] dt-bindings: pinctrl: renesas: rzg2l-pinctrl: Add interrupt-parent

[Fabrizio Castro]

All the platforms from the renesas,rzg2l-pinctrl.yaml binding
actually require the interrupt-parent property. Add it.

Fixes: 35c37efd1273 ("dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the properties to handle GPIO IRQ")
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
 .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml    | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index 56d90c8e1fa3..10f724e87ae7 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -51,6 +51,8 @@ properties:
 
   interrupt-controller: true
 
+  interrupt-parent: true
+
   '#interrupt-cells':
     const: 2
     description:
@@ -155,6 +157,7 @@ required:
   - '#gpio-cells'
   - gpio-ranges
   - interrupt-controller
+  - interrupt-parent
   - '#interrupt-cells'
   - clocks
   - power-domains
@@ -174,6 +177,7 @@ examples:
             gpio-ranges = <&pinctrl 0 0 392>;
             interrupt-controller;
             #interrupt-cells = <2>;
+            interrupt-parent = <&irqc>;
             clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
             resets = <&cpg R9A07G044_GPIO_RSTN>,
                      <&cpg R9A07G044_GPIO_PORT_RESETN>,
-- 
2.34.1

Re: [PATCH 1/6] dt-bindings: pinctrl: renesas: rzg2l-pinctrl: Add interrupt-parent

[Rob Herring (Arm)]

On Tue, 17 Sep 2024 18:32:44 +0100, Fabrizio Castro wrote:
> All the platforms from the renesas,rzg2l-pinctrl.yaml binding
> actually require the interrupt-parent property. Add it.
> 
> Fixes: 35c37efd1273 ("dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the properties to handle GPIO IRQ")
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> ---
>  .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml    | 4 ++++
>  1 file changed, 4 insertions(+)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.example.dtb: pinctrl@11030000: 'interrupt-parent' is a required property
	from schema $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240917173249.158920-2-fabrizio.castro.jz@renesas.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH 1/6] dt-bindings: pinctrl: renesas: rzg2l-pinctrl: Add interrupt-parent

[Rob Herring]

On Tue, Sep 17, 2024 at 06:32:44PM +0100, Fabrizio Castro wrote:
> All the platforms from the renesas,rzg2l-pinctrl.yaml binding
> actually require the interrupt-parent property. Add it.

But they don't require it. It *never* is required. If interrupt-parent 
is not found in a node, the parent will be checked.

The check failure is because the example extraction has to play with 
interrupt-parent to make interrupt parsing work.

> 
> Fixes: 35c37efd1273 ("dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the properties to handle GPIO IRQ")
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> ---
>  .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml    | 4 ++++
>  1 file changed, 4 insertions(+)
> 

RE: [PATCH 1/6] dt-bindings: pinctrl: renesas: rzg2l-pinctrl: Add interrupt-parent

[Fabrizio Castro]

Hi Rob,

Thank you for your reply.

> From: Rob Herring <robh@kernel.org>
> Sent: Tuesday, September 17, 2024 11:15 PM
> To: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> Subject: Re: [PATCH 1/6] dt-bindings: pinctrl: renesas: rzg2l-pinctrl: Add interrupt-parent
> 
> On Tue, Sep 17, 2024 at 06:32:44PM +0100, Fabrizio Castro wrote:
> > All the platforms from the renesas,rzg2l-pinctrl.yaml binding actually
> > require the interrupt-parent property. Add it.
> 
> But they don't require it. It *never* is required. If interrupt-parent is not found in a node, the
> parent will be checked.

Indeed.

I am dropping this patch.

> 
> The check failure is because the example extraction has to play with interrupt-parent to make interrupt
> parsing work.

Gotcha.

Thank you for the explanation.

Cheers,
Fab

> 
> >
> > Fixes: 35c37efd1273 ("dt-bindings: pinctrl: renesas,rzg2l-pinctrl:
> > Document the properties to handle GPIO IRQ")
> > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> > ---
> >  .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml    | 4 ++++
> >  1 file changed, 4 insertions(+)
> >

[PATCH 2/6] pinctrl: renesas: rzg2l: Remove RZG2L_TINT_IRQ_START_INDEX

[Fabrizio Castro]

The RZ/V2H(P) has 16 IRQ interrupts, while every other platforms
has 8, and this affects the start index of TINT interrupts
(1 + 16 = 17, rather than 1 + 8 = 9).
Macro RZG2L_TINT_IRQ_START_INDEX cannot work anymore, replace
it with a new member within struct rzg2l_hwcfg.

Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 5a403915fed2..0aba75dce229 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -168,7 +168,6 @@
 #define RZG2L_PIN_ID_TO_PIN(id)		((id) % RZG2L_PINS_PER_PORT)
 
 #define RZG2L_TINT_MAX_INTERRUPT	32
-#define RZG2L_TINT_IRQ_START_INDEX	9
 #define RZG2L_PACK_HWIRQ(t, i)		(((t) << 16) | (i))
 
 /* Custom pinconf parameters */
@@ -251,6 +250,7 @@ enum rzg2l_iolh_index {
  * @func_base: base number for port function (see register PFC)
  * @oen_max_pin: the maximum pin number supporting output enable
  * @oen_max_port: the maximum port number supporting output enable
+ * @tint_start_index: the start index for the TINT interrupts
  */
 struct rzg2l_hwcfg {
 	const struct rzg2l_register_offsets regs;
@@ -262,6 +262,7 @@ struct rzg2l_hwcfg {
 	u8 func_base;
 	u8 oen_max_pin;
 	u8 oen_max_port;
+	unsigned int tint_start_index;
 };
 
 struct rzg2l_dedicated_configs {
@@ -2379,7 +2380,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
 
 	rzg2l_gpio_irq_endisable(pctrl, child, true);
 	pctrl->hwirq[irq] = child;
-	irq += RZG2L_TINT_IRQ_START_INDEX;
+	irq += pctrl->data->hwcfg->tint_start_index;
 
 	/* All these interrupts are level high in the CPU */
 	*parent_type = IRQ_TYPE_LEVEL_HIGH;
@@ -3035,6 +3036,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = {
 	},
 	.iolh_groupb_oi = { 100, 66, 50, 33, },
 	.oen_max_pin = 0,
+	.tint_start_index = 9,
 };
 
 static const struct rzg2l_hwcfg rzg3s_hwcfg = {
@@ -3067,12 +3069,14 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = {
 	.func_base = 1,
 	.oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */
 	.oen_max_port = 7, /* P7_1 is the maximum OEN port. */
+	.tint_start_index = 9,
 };
 
 static const struct rzg2l_hwcfg rzv2h_hwcfg = {
 	.regs = {
 		.pwpr = 0x3c04,
 	},
+	.tint_start_index = 17,
 };
 
 static struct rzg2l_pinctrl_data r9a07g043_data = {
-- 
2.34.1