From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EAF71E885C; Fri, 31 Jan 2025 16:32:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738341176; cv=none; b=KZLWavot3qZsAKmGSvXFP73EU61NXarkDEAyuc01IUCUhehkUStOstGSvo9axRBwZb7/GBn106PC0e+ZvlMSde7QjPdivh3x186orXB50KuoJdVs/ANmXJ53Z00atCCpSZgggiQB6u568SZA/jnLZNGdURR0NLPIavbeYU378pU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738341176; c=relaxed/simple; bh=5RDZtd57dB3UJYPOXoPH8EL9g2Cfkwd18mHmUkQWA1E=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dIapwylEDPeheuJRtJ5e/ATFCwE8RGXVv9ADEE9p+aL5QMOSAqiBMhCMZWLFvDzw5NojmszpilWIWduJsbfTQkTKzEq2jgBB2DBw7fNtszNRibQWKdaQVVpX3KWGgKHOAIyX3it+QhLdU7DT91zmu19vV2fb9lFFppIsHihOwk0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4Yl1bP1gXVz6D9H9; Sat, 1 Feb 2025 00:30:41 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id C5C2D140155; Sat, 1 Feb 2025 00:32:49 +0800 (CST) Received: from localhost (10.195.244.178) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 31 Jan 2025 17:32:47 +0100 Date: Fri, 31 Jan 2025 16:32:46 +0000 From: Jonathan Cameron To: Geert Uytterhoeven CC: Michael Turquette , Stephen Boyd , Nicolas Ferre , "Alexandre Belloni" , Claudiu Beznea , Giovanni Cabiddu , Herbert Xu , "David S . Miller" , Linus Walleij , "Bartosz Golaszewski" , Joel Stanley , Andrew Jeffery , Crt Mori , Jonathan Cameron , Lars-Peter Clausen , Jacky Huang , Shan-Chun Hung , Yury Norov , Rasmus Villemoes , Jaroslav Kysela , Takashi Iwai , "Johannes Berg" , Jakub Kicinski , "Alex Elder" , , , , , , , , , , Subject: Re: [PATCH treewide v2 1/3] bitfield: Add non-constant field_{prep,get}() helpers Message-ID: <20250131163246.00000077@huawei.com> In-Reply-To: <1824412519cb8791ab428065116927ee7b77cf35.1738329459.git.geert+renesas@glider.be> References: <1824412519cb8791ab428065116927ee7b77cf35.1738329459.git.geert+renesas@glider.be> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: lhrpeml100005.china.huawei.com (7.191.160.25) To frapeml500008.china.huawei.com (7.182.85.71) On Fri, 31 Jan 2025 14:46:51 +0100 Geert Uytterhoeven wrote: > The existing FIELD_{GET,PREP}() macros are limited to compile-time > constants. However, it is very common to prepare or extract bitfield > elements where the bitfield mask is not a compile-time constant. > > To avoid this limitation, the AT91 clock driver and several other > drivers already have their own non-const field_{prep,get}() macros. > Make them available for general use by consolidating them in > , and improve them slightly: > 1. Avoid evaluating macro parameters more than once, > 2. Replace "ffs() - 1" by "__ffs()", > 3. Support 64-bit use on 32-bit architectures. > > Signed-off-by: Geert Uytterhoeven For the IIO one. Acked-by: Jonathan Cameron > --- > v2: > - Cast val resp. reg to the mask type, > - Fix 64-bit use on 32-bit architectures, > - Convert new upstream users: > - drivers/crypto/intel/qat/qat_common/adf_gen4_pm_debugfs.c > - drivers/gpio/gpio-aspeed.c > - drivers/iio/temperature/mlx90614.c > - drivers/pinctrl/nuvoton/pinctrl-ma35.c > - sound/usb/mixer_quirks.c > - Convert new user queued in renesas-devel for v6.15: > - drivers/soc/renesas/rz-sysc.c > --- > drivers/clk/at91/clk-peripheral.c | 1 + > drivers/clk/at91/pmc.h | 3 -- > .../qat/qat_common/adf_gen4_pm_debugfs.c | 8 +---- > drivers/gpio/gpio-aspeed.c | 5 +-- > drivers/iio/temperature/mlx90614.c | 5 +-- > drivers/pinctrl/nuvoton/pinctrl-ma35.c | 4 --- > drivers/soc/renesas/rz-sysc.c | 3 +- > include/linux/bitfield.h | 34 +++++++++++++++++++ > sound/usb/mixer_quirks.c | 4 --- > 9 files changed, 39 insertions(+), 28 deletions(-) > > diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c > index c173a44c800aa8cc..60208bdc3fe4797e 100644 > --- a/drivers/clk/at91/clk-peripheral.c > +++ b/drivers/clk/at91/clk-peripheral.c > @@ -3,6 +3,7 @@ > * Copyright (C) 2013 Boris BREZILLON > */ > > +#include > #include > #include > #include > diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h > index 4fb29ca111f7d427..3838e4f7df2d4a70 100644 > --- a/drivers/clk/at91/pmc.h > +++ b/drivers/clk/at91/pmc.h > @@ -116,9 +116,6 @@ struct at91_clk_pms { > unsigned int parent; > }; > > -#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) > -#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) > - > #define ndck(a, s) (a[s - 1].id + 1) > #define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1) > > diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen4_pm_debugfs.c b/drivers/crypto/intel/qat/qat_common/adf_gen4_pm_debugfs.c > index 2e4095c4c12c94f9..ebaa59e934178309 100644 > --- a/drivers/crypto/intel/qat/qat_common/adf_gen4_pm_debugfs.c > +++ b/drivers/crypto/intel/qat/qat_common/adf_gen4_pm_debugfs.c > @@ -1,5 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0-only > /* Copyright(c) 2023 Intel Corporation */ > +#include > #include > #include > #include > @@ -11,13 +12,6 @@ > #include "adf_gen4_pm.h" > #include "icp_qat_fw_init_admin.h" > > -/* > - * This is needed because a variable is used to index the mask at > - * pm_scnprint_table(), making it not compile time constant, so the compile > - * asserts from FIELD_GET() or u32_get_bits() won't be fulfilled. > - */ > -#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) > - > #define PM_INFO_MEMBER_OFF(member) \ > (offsetof(struct icp_qat_fw_init_admin_pm_info, member) / sizeof(u32)) > > diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c > index 40c1bd80f8b0434d..b45e4dd8d8e4f00a 100644 > --- a/drivers/gpio/gpio-aspeed.c > +++ b/drivers/gpio/gpio-aspeed.c > @@ -5,6 +5,7 @@ > * Joel Stanley > */ > > +#include > #include > #include > #include > @@ -30,10 +31,6 @@ > #include > #include "gpiolib.h" > > -/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ > -#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) > -#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) > - > #define GPIO_G7_IRQ_STS_BASE 0x100 > #define GPIO_G7_IRQ_STS_OFFSET(x) (GPIO_G7_IRQ_STS_BASE + (x) * 0x4) > #define GPIO_G7_CTRL_REG_BASE 0x180 > diff --git a/drivers/iio/temperature/mlx90614.c b/drivers/iio/temperature/mlx90614.c > index 740018d4b3dfb35e..c58dc59d4f570831 100644 > --- a/drivers/iio/temperature/mlx90614.c > +++ b/drivers/iio/temperature/mlx90614.c > @@ -22,6 +22,7 @@ > * the "wakeup" GPIO is not given, power management will be disabled. > */ > > +#include > #include > #include > #include > @@ -68,10 +69,6 @@ > #define MLX90614_CONST_SCALE 20 /* Scale in milliKelvin (0.02 * 1000) */ > #define MLX90614_CONST_FIR 0x7 /* Fixed value for FIR part of low pass filter */ > > -/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ > -#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) > -#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) > - > struct mlx_chip_info { > /* EEPROM offsets with 16-bit data, MSB first */ > /* emissivity correction coefficient */ > diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35.c b/drivers/pinctrl/nuvoton/pinctrl-ma35.c > index 59c4e7c6cddea127..3ba28faa8e1418a9 100644 > --- a/drivers/pinctrl/nuvoton/pinctrl-ma35.c > +++ b/drivers/pinctrl/nuvoton/pinctrl-ma35.c > @@ -81,10 +81,6 @@ > #define MVOLT_1800 0 > #define MVOLT_3300 1 > > -/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ > -#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) > -#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) > - > static const char * const gpio_group_name[] = { > "gpioa", "gpiob", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", > "gpioh", "gpioi", "gpioj", "gpiok", "gpiol", "gpiom", "gpion", > diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c > index 1c98da37b7d18745..917a029d849585cd 100644 > --- a/drivers/soc/renesas/rz-sysc.c > +++ b/drivers/soc/renesas/rz-sysc.c > @@ -5,6 +5,7 @@ > * Copyright (C) 2024 Renesas Electronics Corp. > */ > > +#include > #include > #include > #include > @@ -12,8 +13,6 @@ > > #include "rz-sysc.h" > > -#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) > - > /** > * struct rz_sysc - RZ SYSC private data structure > * @base: SYSC base address > diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h > index 63928f1732230700..c62324a9fcc81241 100644 > --- a/include/linux/bitfield.h > +++ b/include/linux/bitfield.h > @@ -203,4 +203,38 @@ __MAKE_OP(64) > #undef __MAKE_OP > #undef ____MAKE_OP > > +/** > + * field_prep() - prepare a bitfield element > + * @_mask: shifted mask defining the field's length and position > + * @_val: value to put in the field > + * > + * field_prep() masks and shifts up the value. The result should be > + * combined with other fields of the bitfield using logical OR. > + * Unlike FIELD_PREP(), @_mask is not limited to a compile-time constant. > + */ > +#define field_prep(_mask, _val) \ > + ({ \ > + typeof(_mask) __mask = (_mask); \ > + unsigned int __shift = sizeof(_mask) <= 4 ? \ > + __ffs(__mask) : __ffs64(__mask); \ > + (((typeof(_mask))(_val) << __shift) & (__mask)); \ > + }) > + > +/** > + * field_get() - extract a bitfield element > + * @_mask: shifted mask defining the field's length and position > + * @_reg: value of entire bitfield > + * > + * field_get() extracts the field specified by @_mask from the > + * bitfield passed in as @_reg by masking and shifting it down. > + * Unlike FIELD_GET(), @_mask is not limited to a compile-time constant. > + */ > +#define field_get(_mask, _reg) \ > + ({ \ > + typeof(_mask) __mask = _mask; \ > + unsigned int __shift = sizeof(_mask) <= 4 ? \ > + __ffs(__mask) : __ffs64(__mask); \ > + (typeof(_mask))(((_reg) & (__mask)) >> __shift); \ > + }) > + > #endif > diff --git a/sound/usb/mixer_quirks.c b/sound/usb/mixer_quirks.c > index 23fcd680167d0298..00ab811e4b11a573 100644 > --- a/sound/usb/mixer_quirks.c > +++ b/sound/usb/mixer_quirks.c > @@ -3109,10 +3109,6 @@ static int snd_bbfpro_controls_create(struct usb_mixer_interface *mixer) > #define RME_DIGIFACE_REGISTER(reg, mask) (((reg) << 16) | (mask)) > #define RME_DIGIFACE_INVERT BIT(31) > > -/* Nonconst helpers */ > -#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) > -#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) > - > static int snd_rme_digiface_write_reg(struct snd_kcontrol *kcontrol, int item, u16 mask, u16 val) > { > struct usb_mixer_elem_list *list = snd_kcontrol_chip(kcontrol);