* [PATCH 01/33] dt-bindings: hwinfo: samsung,exynos-chipid: add exynos7870-chipid compatible
2025-02-02 18:36 [PATCH 00/33] Add support for the Exynos7870 SoC, along with three devices Kaustabh Chakraborty
@ 2025-02-02 18:36 ` Kaustabh Chakraborty
2025-02-03 7:54 ` Krzysztof Kozlowski
2025-02-02 19:03 ` [PATCH 02/34] " Kaustabh Chakraborty
` (4 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Kaustabh Chakraborty @ 2025-02-02 18:36 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alim Akhtar,
Sylwester Nawrocki, Chanwoo Choi, Michael Turquette, Stephen Boyd,
Tomasz Figa, Linus Walleij, Greg Kroah-Hartman, Jiri Slaby,
Lee Jones, Liam Girdwood, Mark Brown, Vinod Koul,
Kishon Vijay Abraham I, Marek Szyprowski, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Andi Shyti, Ulf Hansson, Jaehoon Chung,
Vivek Gautam, Thinh Nguyen, Kees Cook, Tony Luck,
Guilherme G. Piccoli
Cc: Sergey Lisov, devicetree, linux-arm-kernel, linux-samsung-soc,
linux-kernel, linux-clk, linux-gpio, linux-serial, linux-phy,
linux-usb, dri-devel, linux-i2c, linux-mmc, linux-hardening,
Kaustabh Chakraborty
Add the compatible string "samsung,exynos7870-chipid" to the documentation,
with a fallback to "samsung,exynos4210-chipid".
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
---
Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml b/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml
index 385aac7161a0db9334a92d78a57a125f23ca1920..9105ad48563a42ecaeb3dbca37df734d5b93f52c 100644
--- a/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml
+++ b/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml
@@ -19,6 +19,7 @@ properties:
- enum:
- samsung,exynos5433-chipid
- samsung,exynos7-chipid
+ - samsung,exynos7870-chipid
- const: samsung,exynos4210-chipid
- items:
- enum:
--
2.48.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 01/33] dt-bindings: hwinfo: samsung,exynos-chipid: add exynos7870-chipid compatible
2025-02-02 18:36 ` [PATCH 01/33] dt-bindings: hwinfo: samsung,exynos-chipid: add exynos7870-chipid compatible Kaustabh Chakraborty
@ 2025-02-03 7:54 ` Krzysztof Kozlowski
0 siblings, 0 replies; 13+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-03 7:54 UTC (permalink / raw)
To: Kaustabh Chakraborty
Cc: Rob Herring, Conor Dooley, Alim Akhtar, Sylwester Nawrocki,
Chanwoo Choi, Michael Turquette, Stephen Boyd, Tomasz Figa,
Linus Walleij, Greg Kroah-Hartman, Jiri Slaby, Lee Jones,
Liam Girdwood, Mark Brown, Vinod Koul, Kishon Vijay Abraham I,
Marek Szyprowski, David Airlie, Simona Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Andi Shyti, Ulf Hansson,
Jaehoon Chung, Vivek Gautam, Thinh Nguyen, Kees Cook, Tony Luck,
Guilherme G. Piccoli, Sergey Lisov, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel, linux-clk, linux-gpio,
linux-serial, linux-phy, linux-usb, dri-devel, linux-i2c,
linux-mmc, linux-hardening
On Mon, Feb 03, 2025 at 12:06:34AM +0530, Kaustabh Chakraborty wrote:
> Add the compatible string "samsung,exynos7870-chipid" to the documentation,
> with a fallback to "samsung,exynos4210-chipid".
>
> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
> ---
> Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
That's mess, how could you have two same commits in Git log? The only
answer I see is that you did not create it on top of git repo. That's
not how you should work. Use either b4 or git format-patch
--cover-letter, not some other methods.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 02/34] dt-bindings: hwinfo: samsung,exynos-chipid: add exynos7870-chipid compatible
2025-02-02 18:36 [PATCH 00/33] Add support for the Exynos7870 SoC, along with three devices Kaustabh Chakraborty
2025-02-02 18:36 ` [PATCH 01/33] dt-bindings: hwinfo: samsung,exynos-chipid: add exynos7870-chipid compatible Kaustabh Chakraborty
@ 2025-02-02 19:03 ` Kaustabh Chakraborty
2025-02-03 7:53 ` Krzysztof Kozlowski
2025-02-02 19:04 ` [PATCH 03/34] dt-bindings: clock: add clock definitions for exynos7870 CMU Kaustabh Chakraborty
` (3 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Kaustabh Chakraborty @ 2025-02-02 19:03 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alim Akhtar,
Sylwester Nawrocki, Chanwoo Choi, Michael Turquette, Stephen Boyd,
Tomasz Figa, Linus Walleij, Greg Kroah-Hartman, Jiri Slaby,
Lee Jones, Liam Girdwood, Mark Brown, Vinod Koul,
Kishon Vijay Abraham I, Marek Szyprowski, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Andi Shyti, Ulf Hansson, Jaehoon Chung,
Vivek Gautam, Thinh Nguyen, Kees Cook, Tony Luck,
Guilherme G . Piccoli
Cc: Sergey Lisov, devicetree, linux-arm-kernel, linux-samsung-soc,
linux-kernel, linux-clk, linux-gpio, linux-serial, linux-phy,
linux-usb, dri-devel, linux-i2c, linux-mmc, linux-hardening,
Kaustabh Chakraborty
Add the compatible string "samsung,exynos7870-chipid" to the documentation,
with a fallback to "samsung,exynos4210-chipid".
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
---
.../devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml b/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml
index 385aac7161a0..9105ad48563a 100644
--- a/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml
+++ b/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml
@@ -19,6 +19,7 @@ properties:
- enum:
- samsung,exynos5433-chipid
- samsung,exynos7-chipid
+ - samsung,exynos7870-chipid
- const: samsung,exynos4210-chipid
- items:
- enum:
--
2.48.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 02/34] dt-bindings: hwinfo: samsung,exynos-chipid: add exynos7870-chipid compatible
2025-02-02 19:03 ` [PATCH 02/34] " Kaustabh Chakraborty
@ 2025-02-03 7:53 ` Krzysztof Kozlowski
0 siblings, 0 replies; 13+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-03 7:53 UTC (permalink / raw)
To: Kaustabh Chakraborty
Cc: Rob Herring, Conor Dooley, Alim Akhtar, Sylwester Nawrocki,
Chanwoo Choi, Michael Turquette, Stephen Boyd, Tomasz Figa,
Linus Walleij, Greg Kroah-Hartman, Jiri Slaby, Lee Jones,
Liam Girdwood, Mark Brown, Vinod Koul, Kishon Vijay Abraham I,
Marek Szyprowski, David Airlie, Simona Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Andi Shyti, Ulf Hansson,
Jaehoon Chung, Vivek Gautam, Thinh Nguyen, Kees Cook, Tony Luck,
Guilherme G . Piccoli, Sergey Lisov, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel, linux-clk, linux-gpio,
linux-serial, linux-phy, linux-usb, dri-devel, linux-i2c,
linux-mmc, linux-hardening
On Mon, Feb 03, 2025 at 12:33:53AM +0530, Kaustabh Chakraborty wrote:
> Add the compatible string "samsung,exynos7870-chipid" to the documentation,
> with a fallback to "samsung,exynos4210-chipid".
This we see from the diff. Say something not obvious about hardware
instead of repeating redudundantly subject and diff. Otherwise what you
said is equivalent in just few words: "Document Exynos7870 ChipID."
instead of two lines of text. Instead say whether device is or is not
compatible.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 03/34] dt-bindings: clock: add clock definitions for exynos7870 CMU
2025-02-02 18:36 [PATCH 00/33] Add support for the Exynos7870 SoC, along with three devices Kaustabh Chakraborty
2025-02-02 18:36 ` [PATCH 01/33] dt-bindings: hwinfo: samsung,exynos-chipid: add exynos7870-chipid compatible Kaustabh Chakraborty
2025-02-02 19:03 ` [PATCH 02/34] " Kaustabh Chakraborty
@ 2025-02-02 19:04 ` Kaustabh Chakraborty
2025-02-02 19:07 ` [PATCH 02/33] " Kaustabh Chakraborty
` (2 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Kaustabh Chakraborty @ 2025-02-02 19:04 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alim Akhtar,
Sylwester Nawrocki, Chanwoo Choi, Michael Turquette, Stephen Boyd,
Tomasz Figa, Linus Walleij, Greg Kroah-Hartman, Jiri Slaby,
Lee Jones, Liam Girdwood, Mark Brown, Vinod Koul,
Kishon Vijay Abraham I, Marek Szyprowski, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Andi Shyti, Ulf Hansson, Jaehoon Chung,
Vivek Gautam, Thinh Nguyen, Kees Cook, Tony Luck,
Guilherme G . Piccoli
Cc: Sergey Lisov, devicetree, linux-arm-kernel, linux-samsung-soc,
linux-kernel, linux-clk, linux-gpio, linux-serial, linux-phy,
linux-usb, dri-devel, linux-i2c, linux-mmc, linux-hardening,
Kaustabh Chakraborty
From: Sergey Lisov <sleirsgoevy@gmail.com>
Add unique identifiers for exynos7870 clocks for every bank. It adds all
clocks of CMU_MIF, CMU_DISPAUD, CMU_G3D, CMU_ISP, CMU_MFCMSCL, and
CMU_PERI.
Signed-off-by: Sergey Lisov <sleirsgoevy@gmail.com>
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
---
include/dt-bindings/clock/exynos7870.h | 324 +++++++++++++++++++++++++
1 file changed, 324 insertions(+)
create mode 100644 include/dt-bindings/clock/exynos7870.h
diff --git a/include/dt-bindings/clock/exynos7870.h b/include/dt-bindings/clock/exynos7870.h
new file mode 100644
index 000000000000..eab01948033f
--- /dev/null
+++ b/include/dt-bindings/clock/exynos7870.h
@@ -0,0 +1,324 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Sergey Lisov <sleirsgoevy@gmail.com>
+ *
+ * Device Tree binding constants for Exynos7870 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS7870_H
+#define _DT_BINDINGS_CLOCK_EXYNOS7870_H
+
+/* CMU_MIF */
+#define CLK_DOUT_MIF_APB 1
+#define CLK_DOUT_MIF_BUSD 2
+#define CLK_DOUT_MIF_CMU_DISPAUD_BUS 3
+#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_ECLK 4
+#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_VCLK 5
+#define CLK_DOUT_MIF_CMU_FSYS_BUS 6
+#define CLK_DOUT_MIF_CMU_FSYS_MMC0 7
+#define CLK_DOUT_MIF_CMU_FSYS_MMC1 8
+#define CLK_DOUT_MIF_CMU_FSYS_MMC2 9
+#define CLK_DOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 10
+#define CLK_DOUT_MIF_CMU_G3D_SWITCH 11
+#define CLK_DOUT_MIF_CMU_ISP_CAM 12
+#define CLK_DOUT_MIF_CMU_ISP_ISP 13
+#define CLK_DOUT_MIF_CMU_ISP_SENSOR0 14
+#define CLK_DOUT_MIF_CMU_ISP_SENSOR1 15
+#define CLK_DOUT_MIF_CMU_ISP_SENSOR2 16
+#define CLK_DOUT_MIF_CMU_ISP_VRA 17
+#define CLK_DOUT_MIF_CMU_MFCMSCL_MFC 18
+#define CLK_DOUT_MIF_CMU_MFCMSCL_MSCL 19
+#define CLK_DOUT_MIF_CMU_PERI_BUS 20
+#define CLK_DOUT_MIF_CMU_PERI_SPI0 21
+#define CLK_DOUT_MIF_CMU_PERI_SPI1 22
+#define CLK_DOUT_MIF_CMU_PERI_SPI2 23
+#define CLK_DOUT_MIF_CMU_PERI_SPI3 24
+#define CLK_DOUT_MIF_CMU_PERI_SPI4 25
+#define CLK_DOUT_MIF_CMU_PERI_UART0 26
+#define CLK_DOUT_MIF_CMU_PERI_UART1 27
+#define CLK_DOUT_MIF_CMU_PERI_UART2 28
+#define CLK_DOUT_MIF_HSI2C 29
+#define CLK_FOUT_MIF_BUS_PLL 30
+#define CLK_FOUT_MIF_MEDIA_PLL 31
+#define CLK_FOUT_MIF_MEM_PLL 32
+#define CLK_GOUT_MIF_CMU_DISPAUD_BUS 33
+#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK 34
+#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK 35
+#define CLK_GOUT_MIF_CMU_FSYS_BUS 36
+#define CLK_GOUT_MIF_CMU_FSYS_MMC0 37
+#define CLK_GOUT_MIF_CMU_FSYS_MMC1 38
+#define CLK_GOUT_MIF_CMU_FSYS_MMC2 39
+#define CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 40
+#define CLK_GOUT_MIF_CMU_G3D_SWITCH 41
+#define CLK_GOUT_MIF_CMU_ISP_CAM 42
+#define CLK_GOUT_MIF_CMU_ISP_ISP 43
+#define CLK_GOUT_MIF_CMU_ISP_SENSOR0 44
+#define CLK_GOUT_MIF_CMU_ISP_SENSOR1 45
+#define CLK_GOUT_MIF_CMU_ISP_SENSOR2 46
+#define CLK_GOUT_MIF_CMU_ISP_VRA 47
+#define CLK_GOUT_MIF_CMU_MFCMSCL_MFC 48
+#define CLK_GOUT_MIF_CMU_MFCMSCL_MSCL 49
+#define CLK_GOUT_MIF_CMU_PERI_BUS 50
+#define CLK_GOUT_MIF_CMU_PERI_SPI0 51
+#define CLK_GOUT_MIF_CMU_PERI_SPI1 52
+#define CLK_GOUT_MIF_CMU_PERI_SPI2 53
+#define CLK_GOUT_MIF_CMU_PERI_SPI3 54
+#define CLK_GOUT_MIF_CMU_PERI_SPI4 55
+#define CLK_GOUT_MIF_CMU_PERI_UART0 56
+#define CLK_GOUT_MIF_CMU_PERI_UART1 57
+#define CLK_GOUT_MIF_CMU_PERI_UART2 58
+#define CLK_GOUT_MIF_CP_PCLK_HSI2C 59
+#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_0 60
+#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_1 61
+#define CLK_GOUT_MIF_HSI2C_AP_PCLKM 62
+#define CLK_GOUT_MIF_HSI2C_AP_PCLKS 63
+#define CLK_GOUT_MIF_HSI2C_CP_PCLKM 64
+#define CLK_GOUT_MIF_HSI2C_CP_PCLKS 65
+#define CLK_GOUT_MIF_HSI2C_IPCLK 66
+#define CLK_GOUT_MIF_HSI2C_ITCLK 67
+#define CLK_GOUT_MIF_MUX_BUSD 68
+#define CLK_GOUT_MIF_MUX_BUS_PLL 69
+#define CLK_GOUT_MIF_MUX_BUS_PLL_CON 70
+#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_BUS 71
+#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_ECLK 72
+#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_VCLK 73
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_BUS 74
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC0 75
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC1 76
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC2 77
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK 78
+#define CLK_GOUT_MIF_MUX_CMU_ISP_CAM 79
+#define CLK_GOUT_MIF_MUX_CMU_ISP_ISP 80
+#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR0 81
+#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR1 82
+#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR2 83
+#define CLK_GOUT_MIF_MUX_CMU_ISP_VRA 84
+#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MFC 85
+#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MSCL 86
+#define CLK_GOUT_MIF_MUX_CMU_PERI_BUS 87
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI0 88
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI1 89
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI2 90
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI3 91
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI4 92
+#define CLK_GOUT_MIF_MUX_CMU_PERI_UART0 93
+#define CLK_GOUT_MIF_MUX_CMU_PERI_UART1 94
+#define CLK_GOUT_MIF_MUX_CMU_PERI_UART2 95
+#define CLK_GOUT_MIF_MUX_MEDIA_PLL 96
+#define CLK_GOUT_MIF_MUX_MEDIA_PLL_CON 97
+#define CLK_GOUT_MIF_MUX_MEM_PLL 98
+#define CLK_GOUT_MIF_MUX_MEM_PLL_CON 99
+#define CLK_GOUT_MIF_WRAP_ADC_IF_OSC_SYS 100
+#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S0 101
+#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S1 102
+#define CLK_MOUT_MIF_BUSD 103
+#define CLK_MOUT_MIF_CMU_DISPAUD_BUS 104
+#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_ECLK 105
+#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_VCLK 106
+#define CLK_MOUT_MIF_CMU_FSYS_BUS 107
+#define CLK_MOUT_MIF_CMU_FSYS_MMC0 108
+#define CLK_MOUT_MIF_CMU_FSYS_MMC1 109
+#define CLK_MOUT_MIF_CMU_FSYS_MMC2 110
+#define CLK_MOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 111
+#define CLK_MOUT_MIF_CMU_ISP_CAM 112
+#define CLK_MOUT_MIF_CMU_ISP_ISP 113
+#define CLK_MOUT_MIF_CMU_ISP_SENSOR0 114
+#define CLK_MOUT_MIF_CMU_ISP_SENSOR1 115
+#define CLK_MOUT_MIF_CMU_ISP_SENSOR2 116
+#define CLK_MOUT_MIF_CMU_ISP_VRA 117
+#define CLK_MOUT_MIF_CMU_MFCMSCL_MFC 118
+#define CLK_MOUT_MIF_CMU_MFCMSCL_MSCL 119
+#define CLK_MOUT_MIF_CMU_PERI_BUS 120
+#define CLK_MOUT_MIF_CMU_PERI_SPI0 121
+#define CLK_MOUT_MIF_CMU_PERI_SPI1 122
+#define CLK_MOUT_MIF_CMU_PERI_SPI2 123
+#define CLK_MOUT_MIF_CMU_PERI_SPI3 124
+#define CLK_MOUT_MIF_CMU_PERI_SPI4 125
+#define CLK_MOUT_MIF_CMU_PERI_UART0 126
+#define CLK_MOUT_MIF_CMU_PERI_UART1 127
+#define CLK_MOUT_MIF_CMU_PERI_UART2 128
+#define MIF_NR_CLK 129
+
+/* CMU_DISPAUD */
+#define CLK_DOUT_DISPAUD_APB 1
+#define CLK_DOUT_DISPAUD_DECON_ECLK 2
+#define CLK_DOUT_DISPAUD_DECON_VCLK 3
+#define CLK_DOUT_DISPAUD_MI2S 4
+#define CLK_DOUT_DISPAUD_MIXER 5
+#define CLK_FOUT_DISPAUD_AUD_PLL 6
+#define CLK_FOUT_DISPAUD_PLL 7
+#define CLK_GOUT_DISPAUD_APB_AUD 8
+#define CLK_GOUT_DISPAUD_APB_AUD_AMP 9
+#define CLK_GOUT_DISPAUD_APB_DISP 10
+#define CLK_GOUT_DISPAUD_BUS 11
+#define CLK_GOUT_DISPAUD_BUS_DISP 12
+#define CLK_GOUT_DISPAUD_BUS_PPMU 13
+#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN 14
+#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN 15
+#define CLK_GOUT_DISPAUD_CON_CP2AUD_BCK 16
+#define CLK_GOUT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S 17
+#define CLK_GOUT_DISPAUD_DECON_ECLK 18
+#define CLK_GOUT_DISPAUD_DECON_VCLK 19
+#define CLK_GOUT_DISPAUD_MI2S_AMP_I2SCODCLKI 20
+#define CLK_GOUT_DISPAUD_MI2S_AUD_I2SCODCLKI 21
+#define CLK_GOUT_DISPAUD_MIXER_AUD_SYSCLK 22
+#define CLK_GOUT_DISPAUD_MUX_AUD_PLL 23
+#define CLK_GOUT_DISPAUD_MUX_AUD_PLL_CON 24
+#define CLK_GOUT_DISPAUD_MUX_BUS_USER 25
+#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK 26
+#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK_USER 27
+#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK 28
+#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK_USER 29
+#define CLK_GOUT_DISPAUD_MUX_MI2S 30
+#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER 31
+#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON 32
+#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER 33
+#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON 34
+#define CLK_GOUT_DISPAUD_MUX_PLL 35
+#define CLK_GOUT_DISPAUD_MUX_PLL_CON 36
+#define CLK_MOUT_DISPAUD_BUS_USER 37
+#define CLK_MOUT_DISPAUD_DECON_ECLK 38
+#define CLK_MOUT_DISPAUD_DECON_ECLK_USER 39
+#define CLK_MOUT_DISPAUD_DECON_VCLK 40
+#define CLK_MOUT_DISPAUD_DECON_VCLK_USER 41
+#define CLK_MOUT_DISPAUD_MI2S 42
+#define DISPAUD_NR_CLK 43
+
+/* CMU_FSYS */
+#define CLK_FOUT_FSYS_USB_PLL 1
+#define CLK_GOUT_FSYS_BUSP3_HCLK 2
+#define CLK_GOUT_FSYS_MMC0_ACLK 3
+#define CLK_GOUT_FSYS_MMC1_ACLK 4
+#define CLK_GOUT_FSYS_MMC2_ACLK 5
+#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER 6
+#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON 7
+#define CLK_GOUT_FSYS_MUX_USB_PLL 8
+#define CLK_GOUT_FSYS_MUX_USB_PLL_CON 9
+#define CLK_GOUT_FSYS_PDMA0_ACLK_PDMA0 10
+#define CLK_GOUT_FSYS_PPMU_ACLK 11
+#define CLK_GOUT_FSYS_PPMU_PCLK 12
+#define CLK_GOUT_FSYS_SROMC_HCLK 13
+#define CLK_GOUT_FSYS_UPSIZER_BUS1_ACLK 14
+#define CLK_GOUT_FSYS_USB20DRD_ACLK_HSDRD 15
+#define CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL 16
+#define CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK 17
+#define FSYS_NR_CLK 18
+
+/* CMU_G3D */
+#define CLK_DOUT_G3D_APB 1
+#define CLK_DOUT_G3D_BUS 2
+#define CLK_FOUT_G3D_PLL 3
+#define CLK_GOUT_G3D_ASYNCS_D0_CLK 4
+#define CLK_GOUT_G3D_ASYNC_PCLKM 5
+#define CLK_GOUT_G3D_CLK 6
+#define CLK_GOUT_G3D_MUX 7
+#define CLK_GOUT_G3D_MUX_PLL 8
+#define CLK_GOUT_G3D_MUX_PLL_CON 9
+#define CLK_GOUT_G3D_MUX_SWITCH_USER 10
+#define CLK_GOUT_G3D_PPMU_ACLK 11
+#define CLK_GOUT_G3D_PPMU_PCLK 12
+#define CLK_GOUT_G3D_QE_ACLK 13
+#define CLK_GOUT_G3D_QE_PCLK 14
+#define CLK_GOUT_G3D_SYSREG_PCLK 15
+#define CLK_MOUT_G3D 16
+#define CLK_MOUT_G3D_SWITCH_USER 17
+#define G3D_NR_CLK 18
+
+/* CMU_ISP */
+#define CLK_DOUT_ISP_APB 1
+#define CLK_DOUT_ISP_CAM_HALF 2
+#define CLK_FOUT_ISP_PLL 3
+#define CLK_GOUT_ISP_CAM 4
+#define CLK_GOUT_ISP_CAM_HALF 5
+#define CLK_GOUT_ISP_ISPD 6
+#define CLK_GOUT_ISP_ISPD_PPMU 7
+#define CLK_GOUT_ISP_MUX_CAM 8
+#define CLK_GOUT_ISP_MUX_CAM_USER 9
+#define CLK_GOUT_ISP_MUX_ISP 10
+#define CLK_GOUT_ISP_MUX_ISPD 11
+#define CLK_GOUT_ISP_MUX_PLL 12
+#define CLK_GOUT_ISP_MUX_PLL_CON 13
+#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER 14
+#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON 15
+#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER 16
+#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON 17
+#define CLK_GOUT_ISP_MUX_USER 18
+#define CLK_GOUT_ISP_MUX_VRA 19
+#define CLK_GOUT_ISP_MUX_VRA_USER 20
+#define CLK_GOUT_ISP_VRA 21
+#define CLK_MOUT_ISP_CAM 22
+#define CLK_MOUT_ISP_CAM_USER 23
+#define CLK_MOUT_ISP_ISP 24
+#define CLK_MOUT_ISP_ISPD 25
+#define CLK_MOUT_ISP_USER 26
+#define CLK_MOUT_ISP_VRA 27
+#define CLK_MOUT_ISP_VRA_USER 28
+#define ISP_NR_CLK 29
+
+/* CMU_MFCMSCL */
+#define CLK_DOUT_MFCMSCL_APB 1
+#define CLK_GOUT_MFCMSCL_MFC 2
+#define CLK_GOUT_MFCMSCL_MSCL 3
+#define CLK_GOUT_MFCMSCL_MSCL_BI 4
+#define CLK_GOUT_MFCMSCL_MSCL_D 5
+#define CLK_GOUT_MFCMSCL_MSCL_JPEG 6
+#define CLK_GOUT_MFCMSCL_MSCL_POLY 7
+#define CLK_GOUT_MFCMSCL_MSCL_PPMU 8
+#define CLK_GOUT_MFCMSCL_MUX_MFC_USER 9
+#define CLK_GOUT_MFCMSCL_MUX_MSCL_USER 10
+#define CLK_MOUT_MFCMSCL_MFC_USER 11
+#define CLK_MOUT_MFCMSCL_MSCL_USER 12
+#define MFCMSCL_NR_CLK 13
+
+/* CMU_PERI */
+#define CLK_GOUT_PERI_BUSP1_PERIC0_HCLK 1
+#define CLK_GOUT_PERI_GPIO2_PCLK 2
+#define CLK_GOUT_PERI_GPIO5_PCLK 3
+#define CLK_GOUT_PERI_GPIO6_PCLK 4
+#define CLK_GOUT_PERI_GPIO7_PCLK 5
+#define CLK_GOUT_PERI_HSI2C1_IPCLK 6
+#define CLK_GOUT_PERI_HSI2C2_IPCLK 7
+#define CLK_GOUT_PERI_HSI2C3_IPCLK 8
+#define CLK_GOUT_PERI_HSI2C4_IPCLK 9
+#define CLK_GOUT_PERI_HSI2C5_IPCLK 10
+#define CLK_GOUT_PERI_HSI2C6_IPCLK 11
+#define CLK_GOUT_PERI_I2C0_PCLK 12
+#define CLK_GOUT_PERI_I2C1_PCLK 13
+#define CLK_GOUT_PERI_I2C2_PCLK 14
+#define CLK_GOUT_PERI_I2C3_PCLK 15
+#define CLK_GOUT_PERI_I2C4_PCLK 16
+#define CLK_GOUT_PERI_I2C5_PCLK 17
+#define CLK_GOUT_PERI_I2C6_PCLK 18
+#define CLK_GOUT_PERI_I2C7_PCLK 19
+#define CLK_GOUT_PERI_I2C8_PCLK 20
+#define CLK_GOUT_PERI_MCT_PCLK 21
+#define CLK_GOUT_PERI_PWM_MOTOR_OSCCLK 22
+#define CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0 23
+#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL0_PCLK 24
+#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL1_PCLK 25
+#define CLK_GOUT_PERI_SFRIF_TMU_PCLK 26
+#define CLK_GOUT_PERI_SPI0_PCLK 27
+#define CLK_GOUT_PERI_SPI0_SPI_EXT_CLK 28
+#define CLK_GOUT_PERI_SPI1_PCLK 29
+#define CLK_GOUT_PERI_SPI1_SPI_EXT_CLK 30
+#define CLK_GOUT_PERI_SPI2_PCLK 31
+#define CLK_GOUT_PERI_SPI2_SPI_EXT_CLK 32
+#define CLK_GOUT_PERI_SPI3_PCLK 33
+#define CLK_GOUT_PERI_SPI3_SPI_EXT_CLK 34
+#define CLK_GOUT_PERI_SPI4_PCLK 35
+#define CLK_GOUT_PERI_SPI4_SPI_EXT_CLK 36
+#define CLK_GOUT_PERI_TMU_CLK 37
+#define CLK_GOUT_PERI_TMU_CPUCL0_CLK 38
+#define CLK_GOUT_PERI_TMU_CPUCL1_CLK 39
+#define CLK_GOUT_PERI_UART0_EXT_UCLK 40
+#define CLK_GOUT_PERI_UART0_PCLK 41
+#define CLK_GOUT_PERI_UART1_EXT_UCLK 42
+#define CLK_GOUT_PERI_UART1_PCLK 43
+#define CLK_GOUT_PERI_UART2_EXT_UCLK 44
+#define CLK_GOUT_PERI_UART2_PCLK 45
+#define CLK_GOUT_PERI_WDT_CPUCL0_PCLK 46
+#define CLK_GOUT_PERI_WDT_CPUCL1_PCLK 47
+#define PERI_NR_CLK 48
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS7870_H */
--
2.48.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 02/33] dt-bindings: clock: add clock definitions for exynos7870 CMU
2025-02-02 18:36 [PATCH 00/33] Add support for the Exynos7870 SoC, along with three devices Kaustabh Chakraborty
` (2 preceding siblings ...)
2025-02-02 19:04 ` [PATCH 03/34] dt-bindings: clock: add clock definitions for exynos7870 CMU Kaustabh Chakraborty
@ 2025-02-02 19:07 ` Kaustabh Chakraborty
2025-02-03 7:54 ` Krzysztof Kozlowski
2025-02-02 19:09 ` [PATCH 03/33] dt-bindings: clock: document exynos7870 clock driver CMU bindings Kaustabh Chakraborty
2025-02-02 19:13 ` [PATCH 00/33] Add support for the Exynos7870 SoC, along with three devices Krzysztof Kozlowski
5 siblings, 1 reply; 13+ messages in thread
From: Kaustabh Chakraborty @ 2025-02-02 19:07 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alim Akhtar,
Sylwester Nawrocki, Chanwoo Choi, Michael Turquette, Stephen Boyd,
Tomasz Figa, Linus Walleij, Greg Kroah-Hartman, Jiri Slaby,
Lee Jones, Liam Girdwood, Mark Brown, Vinod Koul,
Kishon Vijay Abraham I, Marek Szyprowski, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Andi Shyti, Ulf Hansson, Jaehoon Chung,
Vivek Gautam, Thinh Nguyen, Kees Cook, Tony Luck,
Guilherme G . Piccoli
Cc: Sergey Lisov, devicetree, linux-arm-kernel, linux-samsung-soc,
linux-kernel, linux-clk, linux-gpio, linux-serial, linux-phy,
linux-usb, dri-devel, linux-i2c, linux-mmc, linux-hardening,
Kaustabh Chakraborty
From: Sergey Lisov <sleirsgoevy@gmail.com>
Add unique identifiers for exynos7870 clocks for every bank. It adds all
clocks of CMU_MIF, CMU_DISPAUD, CMU_G3D, CMU_ISP, CMU_MFCMSCL, and
CMU_PERI.
Signed-off-by: Sergey Lisov <sleirsgoevy@gmail.com>
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
---
include/dt-bindings/clock/exynos7870.h | 324 +++++++++++++++++++++++++
1 file changed, 324 insertions(+)
create mode 100644 include/dt-bindings/clock/exynos7870.h
diff --git a/include/dt-bindings/clock/exynos7870.h b/include/dt-bindings/clock/exynos7870.h
new file mode 100644
index 000000000000..eab01948033f
--- /dev/null
+++ b/include/dt-bindings/clock/exynos7870.h
@@ -0,0 +1,324 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Sergey Lisov <sleirsgoevy@gmail.com>
+ *
+ * Device Tree binding constants for Exynos7870 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS7870_H
+#define _DT_BINDINGS_CLOCK_EXYNOS7870_H
+
+/* CMU_MIF */
+#define CLK_DOUT_MIF_APB 1
+#define CLK_DOUT_MIF_BUSD 2
+#define CLK_DOUT_MIF_CMU_DISPAUD_BUS 3
+#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_ECLK 4
+#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_VCLK 5
+#define CLK_DOUT_MIF_CMU_FSYS_BUS 6
+#define CLK_DOUT_MIF_CMU_FSYS_MMC0 7
+#define CLK_DOUT_MIF_CMU_FSYS_MMC1 8
+#define CLK_DOUT_MIF_CMU_FSYS_MMC2 9
+#define CLK_DOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 10
+#define CLK_DOUT_MIF_CMU_G3D_SWITCH 11
+#define CLK_DOUT_MIF_CMU_ISP_CAM 12
+#define CLK_DOUT_MIF_CMU_ISP_ISP 13
+#define CLK_DOUT_MIF_CMU_ISP_SENSOR0 14
+#define CLK_DOUT_MIF_CMU_ISP_SENSOR1 15
+#define CLK_DOUT_MIF_CMU_ISP_SENSOR2 16
+#define CLK_DOUT_MIF_CMU_ISP_VRA 17
+#define CLK_DOUT_MIF_CMU_MFCMSCL_MFC 18
+#define CLK_DOUT_MIF_CMU_MFCMSCL_MSCL 19
+#define CLK_DOUT_MIF_CMU_PERI_BUS 20
+#define CLK_DOUT_MIF_CMU_PERI_SPI0 21
+#define CLK_DOUT_MIF_CMU_PERI_SPI1 22
+#define CLK_DOUT_MIF_CMU_PERI_SPI2 23
+#define CLK_DOUT_MIF_CMU_PERI_SPI3 24
+#define CLK_DOUT_MIF_CMU_PERI_SPI4 25
+#define CLK_DOUT_MIF_CMU_PERI_UART0 26
+#define CLK_DOUT_MIF_CMU_PERI_UART1 27
+#define CLK_DOUT_MIF_CMU_PERI_UART2 28
+#define CLK_DOUT_MIF_HSI2C 29
+#define CLK_FOUT_MIF_BUS_PLL 30
+#define CLK_FOUT_MIF_MEDIA_PLL 31
+#define CLK_FOUT_MIF_MEM_PLL 32
+#define CLK_GOUT_MIF_CMU_DISPAUD_BUS 33
+#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK 34
+#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK 35
+#define CLK_GOUT_MIF_CMU_FSYS_BUS 36
+#define CLK_GOUT_MIF_CMU_FSYS_MMC0 37
+#define CLK_GOUT_MIF_CMU_FSYS_MMC1 38
+#define CLK_GOUT_MIF_CMU_FSYS_MMC2 39
+#define CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 40
+#define CLK_GOUT_MIF_CMU_G3D_SWITCH 41
+#define CLK_GOUT_MIF_CMU_ISP_CAM 42
+#define CLK_GOUT_MIF_CMU_ISP_ISP 43
+#define CLK_GOUT_MIF_CMU_ISP_SENSOR0 44
+#define CLK_GOUT_MIF_CMU_ISP_SENSOR1 45
+#define CLK_GOUT_MIF_CMU_ISP_SENSOR2 46
+#define CLK_GOUT_MIF_CMU_ISP_VRA 47
+#define CLK_GOUT_MIF_CMU_MFCMSCL_MFC 48
+#define CLK_GOUT_MIF_CMU_MFCMSCL_MSCL 49
+#define CLK_GOUT_MIF_CMU_PERI_BUS 50
+#define CLK_GOUT_MIF_CMU_PERI_SPI0 51
+#define CLK_GOUT_MIF_CMU_PERI_SPI1 52
+#define CLK_GOUT_MIF_CMU_PERI_SPI2 53
+#define CLK_GOUT_MIF_CMU_PERI_SPI3 54
+#define CLK_GOUT_MIF_CMU_PERI_SPI4 55
+#define CLK_GOUT_MIF_CMU_PERI_UART0 56
+#define CLK_GOUT_MIF_CMU_PERI_UART1 57
+#define CLK_GOUT_MIF_CMU_PERI_UART2 58
+#define CLK_GOUT_MIF_CP_PCLK_HSI2C 59
+#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_0 60
+#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_1 61
+#define CLK_GOUT_MIF_HSI2C_AP_PCLKM 62
+#define CLK_GOUT_MIF_HSI2C_AP_PCLKS 63
+#define CLK_GOUT_MIF_HSI2C_CP_PCLKM 64
+#define CLK_GOUT_MIF_HSI2C_CP_PCLKS 65
+#define CLK_GOUT_MIF_HSI2C_IPCLK 66
+#define CLK_GOUT_MIF_HSI2C_ITCLK 67
+#define CLK_GOUT_MIF_MUX_BUSD 68
+#define CLK_GOUT_MIF_MUX_BUS_PLL 69
+#define CLK_GOUT_MIF_MUX_BUS_PLL_CON 70
+#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_BUS 71
+#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_ECLK 72
+#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_VCLK 73
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_BUS 74
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC0 75
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC1 76
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC2 77
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK 78
+#define CLK_GOUT_MIF_MUX_CMU_ISP_CAM 79
+#define CLK_GOUT_MIF_MUX_CMU_ISP_ISP 80
+#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR0 81
+#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR1 82
+#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR2 83
+#define CLK_GOUT_MIF_MUX_CMU_ISP_VRA 84
+#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MFC 85
+#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MSCL 86
+#define CLK_GOUT_MIF_MUX_CMU_PERI_BUS 87
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI0 88
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI1 89
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI2 90
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI3 91
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI4 92
+#define CLK_GOUT_MIF_MUX_CMU_PERI_UART0 93
+#define CLK_GOUT_MIF_MUX_CMU_PERI_UART1 94
+#define CLK_GOUT_MIF_MUX_CMU_PERI_UART2 95
+#define CLK_GOUT_MIF_MUX_MEDIA_PLL 96
+#define CLK_GOUT_MIF_MUX_MEDIA_PLL_CON 97
+#define CLK_GOUT_MIF_MUX_MEM_PLL 98
+#define CLK_GOUT_MIF_MUX_MEM_PLL_CON 99
+#define CLK_GOUT_MIF_WRAP_ADC_IF_OSC_SYS 100
+#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S0 101
+#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S1 102
+#define CLK_MOUT_MIF_BUSD 103
+#define CLK_MOUT_MIF_CMU_DISPAUD_BUS 104
+#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_ECLK 105
+#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_VCLK 106
+#define CLK_MOUT_MIF_CMU_FSYS_BUS 107
+#define CLK_MOUT_MIF_CMU_FSYS_MMC0 108
+#define CLK_MOUT_MIF_CMU_FSYS_MMC1 109
+#define CLK_MOUT_MIF_CMU_FSYS_MMC2 110
+#define CLK_MOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 111
+#define CLK_MOUT_MIF_CMU_ISP_CAM 112
+#define CLK_MOUT_MIF_CMU_ISP_ISP 113
+#define CLK_MOUT_MIF_CMU_ISP_SENSOR0 114
+#define CLK_MOUT_MIF_CMU_ISP_SENSOR1 115
+#define CLK_MOUT_MIF_CMU_ISP_SENSOR2 116
+#define CLK_MOUT_MIF_CMU_ISP_VRA 117
+#define CLK_MOUT_MIF_CMU_MFCMSCL_MFC 118
+#define CLK_MOUT_MIF_CMU_MFCMSCL_MSCL 119
+#define CLK_MOUT_MIF_CMU_PERI_BUS 120
+#define CLK_MOUT_MIF_CMU_PERI_SPI0 121
+#define CLK_MOUT_MIF_CMU_PERI_SPI1 122
+#define CLK_MOUT_MIF_CMU_PERI_SPI2 123
+#define CLK_MOUT_MIF_CMU_PERI_SPI3 124
+#define CLK_MOUT_MIF_CMU_PERI_SPI4 125
+#define CLK_MOUT_MIF_CMU_PERI_UART0 126
+#define CLK_MOUT_MIF_CMU_PERI_UART1 127
+#define CLK_MOUT_MIF_CMU_PERI_UART2 128
+#define MIF_NR_CLK 129
+
+/* CMU_DISPAUD */
+#define CLK_DOUT_DISPAUD_APB 1
+#define CLK_DOUT_DISPAUD_DECON_ECLK 2
+#define CLK_DOUT_DISPAUD_DECON_VCLK 3
+#define CLK_DOUT_DISPAUD_MI2S 4
+#define CLK_DOUT_DISPAUD_MIXER 5
+#define CLK_FOUT_DISPAUD_AUD_PLL 6
+#define CLK_FOUT_DISPAUD_PLL 7
+#define CLK_GOUT_DISPAUD_APB_AUD 8
+#define CLK_GOUT_DISPAUD_APB_AUD_AMP 9
+#define CLK_GOUT_DISPAUD_APB_DISP 10
+#define CLK_GOUT_DISPAUD_BUS 11
+#define CLK_GOUT_DISPAUD_BUS_DISP 12
+#define CLK_GOUT_DISPAUD_BUS_PPMU 13
+#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN 14
+#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN 15
+#define CLK_GOUT_DISPAUD_CON_CP2AUD_BCK 16
+#define CLK_GOUT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S 17
+#define CLK_GOUT_DISPAUD_DECON_ECLK 18
+#define CLK_GOUT_DISPAUD_DECON_VCLK 19
+#define CLK_GOUT_DISPAUD_MI2S_AMP_I2SCODCLKI 20
+#define CLK_GOUT_DISPAUD_MI2S_AUD_I2SCODCLKI 21
+#define CLK_GOUT_DISPAUD_MIXER_AUD_SYSCLK 22
+#define CLK_GOUT_DISPAUD_MUX_AUD_PLL 23
+#define CLK_GOUT_DISPAUD_MUX_AUD_PLL_CON 24
+#define CLK_GOUT_DISPAUD_MUX_BUS_USER 25
+#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK 26
+#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK_USER 27
+#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK 28
+#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK_USER 29
+#define CLK_GOUT_DISPAUD_MUX_MI2S 30
+#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER 31
+#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON 32
+#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER 33
+#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON 34
+#define CLK_GOUT_DISPAUD_MUX_PLL 35
+#define CLK_GOUT_DISPAUD_MUX_PLL_CON 36
+#define CLK_MOUT_DISPAUD_BUS_USER 37
+#define CLK_MOUT_DISPAUD_DECON_ECLK 38
+#define CLK_MOUT_DISPAUD_DECON_ECLK_USER 39
+#define CLK_MOUT_DISPAUD_DECON_VCLK 40
+#define CLK_MOUT_DISPAUD_DECON_VCLK_USER 41
+#define CLK_MOUT_DISPAUD_MI2S 42
+#define DISPAUD_NR_CLK 43
+
+/* CMU_FSYS */
+#define CLK_FOUT_FSYS_USB_PLL 1
+#define CLK_GOUT_FSYS_BUSP3_HCLK 2
+#define CLK_GOUT_FSYS_MMC0_ACLK 3
+#define CLK_GOUT_FSYS_MMC1_ACLK 4
+#define CLK_GOUT_FSYS_MMC2_ACLK 5
+#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER 6
+#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON 7
+#define CLK_GOUT_FSYS_MUX_USB_PLL 8
+#define CLK_GOUT_FSYS_MUX_USB_PLL_CON 9
+#define CLK_GOUT_FSYS_PDMA0_ACLK_PDMA0 10
+#define CLK_GOUT_FSYS_PPMU_ACLK 11
+#define CLK_GOUT_FSYS_PPMU_PCLK 12
+#define CLK_GOUT_FSYS_SROMC_HCLK 13
+#define CLK_GOUT_FSYS_UPSIZER_BUS1_ACLK 14
+#define CLK_GOUT_FSYS_USB20DRD_ACLK_HSDRD 15
+#define CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL 16
+#define CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK 17
+#define FSYS_NR_CLK 18
+
+/* CMU_G3D */
+#define CLK_DOUT_G3D_APB 1
+#define CLK_DOUT_G3D_BUS 2
+#define CLK_FOUT_G3D_PLL 3
+#define CLK_GOUT_G3D_ASYNCS_D0_CLK 4
+#define CLK_GOUT_G3D_ASYNC_PCLKM 5
+#define CLK_GOUT_G3D_CLK 6
+#define CLK_GOUT_G3D_MUX 7
+#define CLK_GOUT_G3D_MUX_PLL 8
+#define CLK_GOUT_G3D_MUX_PLL_CON 9
+#define CLK_GOUT_G3D_MUX_SWITCH_USER 10
+#define CLK_GOUT_G3D_PPMU_ACLK 11
+#define CLK_GOUT_G3D_PPMU_PCLK 12
+#define CLK_GOUT_G3D_QE_ACLK 13
+#define CLK_GOUT_G3D_QE_PCLK 14
+#define CLK_GOUT_G3D_SYSREG_PCLK 15
+#define CLK_MOUT_G3D 16
+#define CLK_MOUT_G3D_SWITCH_USER 17
+#define G3D_NR_CLK 18
+
+/* CMU_ISP */
+#define CLK_DOUT_ISP_APB 1
+#define CLK_DOUT_ISP_CAM_HALF 2
+#define CLK_FOUT_ISP_PLL 3
+#define CLK_GOUT_ISP_CAM 4
+#define CLK_GOUT_ISP_CAM_HALF 5
+#define CLK_GOUT_ISP_ISPD 6
+#define CLK_GOUT_ISP_ISPD_PPMU 7
+#define CLK_GOUT_ISP_MUX_CAM 8
+#define CLK_GOUT_ISP_MUX_CAM_USER 9
+#define CLK_GOUT_ISP_MUX_ISP 10
+#define CLK_GOUT_ISP_MUX_ISPD 11
+#define CLK_GOUT_ISP_MUX_PLL 12
+#define CLK_GOUT_ISP_MUX_PLL_CON 13
+#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER 14
+#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON 15
+#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER 16
+#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON 17
+#define CLK_GOUT_ISP_MUX_USER 18
+#define CLK_GOUT_ISP_MUX_VRA 19
+#define CLK_GOUT_ISP_MUX_VRA_USER 20
+#define CLK_GOUT_ISP_VRA 21
+#define CLK_MOUT_ISP_CAM 22
+#define CLK_MOUT_ISP_CAM_USER 23
+#define CLK_MOUT_ISP_ISP 24
+#define CLK_MOUT_ISP_ISPD 25
+#define CLK_MOUT_ISP_USER 26
+#define CLK_MOUT_ISP_VRA 27
+#define CLK_MOUT_ISP_VRA_USER 28
+#define ISP_NR_CLK 29
+
+/* CMU_MFCMSCL */
+#define CLK_DOUT_MFCMSCL_APB 1
+#define CLK_GOUT_MFCMSCL_MFC 2
+#define CLK_GOUT_MFCMSCL_MSCL 3
+#define CLK_GOUT_MFCMSCL_MSCL_BI 4
+#define CLK_GOUT_MFCMSCL_MSCL_D 5
+#define CLK_GOUT_MFCMSCL_MSCL_JPEG 6
+#define CLK_GOUT_MFCMSCL_MSCL_POLY 7
+#define CLK_GOUT_MFCMSCL_MSCL_PPMU 8
+#define CLK_GOUT_MFCMSCL_MUX_MFC_USER 9
+#define CLK_GOUT_MFCMSCL_MUX_MSCL_USER 10
+#define CLK_MOUT_MFCMSCL_MFC_USER 11
+#define CLK_MOUT_MFCMSCL_MSCL_USER 12
+#define MFCMSCL_NR_CLK 13
+
+/* CMU_PERI */
+#define CLK_GOUT_PERI_BUSP1_PERIC0_HCLK 1
+#define CLK_GOUT_PERI_GPIO2_PCLK 2
+#define CLK_GOUT_PERI_GPIO5_PCLK 3
+#define CLK_GOUT_PERI_GPIO6_PCLK 4
+#define CLK_GOUT_PERI_GPIO7_PCLK 5
+#define CLK_GOUT_PERI_HSI2C1_IPCLK 6
+#define CLK_GOUT_PERI_HSI2C2_IPCLK 7
+#define CLK_GOUT_PERI_HSI2C3_IPCLK 8
+#define CLK_GOUT_PERI_HSI2C4_IPCLK 9
+#define CLK_GOUT_PERI_HSI2C5_IPCLK 10
+#define CLK_GOUT_PERI_HSI2C6_IPCLK 11
+#define CLK_GOUT_PERI_I2C0_PCLK 12
+#define CLK_GOUT_PERI_I2C1_PCLK 13
+#define CLK_GOUT_PERI_I2C2_PCLK 14
+#define CLK_GOUT_PERI_I2C3_PCLK 15
+#define CLK_GOUT_PERI_I2C4_PCLK 16
+#define CLK_GOUT_PERI_I2C5_PCLK 17
+#define CLK_GOUT_PERI_I2C6_PCLK 18
+#define CLK_GOUT_PERI_I2C7_PCLK 19
+#define CLK_GOUT_PERI_I2C8_PCLK 20
+#define CLK_GOUT_PERI_MCT_PCLK 21
+#define CLK_GOUT_PERI_PWM_MOTOR_OSCCLK 22
+#define CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0 23
+#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL0_PCLK 24
+#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL1_PCLK 25
+#define CLK_GOUT_PERI_SFRIF_TMU_PCLK 26
+#define CLK_GOUT_PERI_SPI0_PCLK 27
+#define CLK_GOUT_PERI_SPI0_SPI_EXT_CLK 28
+#define CLK_GOUT_PERI_SPI1_PCLK 29
+#define CLK_GOUT_PERI_SPI1_SPI_EXT_CLK 30
+#define CLK_GOUT_PERI_SPI2_PCLK 31
+#define CLK_GOUT_PERI_SPI2_SPI_EXT_CLK 32
+#define CLK_GOUT_PERI_SPI3_PCLK 33
+#define CLK_GOUT_PERI_SPI3_SPI_EXT_CLK 34
+#define CLK_GOUT_PERI_SPI4_PCLK 35
+#define CLK_GOUT_PERI_SPI4_SPI_EXT_CLK 36
+#define CLK_GOUT_PERI_TMU_CLK 37
+#define CLK_GOUT_PERI_TMU_CPUCL0_CLK 38
+#define CLK_GOUT_PERI_TMU_CPUCL1_CLK 39
+#define CLK_GOUT_PERI_UART0_EXT_UCLK 40
+#define CLK_GOUT_PERI_UART0_PCLK 41
+#define CLK_GOUT_PERI_UART1_EXT_UCLK 42
+#define CLK_GOUT_PERI_UART1_PCLK 43
+#define CLK_GOUT_PERI_UART2_EXT_UCLK 44
+#define CLK_GOUT_PERI_UART2_PCLK 45
+#define CLK_GOUT_PERI_WDT_CPUCL0_PCLK 46
+#define CLK_GOUT_PERI_WDT_CPUCL1_PCLK 47
+#define PERI_NR_CLK 48
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS7870_H */
--
2.48.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 02/33] dt-bindings: clock: add clock definitions for exynos7870 CMU
2025-02-02 19:07 ` [PATCH 02/33] " Kaustabh Chakraborty
@ 2025-02-03 7:54 ` Krzysztof Kozlowski
2025-02-03 12:40 ` Kaustabh Chakraborty
0 siblings, 1 reply; 13+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-03 7:54 UTC (permalink / raw)
To: Kaustabh Chakraborty
Cc: Rob Herring, Conor Dooley, Alim Akhtar, Sylwester Nawrocki,
Chanwoo Choi, Michael Turquette, Stephen Boyd, Tomasz Figa,
Linus Walleij, Greg Kroah-Hartman, Jiri Slaby, Lee Jones,
Liam Girdwood, Mark Brown, Vinod Koul, Kishon Vijay Abraham I,
Marek Szyprowski, David Airlie, Simona Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Andi Shyti, Ulf Hansson,
Jaehoon Chung, Vivek Gautam, Thinh Nguyen, Kees Cook, Tony Luck,
Guilherme G . Piccoli, Sergey Lisov, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel, linux-clk, linux-gpio,
linux-serial, linux-phy, linux-usb, dri-devel, linux-i2c,
linux-mmc, linux-hardening
On Mon, Feb 03, 2025 at 12:37:58AM +0530, Kaustabh Chakraborty wrote:
> From: Sergey Lisov <sleirsgoevy@gmail.com>
>
> Add unique identifiers for exynos7870 clocks for every bank. It adds all
> clocks of CMU_MIF, CMU_DISPAUD, CMU_G3D, CMU_ISP, CMU_MFCMSCL, and
> CMU_PERI.
>
> Signed-off-by: Sergey Lisov <sleirsgoevy@gmail.com>
> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
> ---
> include/dt-bindings/clock/exynos7870.h | 324 +++++++++++++++++++++++++
> 1 file changed, 324 insertions(+)
Look at git log - that's never a separate commit.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 02/33] dt-bindings: clock: add clock definitions for exynos7870 CMU
2025-02-03 7:54 ` Krzysztof Kozlowski
@ 2025-02-03 12:40 ` Kaustabh Chakraborty
2025-02-03 14:01 ` Krzysztof Kozlowski
0 siblings, 1 reply; 13+ messages in thread
From: Kaustabh Chakraborty @ 2025-02-03 12:40 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Conor Dooley, Alim Akhtar, Sylwester Nawrocki,
Chanwoo Choi, Michael Turquette, Stephen Boyd, Tomasz Figa,
Linus Walleij, Greg Kroah-Hartman, Jiri Slaby, Lee Jones,
Liam Girdwood, Mark Brown, Vinod Koul, Kishon Vijay Abraham I,
Marek Szyprowski, David Airlie, Simona Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Andi Shyti, Ulf Hansson,
Jaehoon Chung, Vivek Gautam, Thinh Nguyen, Kees Cook, Tony Luck,
Guilherme G . Piccoli, Sergey Lisov, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel, linux-clk, linux-gpio,
linux-serial, linux-phy, linux-usb, dri-devel, linux-i2c,
linux-mmc, linux-hardening, Kaustabh Chakraborty
On 2025-02-03 07:54, Krzysztof Kozlowski wrote:
> On Mon, Feb 03, 2025 at 12:37:58AM +0530, Kaustabh Chakraborty wrote:
>> From: Sergey Lisov <sleirsgoevy@gmail.com>
>>
>> Add unique identifiers for exynos7870 clocks for every bank. It adds all
>> clocks of CMU_MIF, CMU_DISPAUD, CMU_G3D, CMU_ISP, CMU_MFCMSCL, and
>> CMU_PERI.
>>
>> Signed-off-by: Sergey Lisov <sleirsgoevy@gmail.com>
>> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
>> ---
>> include/dt-bindings/clock/exynos7870.h | 324 +++++++++++++++++++++++++
>> 1 file changed, 324 insertions(+)
>
> Look at git log - that's never a separate commit.
Hmm, I see past examples which are mixed.
2ae5c2c3f8d586b709cf67efe94488be397d7544
Exynos850 CMU (c. 2021). CMU definitions are in a separate commit.
591020a516720e9eba1c4b1748cb73b6748e445f
Exynos7885 CMU (c. 2021). CMU definitions are in a separate commit.
while
96bd6224f07b8bf73e0359f15a3d7678118494e6
Exynos5433 CMU (c. 2015). CMU definitions and driver are in a single commit.
Let me know if I should still continue with the approach you mentioned.
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 02/33] dt-bindings: clock: add clock definitions for exynos7870 CMU
2025-02-03 12:40 ` Kaustabh Chakraborty
@ 2025-02-03 14:01 ` Krzysztof Kozlowski
0 siblings, 0 replies; 13+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-03 14:01 UTC (permalink / raw)
To: Kaustabh Chakraborty
Cc: Rob Herring, Conor Dooley, Alim Akhtar, Sylwester Nawrocki,
Chanwoo Choi, Michael Turquette, Stephen Boyd, Tomasz Figa,
Linus Walleij, Greg Kroah-Hartman, Jiri Slaby, Lee Jones,
Liam Girdwood, Mark Brown, Vinod Koul, Kishon Vijay Abraham I,
Marek Szyprowski, David Airlie, Simona Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Andi Shyti, Ulf Hansson,
Jaehoon Chung, Vivek Gautam, Thinh Nguyen, Kees Cook, Tony Luck,
Guilherme G . Piccoli, Sergey Lisov, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel, linux-clk, linux-gpio,
linux-serial, linux-phy, linux-usb, dri-devel, linux-i2c,
linux-mmc, linux-hardening
On 03/02/2025 13:40, Kaustabh Chakraborty wrote:
> On 2025-02-03 07:54, Krzysztof Kozlowski wrote:
>> On Mon, Feb 03, 2025 at 12:37:58AM +0530, Kaustabh Chakraborty wrote:
>>> From: Sergey Lisov <sleirsgoevy@gmail.com>
>>>
>>> Add unique identifiers for exynos7870 clocks for every bank. It adds all
>>> clocks of CMU_MIF, CMU_DISPAUD, CMU_G3D, CMU_ISP, CMU_MFCMSCL, and
>>> CMU_PERI.
>>>
>>> Signed-off-by: Sergey Lisov <sleirsgoevy@gmail.com>
>>> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
>>> ---
>>> include/dt-bindings/clock/exynos7870.h | 324 +++++++++++++++++++++++++
>>> 1 file changed, 324 insertions(+)
>>
>> Look at git log - that's never a separate commit.
>
> Hmm, I see past examples which are mixed.
>
> 2ae5c2c3f8d586b709cf67efe94488be397d7544
> Exynos850 CMU (c. 2021). CMU definitions are in a separate commit.
>
> 591020a516720e9eba1c4b1748cb73b6748e445f
> Exynos7885 CMU (c. 2021). CMU definitions are in a separate commit.
>
Huh, indeed, my mistake.
Let's avoid that pattern, so binding headers are always part of bindings
commit.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 03/33] dt-bindings: clock: document exynos7870 clock driver CMU bindings
2025-02-02 18:36 [PATCH 00/33] Add support for the Exynos7870 SoC, along with three devices Kaustabh Chakraborty
` (3 preceding siblings ...)
2025-02-02 19:07 ` [PATCH 02/33] " Kaustabh Chakraborty
@ 2025-02-02 19:09 ` Kaustabh Chakraborty
2025-02-03 7:57 ` Krzysztof Kozlowski
2025-02-02 19:13 ` [PATCH 00/33] Add support for the Exynos7870 SoC, along with three devices Krzysztof Kozlowski
5 siblings, 1 reply; 13+ messages in thread
From: Kaustabh Chakraborty @ 2025-02-02 19:09 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alim Akhtar,
Sylwester Nawrocki, Chanwoo Choi, Michael Turquette, Stephen Boyd,
Tomasz Figa, Linus Walleij, Greg Kroah-Hartman, Jiri Slaby,
Lee Jones, Liam Girdwood, Mark Brown, Vinod Koul,
Kishon Vijay Abraham I, Marek Szyprowski, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Andi Shyti, Ulf Hansson, Jaehoon Chung,
Vivek Gautam, Thinh Nguyen, Kees Cook, Tony Luck,
Guilherme G . Piccoli
Cc: Sergey Lisov, devicetree, linux-arm-kernel, linux-samsung-soc,
linux-kernel, linux-clk, linux-gpio, linux-serial, linux-phy,
linux-usb, dri-devel, linux-i2c, linux-mmc, linux-hardening,
Kaustabh Chakraborty
Provide dt-schema documentation for Exynos7870 SoC clock controller.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
---
.../clock/samsung,exynos7870-clock.yaml | 246 ++++++++++++++++++
1 file changed, 246 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos7870-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7870-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7870-clock.yaml
new file mode 100644
index 000000000000..697e03ca191d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos7870-clock.yaml
@@ -0,0 +1,246 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos7870-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos7870 SoC clock controller
+
+maintainers:
+ - Chanwoo Choi <cw00.choi@samsung.com>
+ - Krzysztof Kozlowski <krzk@kernel.org>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+ - Tomasz Figa <tomasz.figa@gmail.com>
+
+description: |
+ Exynos7870 clock controller is comprised of several CMU units, generating
+ clocks for different domains. Those CMU units are modeled as separate device
+ tree nodes, and might depend on each other. The root clock in that root tree
+ is an external clock: OSCCLK (26 MHz). This external clock must be defined
+ as a fixed-rate clock in dts.
+
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All clocks available for usage
+ in clock consumer nodes are defined as preprocessor macros in
+ 'dt-bindings/clock/exynos7870.h' header.
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos7870-cmu-mif
+ - samsung,exynos7870-cmu-dispaud
+ - samsung,exynos7870-cmu-fsys
+ - samsung,exynos7870-cmu-g3d
+ - samsung,exynos7870-cmu-isp
+ - samsung,exynos7870-cmu-mfcmscl
+ - samsung,exynos7870-cmu-peri
+
+ clocks:
+ minItems: 1
+ maxItems: 10
+
+ clock-names:
+ minItems: 1
+ maxItems: 10
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7870-cmu-mif
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+
+ clock-names:
+ items:
+ - const: oscclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7870-cmu-dispaud
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_DISPAUD bus clock (from CMU_MIF)
+ - description: DECON external clock (from CMU_MIF)
+ - description: DECON vertical clock (from CMU_MIF)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: gout_mif_cmu_dispaud_bus
+ - const: gout_mif_cmu_dispaud_decon_eclk
+ - const: gout_mif_cmu_dispaud_decon_vclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7870-cmu-fsys
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_FSYS bus clock (from CMU_MIF)
+ - description: USB20DRD clock (from CMU_MIF)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: gout_mif_cmu_fsys_bus
+ - const: gout_mif_cmu_fsys_usb20drd_refclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7870-cmu-g3d
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: G3D switch clock (from CMU_MIF)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: gout_mif_cmu_g3d_switch
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7870-cmu-isp
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: ISP camera clock (from CMU_MIF)
+ - description: ISP clock (from CMU_MIF)
+ - description: ISP VRA clock (from CMU_MIF)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: gout_mif_cmu_isp_cam
+ - const: gout_mif_cmu_isp_isp
+ - const: gout_mif_cmu_isp_vra
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7870-cmu-mfcmscl
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: MSCL clock (from CMU_MIF)
+ - description: MFC clock (from CMU_MIF)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: gout_mif_cmu_mfcmscl_mfc
+ - const: gout_mif_cmu_mfcmscl_mscl
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7870-cmu-peri
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_PERI bus clock (from CMU_MIF)
+ - description: SPI0 clock (from CMU_MIF)
+ - description: SPI1 clock (from CMU_MIF)
+ - description: SPI2 clock (from CMU_MIF)
+ - description: SPI3 clock (from CMU_MIF)
+ - description: SPI4 clock (from CMU_MIF)
+ - description: UART0 clock (from CMU_MIF)
+ - description: UART1 clock (from CMU_MIF)
+ - description: UART2 clock (from CMU_MIF)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: gout_mif_cmu_peri_bus
+ - const: gout_mif_cmu_peri_spi0
+ - const: gout_mif_cmu_peri_spi1
+ - const: gout_mif_cmu_peri_spi2
+ - const: gout_mif_cmu_peri_spi3
+ - const: gout_mif_cmu_peri_spi4
+ - const: gout_mif_cmu_peri_uart0
+ - const: gout_mif_cmu_peri_uart1
+ - const: gout_mif_cmu_peri_uart2
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+ - reg
+
+additionalProperties: false
+
+examples:
+ # Clock controller node for CMU_PERI
+ - |
+ #include <dt-bindings/clock/exynos7870.h>
+
+ cmu_peri: clock-controller@101F0000 {
+ compatible = "samsung,exynos7870-cmu-peri";
+ reg = <0x101f0000 0x1000>;
+ #clock-cells = <1>;
+
+ clock-names = "oscclk",
+ "gout_mif_cmu_peri_bus",
+ "gout_mif_cmu_peri_spi0",
+ "gout_mif_cmu_peri_spi1",
+ "gout_mif_cmu_peri_spi2",
+ "gout_mif_cmu_peri_spi3",
+ "gout_mif_cmu_peri_spi4",
+ "gout_mif_cmu_peri_uart0",
+ "gout_mif_cmu_peri_uart1",
+ "gout_mif_cmu_peri_uart2";
+ clocks = <&oscclk>,
+ <&cmu_mif CLK_GOUT_MIF_CMU_PERI_BUS>,
+ <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI0>,
+ <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI1>,
+ <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI2>,
+ <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI3>,
+ <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI4>,
+ <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART0>,
+ <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART1>,
+ <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART2>;
+ };
+
+...
--
2.48.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 03/33] dt-bindings: clock: document exynos7870 clock driver CMU bindings
2025-02-02 19:09 ` [PATCH 03/33] dt-bindings: clock: document exynos7870 clock driver CMU bindings Kaustabh Chakraborty
@ 2025-02-03 7:57 ` Krzysztof Kozlowski
0 siblings, 0 replies; 13+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-03 7:57 UTC (permalink / raw)
To: Kaustabh Chakraborty
Cc: Rob Herring, Conor Dooley, Alim Akhtar, Sylwester Nawrocki,
Chanwoo Choi, Michael Turquette, Stephen Boyd, Tomasz Figa,
Linus Walleij, Greg Kroah-Hartman, Jiri Slaby, Lee Jones,
Liam Girdwood, Mark Brown, Vinod Koul, Kishon Vijay Abraham I,
Marek Szyprowski, David Airlie, Simona Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Andi Shyti, Ulf Hansson,
Jaehoon Chung, Vivek Gautam, Thinh Nguyen, Kees Cook, Tony Luck,
Guilherme G . Piccoli, Sergey Lisov, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel, linux-clk, linux-gpio,
linux-serial, linux-phy, linux-usb, dri-devel, linux-i2c,
linux-mmc, linux-hardening
On Mon, Feb 03, 2025 at 12:39:24AM +0530, Kaustabh Chakraborty wrote:
Subject - drop driver. Bindings are about hardware. This applies to all
your bindings patches
> + clock-names:
> + items:
> + - const: oscclk
> + - const: gout_mif_cmu_mfcmscl_mfc
> + - const: gout_mif_cmu_mfcmscl_mscl
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynos7870-cmu-peri
> +
Drop blank line
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (26 MHz)
> + - description: CMU_PERI bus clock (from CMU_MIF)
> + - description: SPI0 clock (from CMU_MIF)
> + - description: SPI1 clock (from CMU_MIF)
> + - description: SPI2 clock (from CMU_MIF)
> + - description: SPI3 clock (from CMU_MIF)
> + - description: SPI4 clock (from CMU_MIF)
> + - description: UART0 clock (from CMU_MIF)
> + - description: UART1 clock (from CMU_MIF)
> + - description: UART2 clock (from CMU_MIF)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: gout_mif_cmu_peri_bus
> + - const: gout_mif_cmu_peri_spi0
> + - const: gout_mif_cmu_peri_spi1
> + - const: gout_mif_cmu_peri_spi2
> + - const: gout_mif_cmu_peri_spi3
> + - const: gout_mif_cmu_peri_spi4
> + - const: gout_mif_cmu_peri_uart0
> + - const: gout_mif_cmu_peri_uart1
> + - const: gout_mif_cmu_peri_uart2
> +
> +required:
> + - compatible
> + - "#clock-cells"
> + - clocks
> + - clock-names
> + - reg
required block is just after properties.
> +
> +additionalProperties: false
> +
> +examples:
> + # Clock controller node for CMU_PERI
Drop
> + - |
> + #include <dt-bindings/clock/exynos7870.h>
> +
> + cmu_peri: clock-controller@101F0000 {
Lowercase hex
> + compatible = "samsung,exynos7870-cmu-peri";
> + reg = <0x101f0000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "gout_mif_cmu_peri_bus",
> + "gout_mif_cmu_peri_spi0",
> + "gout_mif_cmu_peri_spi1",
> + "gout_mif_cmu_peri_spi2",
> + "gout_mif_cmu_peri_spi3",
> + "gout_mif_cmu_peri_spi4",
> + "gout_mif_cmu_peri_uart0",
> + "gout_mif_cmu_peri_uart1",
> + "gout_mif_cmu_peri_uart2";
> + clocks = <&oscclk>,
> + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_BUS>,
> + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI0>,
> + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI1>,
> + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI2>,
> + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI3>,
> + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI4>,
> + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART0>,
> + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART1>,
> + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART2>;
> + };
> +
> +...
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 00/33] Add support for the Exynos7870 SoC, along with three devices
2025-02-02 18:36 [PATCH 00/33] Add support for the Exynos7870 SoC, along with three devices Kaustabh Chakraborty
` (4 preceding siblings ...)
2025-02-02 19:09 ` [PATCH 03/33] dt-bindings: clock: document exynos7870 clock driver CMU bindings Kaustabh Chakraborty
@ 2025-02-02 19:13 ` Krzysztof Kozlowski
5 siblings, 0 replies; 13+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-02 19:13 UTC (permalink / raw)
To: Kaustabh Chakraborty, Rob Herring, Conor Dooley, Alim Akhtar,
Sylwester Nawrocki, Chanwoo Choi, Michael Turquette, Stephen Boyd,
Tomasz Figa, Linus Walleij, Greg Kroah-Hartman, Jiri Slaby,
Lee Jones, Liam Girdwood, Mark Brown, Vinod Koul,
Kishon Vijay Abraham I, Marek Szyprowski, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Andi Shyti, Ulf Hansson, Jaehoon Chung,
Vivek Gautam, Thinh Nguyen, Kees Cook, Tony Luck,
Guilherme G. Piccoli
Cc: Sergey Lisov, devicetree, linux-arm-kernel, linux-samsung-soc,
linux-kernel, linux-clk, linux-gpio, linux-serial, linux-phy,
linux-usb, dri-devel, linux-i2c, linux-mmc, linux-hardening
On 02/02/2025 19:36, Kaustabh Chakraborty wrote:
> Samsung Exynos 7870 (codename: Joshua) is an ARM-v8 system-on-chip that was
> announced in 2016. The chipset was found in several popular mid-range to
> low-end Samsung phones, released within 2016 to 2019.
>
> This patch series aims to add support for Exynos 7870, starting with the
> most basic yet essential components such as CPU, GPU, clock controllers,
> PMIC, pin controllers, etc.
>
> Moreover, the series also adds support for three Exynos 7870 devices via
> devicetree. The devices are:
> * Samsung Galaxy J7 Prime - released 2016, codename on7xelte
> * Samsung Galaxy J6 - released 2018, codename j6lte
> * Samsung Galaxy A2 Core - released 2019, codename a2corelte
>
> Additional features implemented in this series include:
> * I2C - touchscreen, IIO sensors, etc.
> * UART - bluetooth and serial debugging
> * MMC - eMMC, Wi-Fi SDIO, SDCard
> * USB - micro-USB 2.0 interface
>
> The series has commits from me and Sergey, who has given me permission
> to upstream their patches with proper attribution.
>
> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
> ---
> Kaustabh Chakraborty (26):
> dt-bindings: hwinfo: samsung,exynos-chipid: add exynos7870-chipid compatible
> dt-bindings: clock: document exynos7870 clock driver CMU bindings
> dt-bindings: soc: samsung: exynos-pmu: add exynos7870-pmu compatible
> dt-bindings: pinctrl: samsung: add exynos7870-pinctrl compatible
> dt-bindings: pinctrl: samsung: add exynos7870-wakeup-eint compatible
> dt-bindings: serial: samsung: add exynos7870-uart compatible
> dt-bindings: mfd: samsung,s2mps11: add compatible for s2mpu05-pmic
This is not related at all to this patchset.
> regulator: dt-bindings: add documentation for s2mpu05-pmic regulators
Neither is this.
> dt-bindings: phy: samsung,usb3-drd-phy: add exynos7870-usbdrd-phy compatible
> dt-bindings: usb: samsung,exynos-dwc3: add exynos7870 support
> dt-bindings: gpu: arm,mali-midgard: add exynos7870 mali compatible
> dt-bindings: i2c: samsung,s3c2410: add exynos7870-i2c compatible
> dt-bindings: i2c: exynos5: add exynos7870-hsi2c compatible
> dt-bindings: mmc: samsung,exynos-dw-mshc: add exynos7870 support
> dt-bindings: soc: samsung,boot-mode: add boot mode definitions for exynos7870
> dt-bindings: arm: samsung: add compatibles for exynos7870 devices
> soc: samsung: exynos-chipid: add support for exynos7870
> clk: samsung: add exynos7870 CLKOUT support
> tty: serial: samsung: add support for exynos7870
This goes to different patchset. Don't mix with SoC changes or pure
bindings. Your CC list is too big.
> phy: exynos5-usbdrd: fix MPLL_MULTIPLIER and SSC_REFCLKSEL masks in refclk
> phy: exynos5-usbdrd: use GENMASK and FIELD_PREP for Exynos5 PHY registers
Different patchset.
> usb: dwc3: exynos: add support for exynos7870
As well, with bindings.
Please organize your patchset according to standard SoC upstream
guidelines - don't mix SoC with non-Soc upstreaming or other subsystems.
While putting entire SoC in one patchset is tempting, you added here
totally unrelated changes like PMIC drivers. Result: 33 patches and huge
cc-list bouncing from mailing lists.
https://lore.kernel.org/linux-samsung-soc/CADrjBPq_0nUYRABKpskRF_dhHu+4K=duPVZX==0pr+cjSL_caQ@mail.gmail.com/T/#m2d9130a1342ab201ab49670fa6c858ee3724c83c
https://lore.kernel.org/all/20231121-topic-sm8650-upstream-dt-v3-0-db9d0507ffd3@linaro.org/
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread