From: Icenowy Zheng <uwu@icenowy.me>
To: Emil Renner Berthing <kernel@esmil.dk>,
Jianlong Huang <jianlong.huang@starfivetech.com>,
Hal Feng <hal.feng@starfivetech.com>,
Linus Walleij <linus.walleij@linaro.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
Icenowy Zheng <uwu@icenowy.me>
Subject: [PATCH v2 2/3] pinctrl: starfive: jh7110: add support for PAD_INTERNAL_* for GPI
Date: Thu, 24 Apr 2025 14:20:16 +0800 [thread overview]
Message-ID: <20250424062017.652969-3-uwu@icenowy.me> (raw)
In-Reply-To: <20250424062017.652969-1-uwu@icenowy.me>
The JH7110 SoC's both pin controller support routing GPI signals to
internal fixed low/high level.
As we allocated two special "pin" numbers for these situations
(PAD_INTERNAL_{LOW,HIGH}), add special handling code for these "pins".
The DOEn/DOUT/FUNCTION fields are ignored and the internal input signal
specified by the DIN field is routed to fixed low/high level.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
.../starfive/pinctrl-starfive-jh7110.c | 41 +++++++++++++++----
1 file changed, 34 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
index 1d0d6c224c104..fb18c7974ec86 100644
--- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
@@ -291,6 +291,24 @@ void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin,
}
EXPORT_SYMBOL_GPL(jh7110_set_gpiomux);
+static void jh7110_set_gpi(struct jh7110_pinctrl *sfp, u32 gpi, u32 val)
+{
+ u32 offset, shift;
+ u32 reg_val;
+ const struct jh7110_pinctrl_soc_info *info = sfp->info;
+
+ offset = 4 * (gpi / 4);
+ shift = 8 * (gpi % 4);
+
+ reg_val = readl_relaxed(sfp->base +
+ info->gpi_reg_base + offset);
+ reg_val &= info->gpi_mask << shift;
+ reg_val |= (val & info->gpi_mask) << shift;
+
+ writel_relaxed(reg_val, sfp->base +
+ info->gpi_reg_base + offset);
+}
+
static int jh7110_set_mux(struct pinctrl_dev *pctldev,
unsigned int fsel, unsigned int gsel)
{
@@ -307,14 +325,23 @@ static int jh7110_set_mux(struct pinctrl_dev *pctldev,
pinmux = group->data;
for (i = 0; i < group->grp.npins; i++) {
u32 v = pinmux[i];
+ u32 pin = jh7110_pinmux_pin(v);
- if (info->jh7110_set_one_pin_mux)
- info->jh7110_set_one_pin_mux(sfp,
- jh7110_pinmux_pin(v),
- jh7110_pinmux_din(v),
- jh7110_pinmux_dout(v),
- jh7110_pinmux_doen(v),
- jh7110_pinmux_function(v));
+ switch (pin) {
+ case PAD_INTERNAL_LOW:
+ case PAD_INTERNAL_HIGH:
+ jh7110_set_gpi(sfp, jh7110_pinmux_din(v),
+ pin == PAD_INTERNAL_HIGH);
+ break;
+ default:
+ if (info->jh7110_set_one_pin_mux)
+ info->jh7110_set_one_pin_mux(sfp,
+ jh7110_pinmux_pin(v),
+ jh7110_pinmux_din(v),
+ jh7110_pinmux_dout(v),
+ jh7110_pinmux_doen(v),
+ jh7110_pinmux_function(v));
+ }
}
return 0;
--
2.49.0
next prev parent reply other threads:[~2025-04-24 6:20 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-24 6:20 [PATCH v2 0/3] pinctrl: starfive: jh7110: support force inputs Icenowy Zheng
2025-04-24 6:20 ` [PATCH v2 1/3] dt-bindings: pinctrl: starfive,jh7110: add PAD_INTERNAL_* virtual pins Icenowy Zheng
2025-04-24 8:15 ` E Shattow
2025-04-25 8:43 ` Icenowy Zheng
2025-04-24 8:51 ` Linus Walleij
2025-04-24 9:38 ` Icenowy Zheng
2025-04-24 10:30 ` Linus Walleij
2025-04-24 12:25 ` Icenowy Zheng
2025-04-28 14:18 ` Linus Walleij
2025-04-28 7:20 ` Krzysztof Kozlowski
2025-04-28 8:40 ` Icenowy Zheng
2025-04-29 7:31 ` Krzysztof Kozlowski
2025-04-29 9:00 ` Icenowy Zheng
2025-04-30 7:21 ` Krzysztof Kozlowski
2025-04-24 6:20 ` Icenowy Zheng [this message]
2025-04-24 7:57 ` [PATCH v2 2/3] pinctrl: starfive: jh7110: add support for PAD_INTERNAL_* for GPI E Shattow
2025-05-06 8:10 ` Icenowy Zheng
2025-04-24 6:21 ` [PATCH v2 3/3] riscv: dts: starfive: jh7110-pine64-star64: force no USB overcurrent Icenowy Zheng
2025-04-25 9:22 ` kernel test robot
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