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Tue, 20 May 2025 17:04:05 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 5134540068; Tue, 20 May 2025 17:02:59 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 5A151B20AF1; Tue, 20 May 2025 17:02:36 +0200 (CEST) Received: from localhost (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 20 May 2025 17:02:36 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Tue, 20 May 2025 17:02:33 +0200 Subject: [PATCH v2 6/8] ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp25 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-ID: <20250520-hdp-upstream-v2-6-53f6b8b5ffc8@foss.st.com> References: <20250520-hdp-upstream-v2-0-53f6b8b5ffc8@foss.st.com> In-Reply-To: <20250520-hdp-upstream-v2-0-53f6b8b5ffc8@foss.st.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski CC: , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-6f78e X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-20_06,2025-05-20_01,2025-03-28_01 Add the hdp devicetree node for stm32mp25 SoC family Signed-off-by: Clément Le Goffic --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 87110f91e489..0fd79acd458f 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -917,6 +917,13 @@ package_otp@1e8 { }; }; + hdp: pinctrl@44090000 { + compatible = "st,stm32mp251-hdp"; + reg = <0x44090000 0x400>; + clocks = <&rcc CK_BUS_HDP>; + status = "disabled"; + }; + rcc: clock-controller@44200000 { compatible = "st,stm32mp25-rcc"; reg = <0x44200000 0x10000>; -- 2.43.0