From: Christian Bruel <christian.bruel@foss.st.com>
To: <christian.bruel@foss.st.com>, <lpieralisi@kernel.org>,
<kwilczynski@kernel.org>, <mani@kernel.org>, <robh@kernel.org>,
<bhelgaas@google.com>, <krzk+dt@kernel.org>,
<conor+dt@kernel.org>, <mcoquelin.stm32@gmail.com>,
<alexandre.torgue@foss.st.com>, <linus.walleij@linaro.org>,
<corbet@lwn.net>, <p.zabel@pengutronix.de>,
<shradha.t@samsung.com>, <mayank.rana@oss.qualcomm.com>,
<namcao@linutronix.de>, <qiang.yu@oss.qualcomm.com>,
<thippeswamy.havalige@amd.com>, <inochiama@gmail.com>,
<quic_schintav@quicinc.com>
Cc: <johan+linaro@kernel.org>, <linux-pci@vger.kernel.org>,
<devicetree@vger.kernel.org>,
<linux-stm32@st-md-mailman.stormreply.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-gpio@vger.kernel.org>,
<linux-doc@vger.kernel.org>
Subject: [PATCH v13 00/11] Add STM32MP25 PCIe drivers
Date: Wed, 20 Aug 2025 09:54:00 +0200 [thread overview]
Message-ID: <20250820075411.1178729-1-christian.bruel@foss.st.com> (raw)
Changes in v13:
- Rebase on pci/next
- Replace access to dev->pins->init_state by new
pinctrl_pm_select_init_state().
- Document pinctrl PM state API.
- Group GPIO PERST# de-assertion with PVPERL delay. (Bjorn)
Changes in v12:
Fix warning reported by kernel test robot <lkp@intel.com>
Changes in v11:
Address comments from Manivanna:
- RC driver: Do not call pm_runtime_get_noresume in probe
More uses of dev_err_probe
- EP driver: Use level triggered PERST# irq
Changes in v10:
- Update pcie_ep bindings with dbi2 and atu regs,
thus remove Reviewed-by and Acked-by.
Changes in v9:
- Describe atu and dbi2 shadowed registers in pcie_ep node
Address RC and EP drivers comments from Manivanna:
- Use dev_error_probe() for pm_runtime_enable() calls
- Reword Kconfig help message
- Move pm_runtime_get_noresume() before devm_pm_runtime_enable()
Changes in v8:
- Whitespace in comment
Changes in v7:
- Use device_init_wakeup to enable wakeup
- Fix comments (Bjorn)
Changes in v6:
- Call device_wakeup_enable() to fix WAKE# wakeup.
Address comments from Manivanna:
- Fix/Add Comments
- Fix DT indents
- Remove dw_pcie_ep_linkup() in EP start link
- Add PCIE_T_PVPERL_MS delay in RC PERST# deassert
Changes in v5:
Address driver comments from Manivanna:
- Use dw_pcie_{suspend/resume}_noirq instead of private ones.
- Move dw_pcie_host_init() to probe
- Add stm32_remove_pcie_port cleanup function
- Use of_node_put in stm32_pcie_parse_port
- Remove wakeup-source property
- Use generic dev_pm_set_dedicated_wake_irq to support wake# irq
Changes in v4:
Address bindings comments Rob Herring
- Remove phy property form common yaml
- Remove phy-name property
- Move wake_gpio and reset_gpio to the host root port
Changes in v3:
Address comments from Manivanna, Rob and Bjorn:
- Move host wakeup helper to dwc core (Mani)
- Drop num-lanes=<1> from bindings (Rob)
- Fix PCI address of I/O region (Mani)
- Moved PHY to a RC rootport subsection (Bjorn, Mani)
- Replaced dma-limit quirk by dma-ranges property (Bjorn)
- Moved out perst assert/deassert from start/stop link (Mani)
- Drop link_up test optim (Mani)
- DT and comments rephrasing (Bjorn)
- Add dts entries now that the combophy entries has landed
- Drop delaying Configuration Requests
Changes in v2:
- Fix st,stm32-pcie-common.yaml dt_binding_check
Changes in v1:
Address comments from Rob Herring and Bjorn Helgaas:
- Drop st,limit-mrrs and st,max-payload-size from this patchset
- Remove single reset and clocks binding names and misc yaml cleanups
- Split RC/EP common bindings to a separate schema file
- Use correct PCIE_T_PERST_CLK_US and PCIE_T_RRS_READY_MS defines
- Use .remove instead of .remove_new
- Fix bar reset sequence in EP driver
- Use cleanup blocks for error handling
- Cosmetic fixes
Christian Bruel (11):
Documentation: pinctrl: Describe PM helper functions for standard
states.
pinctrl: Add pinctrl_pm_select_init_state helper function
dt-bindings: PCI: Add STM32MP25 PCIe Root Complex bindings
PCI: stm32: Add PCIe host support for STM32MP25
dt-bindings: PCI: Add STM32MP25 PCIe Endpoint bindings
PCI: stm32: Add PCIe Endpoint support for STM32MP25
MAINTAINERS: add entry for ST STM32MP25 PCIe drivers
arm64: dts: st: add PCIe pinctrl entries in stm32mp25-pinctrl.dtsi
arm64: dts: st: Add PCIe Root Complex mode on stm32mp251
arm64: dts: st: Add PCIe Endpoint mode on stm32mp251
arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 board
.../bindings/pci/st,stm32-pcie-common.yaml | 33 ++
.../bindings/pci/st,stm32-pcie-ep.yaml | 73 ++++
.../bindings/pci/st,stm32-pcie-host.yaml | 112 +++++
Documentation/driver-api/pin-control.rst | 57 ++-
MAINTAINERS | 7 +
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 20 +
arch/arm64/boot/dts/st/stm32mp251.dtsi | 59 +++
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 21 +
drivers/pci/controller/dwc/Kconfig | 24 ++
drivers/pci/controller/dwc/Makefile | 2 +
drivers/pci/controller/dwc/pcie-stm32-ep.c | 384 ++++++++++++++++++
drivers/pci/controller/dwc/pcie-stm32.c | 360 ++++++++++++++++
drivers/pci/controller/dwc/pcie-stm32.h | 16 +
drivers/pinctrl/core.c | 13 +
include/linux/pinctrl/consumer.h | 10 +
15 files changed, 1189 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml
create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml
create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml
create mode 100644 drivers/pci/controller/dwc/pcie-stm32-ep.c
create mode 100644 drivers/pci/controller/dwc/pcie-stm32.c
create mode 100644 drivers/pci/controller/dwc/pcie-stm32.h
--
2.34.1
next reply other threads:[~2025-08-20 7:58 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-20 7:54 Christian Bruel [this message]
2025-08-20 7:54 ` [PATCH v13 01/11] Documentation: pinctrl: Describe PM helper functions for standard states Christian Bruel
2025-08-20 7:54 ` [PATCH v13 02/11] pinctrl: Add pinctrl_pm_select_init_state helper function Christian Bruel
2025-08-20 7:54 ` [PATCH v13 03/11] dt-bindings: PCI: Add STM32MP25 PCIe Root Complex bindings Christian Bruel
2025-08-20 7:54 ` [PATCH v13 04/11] PCI: stm32: Add PCIe host support for STM32MP25 Christian Bruel
2025-08-25 9:15 ` Philipp Zabel
2025-08-25 14:47 ` Christian Bruel
2025-08-25 15:56 ` Philipp Zabel
2025-08-20 7:54 ` [PATCH v13 05/11] dt-bindings: PCI: Add STM32MP25 PCIe Endpoint bindings Christian Bruel
2025-08-20 7:54 ` [PATCH v13 06/11] PCI: stm32: Add PCIe Endpoint support for STM32MP25 Christian Bruel
2025-08-27 18:58 ` Bjorn Helgaas
2025-08-28 12:12 ` Christian Bruel
2025-08-28 17:16 ` Bjorn Helgaas
2025-08-28 18:46 ` Christian Bruel
2025-08-28 17:22 ` Bjorn Helgaas
2025-08-28 19:06 ` Christian Bruel
2025-08-28 19:20 ` Bjorn Helgaas
2025-08-20 7:54 ` [PATCH v13 07/11] MAINTAINERS: add entry for ST STM32MP25 PCIe drivers Christian Bruel
2025-08-20 7:54 ` [PATCH v13 08/11] arm64: dts: st: add PCIe pinctrl entries in stm32mp25-pinctrl.dtsi Christian Bruel
2025-08-20 7:54 ` [PATCH v13 09/11] arm64: dts: st: Add PCIe Root Complex mode on stm32mp251 Christian Bruel
2025-08-20 7:54 ` [PATCH v13 10/11] arm64: dts: st: Add PCIe Endpoint " Christian Bruel
2025-08-20 7:54 ` [PATCH v13 11/11] arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 board Christian Bruel
2025-08-27 13:30 ` (subset) [PATCH v13 00/11] Add STM32MP25 PCIe drivers Manivannan Sadhasivam
2025-09-04 8:27 ` Alexandre TORGUE
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250820075411.1178729-1-christian.bruel@foss.st.com \
--to=christian.bruel@foss.st.com \
--cc=alexandre.torgue@foss.st.com \
--cc=bhelgaas@google.com \
--cc=conor+dt@kernel.org \
--cc=corbet@lwn.net \
--cc=devicetree@vger.kernel.org \
--cc=inochiama@gmail.com \
--cc=johan+linaro@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=kwilczynski@kernel.org \
--cc=linus.walleij@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-stm32@st-md-mailman.stormreply.com \
--cc=lpieralisi@kernel.org \
--cc=mani@kernel.org \
--cc=mayank.rana@oss.qualcomm.com \
--cc=mcoquelin.stm32@gmail.com \
--cc=namcao@linutronix.de \
--cc=p.zabel@pengutronix.de \
--cc=qiang.yu@oss.qualcomm.com \
--cc=quic_schintav@quicinc.com \
--cc=robh@kernel.org \
--cc=shradha.t@samsung.com \
--cc=thippeswamy.havalige@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).