From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24C802D8791; Wed, 20 Aug 2025 07:59:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755676790; cv=none; b=NOGgTZdBuOsLmBTizroZGnsCn6Jc78nfrBv88kCTNmjo87K1VQku6Qcm6q6QCP1IS2m4Cb3kqfk8v2if3/UBRq7VDi+QMskjhJ0g/2iXvZNTg035iCX8zyjUP9+yJ8Jn8Q3tVz8s92FjWqsh8GWeJEnY3ExcJrHtLVw7ddDatU0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755676790; c=relaxed/simple; bh=aDfuuMiWkf0lkqLLHUt1wwJ5Qz9LTVGJXcN1g2ZjIZ8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=j6fGeeAm3yRbpAOYfYfa13qLPWKaH/8sKq7NTJZgEH3hxAOPHzLcqRbAPce1hYJZpcElmSm/ePVJJmusaMDPFpYu8tzE9/CgcbcvGEf/1GF18R7opo51j5ODcF4TOuCDAUHcn9ablmRfD0tcBapWob3+14Vzd/UPl2C9QJ4i62E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=ObPLhKWi; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="ObPLhKWi" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57K6QoSO010506; Wed, 20 Aug 2025 09:59:24 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= H6eETUqWv3VVFbBigRhvmAs5gJe0ByLoViR9hRNwVhM=; b=ObPLhKWiDYDeiPUY cV1JAaqWYgGxBNHvDo1u183YI0/LBPSRbhCCupt69hMnDyyQ/4P5XOjbOflgvC3z MRjcUbJXKPVuPH7VA/3XS+AbdIV3K60B0VDemN+6+lBIxHFNUtTRrqFA1kNxRVvh rPxnkfGYlUfHAxCWKaezt8NgpwbAzDkP08M5S1kNOqn3xmcSNF1x+YN7uegNEE7G /qxr5KG2Bu1f6B75Py1Y8sVANYp03up5tx1uYBt0pXLn0WUeJcuZT+0ZZ3F5Unn4 j5jW5Y6HH6uO4D3AdgzkdtcKxeQw3z+WW2morrju0X/bSn787kBp2GxZogdEpD+9 M9kmmQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 48n7548x8k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Aug 2025 09:59:23 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 9609F40045; Wed, 20 Aug 2025 09:57:24 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 266335E811A; Wed, 20 Aug 2025 09:56:02 +0200 (CEST) Received: from localhost (10.130.77.120) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 20 Aug 2025 09:56:01 +0200 From: Christian Bruel To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v13 05/11] dt-bindings: PCI: Add STM32MP25 PCIe Endpoint bindings Date: Wed, 20 Aug 2025 09:54:05 +0200 Message-ID: <20250820075411.1178729-6-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250820075411.1178729-1-christian.bruel@foss.st.com> References: <20250820075411.1178729-1-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-20_03,2025-08-20_01,2025-03-28_01 STM32MP25 PCIe Controller is based on the DesignWare core configured as end point mode from the SYSCFG register. Signed-off-by: Christian Bruel Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/st,stm32-pcie-ep.yaml | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml new file mode 100644 index 000000000000..b076ada4f332 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32MP25 PCIe Endpoint + +maintainers: + - Christian Bruel + +description: + PCIe endpoint controller based on the Synopsys DesignWare PCIe core. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + - $ref: /schemas/pci/st,stm32-pcie-common.yaml# + +properties: + compatible: + const: st,stm32mp25-pcie-ep + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: Data Bus Interface (DBI) shadow registers. + - description: Internal Address Translation Unit (iATU) registers. + - description: PCIe configuration registers. + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: atu + - const: addr_space + + reset-gpios: + description: GPIO controlled connection to PERST# signal + maxItems: 1 + + phys: + maxItems: 1 + +required: + - phys + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + pcie-ep@48400000 { + compatible = "st,stm32mp25-pcie-ep"; + reg = <0x48400000 0x400000>, + <0x48500000 0x100000>, + <0x48700000 0x80000>, + <0x10000000 0x10000000>; + reg-names = "dbi", "dbi2", "atu", "addr_space"; + clocks = <&rcc CK_BUS_PCIE>; + phys = <&combophy PHY_TYPE_PCIE>; + resets = <&rcc PCIE_R>; + pinctrl-names = "default", "init"; + pinctrl-0 = <&pcie_pins_a>; + pinctrl-1 = <&pcie_init_pins_a>; + reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>; + access-controllers = <&rifsc 68>; + power-domains = <&CLUSTER_PD>; + }; -- 2.34.1