[PATCH] pinctrl: amd: Don't access irq_data's hwirq member directly

[PATCH] pinctrl: amd: Don't access irq_data's hwirq member directly

[Mario Limonciello (AMD)]

There is an irqd_to_hwirq() intended to get the hwirq number. Switch
all use to it.

Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>
---
 drivers/pinctrl/pinctrl-amd.c | 34 +++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 127eeb0104d85..f9b7ee607c02d 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -384,13 +384,13 @@ static void amd_gpio_irq_enable(struct irq_data *d)
 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
 
-	gpiochip_enable_irq(gc, d->hwirq);
+	gpiochip_enable_irq(gc, irqd_to_hwirq(d));
 
 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
-	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+	pin_reg = readl(gpio_dev->base + irqd_to_hwirq(d)*4);
 	pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
 	pin_reg |= BIT(INTERRUPT_MASK_OFF);
-	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+	writel(pin_reg, gpio_dev->base + irqd_to_hwirq(d)*4);
 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
 }
 
@@ -402,13 +402,13 @@ static void amd_gpio_irq_disable(struct irq_data *d)
 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
 
 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
-	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+	pin_reg = readl(gpio_dev->base + irqd_to_hwirq(d)*4);
 	pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
 	pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
-	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+	writel(pin_reg, gpio_dev->base + irqd_to_hwirq(d)*4);
 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
 
-	gpiochip_disable_irq(gc, d->hwirq);
+	gpiochip_disable_irq(gc, irqd_to_hwirq(d));
 }
 
 static void amd_gpio_irq_mask(struct irq_data *d)
@@ -419,9 +419,9 @@ static void amd_gpio_irq_mask(struct irq_data *d)
 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
 
 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
-	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+	pin_reg = readl(gpio_dev->base + irqd_to_hwirq(d)*4);
 	pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
-	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+	writel(pin_reg, gpio_dev->base + irqd_to_hwirq(d)*4);
 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
 }
 
@@ -433,9 +433,9 @@ static void amd_gpio_irq_unmask(struct irq_data *d)
 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
 
 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
-	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+	pin_reg = readl(gpio_dev->base + irqd_to_hwirq(d)*4);
 	pin_reg |= BIT(INTERRUPT_MASK_OFF);
-	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+	writel(pin_reg, gpio_dev->base + irqd_to_hwirq(d)*4);
 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
 }
 
@@ -449,17 +449,17 @@ static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 	int err;
 
 	pm_pr_dbg("Setting wake for GPIO %lu to %s\n",
-		   d->hwirq, str_enable_disable(on));
+		   irqd_to_hwirq(d), str_enable_disable(on));
 
 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
-	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+	pin_reg = readl(gpio_dev->base + irqd_to_hwirq(d)*4);
 
 	if (on)
 		pin_reg |= wake_mask;
 	else
 		pin_reg &= ~wake_mask;
 
-	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+	writel(pin_reg, gpio_dev->base + irqd_to_hwirq(d)*4);
 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
 
 	if (on)
@@ -497,7 +497,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
 
 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
-	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+	pin_reg = readl(gpio_dev->base + irqd_to_hwirq(d)*4);
 
 	switch (type & IRQ_TYPE_SENSE_MASK) {
 	case IRQ_TYPE_EDGE_RISING:
@@ -563,10 +563,10 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 	pin_reg_irq_en = pin_reg;
 	pin_reg_irq_en |= mask;
 	pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
-	writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
-	while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
+	writel(pin_reg_irq_en, gpio_dev->base + irqd_to_hwirq(d)*4);
+	while ((readl(gpio_dev->base + irqd_to_hwirq(d)*4) & mask) != mask)
 		continue;
-	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+	writel(pin_reg, gpio_dev->base + irqd_to_hwirq(d)*4);
 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
 
 	return ret;
-- 
2.43.0

Re: [PATCH] pinctrl: amd: Don't access irq_data's hwirq member directly

[Andy Shevchenko]

On Wed, Aug 20, 2025 at 06:31:52PM -0500, Mario Limonciello (AMD) wrote:
> There is an irqd_to_hwirq() intended to get the hwirq number. Switch
> all use to it.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
One nit-pick below, though.

Thanks, Mario, for a prompt act!

...

>  	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
>  	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);

Perhaps better

	irq_hw_number_t hwirq = ...;

?

> -	gpiochip_enable_irq(gc, d->hwirq);
> +	gpiochip_enable_irq(gc, irqd_to_hwirq(d));
>  
>  	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
> -	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
> +	pin_reg = readl(gpio_dev->base + irqd_to_hwirq(d)*4);
>  	pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
>  	pin_reg |= BIT(INTERRUPT_MASK_OFF);
> -	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
> +	writel(pin_reg, gpio_dev->base + irqd_to_hwirq(d)*4);
>  	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);

Ditto for the rest.

-- 
With Best Regards,
Andy Shevchenko