From: "Herve Codina (Schneider Electric)" <herve.codina@bootlin.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Wolfram Sang <wsa+renesas@sang-engineering.com>,
Hoan Tran <hoan@os.amperecomputing.com>,
Linus Walleij <linus.walleij@linaro.org>,
Bartosz Golaszewski <brgl@bgdev.pl>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Saravana Kannan <saravanak@google.com>,
Serge Semin <fancer.lancer@gmail.com>,
Herve Codina <herve.codina@bootlin.com>
Cc: Phil Edworthy <phil.edworthy@renesas.com>,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Pascal Eberhard <pascal.eberhard@se.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Subject: [PATCH v3 7/8] soc: renesas: Add support for Renesas RZ/N1 GPIO Interrupt Multiplexer
Date: Thu, 18 Sep 2025 12:40:05 +0200 [thread overview]
Message-ID: <20250918104009.94754-8-herve.codina@bootlin.com> (raw)
In-Reply-To: <20250918104009.94754-1-herve.codina@bootlin.com>
On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those
interruption lines are multiplexed by the GPIO Interrupt Multiplexer in
order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.
The GPIO interrupt multiplexer IP does nothing but select 8 GPIO
IRQ lines out of the 96 available to wire them to the GIC input lines.
Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
---
drivers/soc/renesas/Kconfig | 4 ++
drivers/soc/renesas/Makefile | 1 +
drivers/soc/renesas/rzn1_irqmux.c | 110 ++++++++++++++++++++++++++++++
3 files changed, 115 insertions(+)
create mode 100644 drivers/soc/renesas/rzn1_irqmux.c
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 719b7f4f376f..0878b6884515 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -58,6 +58,7 @@ config ARCH_RZN1
select PM
select PM_GENERIC_DOMAINS
select ARM_AMBA
+ select RZN1_IRQMUX
if ARM && ARCH_RENESAS
@@ -447,6 +448,9 @@ config PWC_RZV2M
config RST_RCAR
bool "Reset Controller support for R-Car" if COMPILE_TEST
+config RZN1_IRQMUX
+ bool "Renesas RZ/N1 GPIO IRQ multiplexer support" if COMPILE_TEST
+
config SYSC_RZ
bool "System controller for RZ SoCs" if COMPILE_TEST
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index 3bdcc6a395d5..daa932c7698d 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -14,4 +14,5 @@ obj-$(CONFIG_SYS_R9A09G057) += r9a09g057-sys.o
# Family
obj-$(CONFIG_PWC_RZV2M) += pwc-rzv2m.o
obj-$(CONFIG_RST_RCAR) += rcar-rst.o
+obj-$(CONFIG_RZN1_IRQMUX) += rzn1_irqmux.o
obj-$(CONFIG_SYSC_RZ) += rz-sysc.o
diff --git a/drivers/soc/renesas/rzn1_irqmux.c b/drivers/soc/renesas/rzn1_irqmux.c
new file mode 100644
index 000000000000..3855e132c15f
--- /dev/null
+++ b/drivers/soc/renesas/rzn1_irqmux.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * RZ/N1 GPIO Interrupt Multiplexer
+ *
+ * Copyright 2025 Schneider Electric
+ * Author: Herve Codina <herve.codina@bootlin.com>
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+
+#define IRQMUX_MAX_IRQS 8
+
+static int irqmux_setup(struct device *dev, struct device_node *np, u32 __iomem *regs)
+{
+ struct of_imap_parser imap_parser;
+ struct of_imap_item imap_item;
+ unsigned int index = 0;
+ u32 tmp;
+ int ret;
+
+ /* We support only #interrupt-cells = <1> and #address-cells = <0> */
+ ret = of_property_read_u32(np, "#interrupt-cells", &tmp);
+ if (ret)
+ return ret;
+ if (tmp != 1)
+ return -EINVAL;
+
+ ret = of_property_read_u32(np, "#address-cells", &tmp);
+ if (ret)
+ return ret;
+ if (tmp != 0)
+ return -EINVAL;
+
+ ret = of_imap_parser_init(&imap_parser, np, &imap_item);
+ if (ret)
+ return ret;
+
+ for_each_of_imap_item(&imap_parser, &imap_item) {
+ /*
+ * The child #address-cells is 0 (already checked). The first
+ * value in imap item is the src hwirq.
+ *
+ * imap items matches 1:1 the interrupt lines that could
+ * be configured by registers (same order, same number).
+ * Configure the related register with the src hwirq retrieved
+ * from the interrupt-map.
+ */
+ if (index > IRQMUX_MAX_IRQS) {
+ of_node_put(imap_item.parent_args.np);
+ dev_err(dev, "too much items in interrupt-map\n");
+ return -EINVAL;
+ }
+
+ writel(imap_item.child_imap[0], regs + index);
+ index++;
+ }
+
+ return 0;
+}
+
+static int irqmux_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ u32 __iomem *regs;
+ int nr_irqs;
+ int ret;
+
+ regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
+
+ nr_irqs = of_irq_count(np);
+ if (nr_irqs < 0)
+ return nr_irqs;
+
+ if (nr_irqs > IRQMUX_MAX_IRQS) {
+ dev_err(dev, "too many output interrupts\n");
+ return -ENOENT;
+ }
+
+ ret = irqmux_setup(dev, np, regs);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to setup mux\n");
+
+ return 0;
+}
+
+static const struct of_device_id irqmux_of_match[] = {
+ { .compatible = "renesas,rzn1-gpioirqmux", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, irq_mux_of_match);
+
+static struct platform_driver irqmux_driver = {
+ .probe = irqmux_probe,
+ .driver = {
+ .name = "rzn1_irqmux",
+ .of_match_table = irqmux_of_match,
+ },
+};
+module_platform_driver(irqmux_driver);
+
+MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>");
+MODULE_DESCRIPTION("Renesas RZ/N1 GPIO IRQ Multiplexer Driver");
+MODULE_LICENSE("GPL");
--
2.51.0
next prev parent reply other threads:[~2025-09-18 10:40 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-18 10:39 [PATCH v3 0/8] gpio: renesas: Add support for GPIO and related interrupts in RZ/N1 SoC Herve Codina (Schneider Electric)
2025-09-18 10:39 ` [PATCH v3 1/8] of/irq: Introduce for_each_of_imap_item Herve Codina (Schneider Electric)
2025-09-18 10:40 ` [PATCH v3 2/8] of: unittest: Add a test case for for_each_of_imap_item iterator Herve Codina (Schneider Electric)
2025-09-18 10:40 ` [PATCH v3 3/8] irqchip/ls-extirq: Use " Herve Codina (Schneider Electric)
2025-09-18 10:40 ` [PATCH v3 4/8] irqchip/renesas-rza1: " Herve Codina (Schneider Electric)
2025-09-18 10:40 ` [PATCH v3 5/8] ARM: dts: r9a06g032: Add GPIO controllers Herve Codina (Schneider Electric)
2025-09-19 10:03 ` Wolfram Sang
2025-09-22 14:22 ` Bartosz Golaszewski
2025-09-22 15:31 ` Herve Codina
2025-09-22 15:33 ` Bartosz Golaszewski
2025-09-22 16:08 ` Herve Codina
2025-09-18 10:40 ` [PATCH v3 6/8] dt-bindings: soc: renesas: Add the Renesas RZ/N1 GPIO Interrupt Multiplexer Herve Codina (Schneider Electric)
2025-09-18 15:06 ` Conor Dooley
2025-09-18 15:15 ` Herve Codina
2025-09-18 15:26 ` Conor Dooley
2025-09-18 15:39 ` Herve Codina
2025-09-18 15:44 ` Conor Dooley
2025-09-19 17:33 ` Rob Herring
2025-09-19 9:34 ` Wolfram Sang
2025-09-19 12:39 ` Herve Codina
2025-09-18 10:40 ` Herve Codina (Schneider Electric) [this message]
2025-09-19 9:41 ` [PATCH v3 7/8] soc: renesas: Add support for " Wolfram Sang
2025-09-19 13:14 ` Herve Codina
2025-09-19 14:40 ` Wolfram Sang
2025-09-19 15:30 ` Herve Codina
2025-09-19 15:47 ` Wolfram Sang
2025-10-14 13:19 ` Geert Uytterhoeven
2025-10-14 14:11 ` Wolfram Sang
2025-10-14 14:58 ` Geert Uytterhoeven
2025-09-18 10:40 ` [PATCH v3 8/8] ARM: dts: r9a06g032: Add support for GPIO interrupts Herve Codina (Schneider Electric)
2025-09-19 9:42 ` Wolfram Sang
2025-09-19 13:59 ` Herve Codina
2025-09-19 14:41 ` Wolfram Sang
2025-09-19 17:12 ` Herve Codina
2025-09-22 14:16 ` Herve Codina
2025-09-22 14:29 ` Wolfram Sang
2025-09-18 15:37 ` [PATCH v3 0/8] gpio: renesas: Add support for GPIO and related interrupts in RZ/N1 SoC Conor Dooley
2025-09-18 15:57 ` Herve Codina
2025-09-19 5:41 ` Wolfram Sang
2025-09-19 9:43 ` Wolfram Sang
2025-09-19 9:54 ` Wolfram Sang
2025-09-19 15:48 ` Wolfram Sang
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