From: Rob Herring <robh@kernel.org>
To: Svyatoslav Ryhel <clamor95@gmail.com>
Cc: "David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Thierry Reding" <thierry.reding@gmail.com>,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Sowjanya Komatineni" <skomatineni@nvidia.com>,
"Luca Ceresoli" <luca.ceresoli@bootlin.com>,
"Prashant Gaikwad" <pgaikwad@nvidia.com>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Mikko Perttunen" <mperttunen@nvidia.com>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Mauro Carvalho Chehab" <mchehab@kernel.org>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Jonas Schwöbel" <jonasschwoebel@yahoo.de>,
"Dmitry Osipenko" <digetx@gmail.com>,
"Charan Pedumuru" <charan.pedumuru@gmail.com>,
"Diogo Ivo" <diogo.ivo@tecnico.ulisboa.pt>,
"Aaron Kling" <webgeek1234@gmail.com>,
"Arnd Bergmann" <arnd@arndb.de>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-media@vger.kernel.org, linux-clk@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-staging@lists.linux.dev
Subject: Re: [PATCH v3 20/22] dt-bindings: display: tegra: document Tegra20 and Tegra30 CSI
Date: Wed, 1 Oct 2025 20:52:44 -0500 [thread overview]
Message-ID: <20251002015244.GA2836647-robh@kernel.org> (raw)
In-Reply-To: <20250925151648.79510-21-clamor95@gmail.com>
On Thu, Sep 25, 2025 at 06:16:46PM +0300, Svyatoslav Ryhel wrote:
> Document CSI HW block found in Tegra20 and Tegra30 SoC.
>
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
> .../display/tegra/nvidia,tegra20-csi.yaml | 135 ++++++++++++++++++
> 1 file changed, 135 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml
> new file mode 100644
> index 000000000000..817b3097846b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml
> @@ -0,0 +1,135 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-csi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra20 CSI controller
> +
> +maintainers:
> + - Svyatoslav Ryhel <clamor95@gmail.com>
> +
> +properties:
> + compatible:
> + enum:
> + - nvidia,tegra20-csi
> + - nvidia,tegra30-csi
> +
> + reg:
> + maxItems: 1
> +
> + clocks: true
> + clock-names: true
> +
> + avdd-dsi-csi-supply:
> + description: DSI/CSI power supply. Must supply 1.2 V.
> +
> + power-domains:
> + maxItems: 1
> +
> + "#nvidia,mipi-calibrate-cells":
> + description:
> + The number of cells in a MIPI calibration specifier. Should be 1.
> + The single cell specifies an id of the pad that need to be
> + calibrated for a given device. Valid pad ids for receiver would be
> + 0 for CSI-A; 1 for CSI-B; 2 for DSI-A and 3 for DSI-B.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + const: 1
Sorry I didn't bring this up before, but is this ever not 1? If it is
fixed, then you don't really need the property. I prefer it just be
fixed rather than getting a bunch of vendor specific #foo-cells.
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> +patternProperties:
> + "^channel@[0-1]$":
> + type: object
> + description: channel 0 represents CSI-A and 1 represents CSI-B
> + additionalProperties: false
> +
> + properties:
> + reg:
> + maximum: 1
> +
> + nvidia,mipi-calibrate:
> + description: Should contain a phandle and a specifier specifying
> + which pad is used by this CSI channel and needs to be calibrated.
> + $ref: /schemas/types.yaml#/definitions/phandle-array
Sounds like only one entry? Then 'maxItems: 1' is needed. If you drop
#nvidia,mipi-calibrate-cells, then you need to define the arg size too:
items:
- items:
- description: phandle to ...
- description: what the arg contains.
next prev parent reply other threads:[~2025-10-02 1:52 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-25 15:16 [PATCH v3 00/22] tegra-video: add CSI support for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 01/22] clk: tegra: set CSUS as vi_sensor's gate for Tegra20, Tegra30 and Tegra114 Svyatoslav Ryhel
2025-10-01 4:02 ` Mikko Perttunen
2025-09-25 15:16 ` [PATCH v3 02/22] dt-bindings: clock: tegra30: Add IDs for CSI pad clocks Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 03/22] clk: tegra30: add CSI pad clock gates Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 04/22] dt-bindings: display: tegra: document Tegra30 VI and VIP Svyatoslav Ryhel
2025-10-02 1:19 ` Rob Herring (Arm)
2025-09-25 15:16 ` [PATCH v3 05/22] staging: media: tegra-video: expand VI and VIP support to Tegra30 Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 06/22] staging: media: tegra-video: vi: adjust get_selection op check Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 07/22] staging: media: tegra-video: vi: add flip controls only if no source controls are provided Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 08/22] staging: media: tegra-video: csi: move CSI helpers to header Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 09/22] gpu: host1x: convert MIPI to use operation function pointers Svyatoslav Ryhel
2025-10-01 4:18 ` Mikko Perttunen
2025-09-25 15:16 ` [PATCH v3 10/22] staging: media: tegra-video: vi: improve logic of source requesting Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 11/22] staging: media: tegra-video: csi: move avdd-dsi-csi-supply from VI to CSI Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 12/22] arm64: tegra: move avdd-dsi-csi-supply into CSI node Svyatoslav Ryhel
2025-10-01 4:27 ` Mikko Perttunen
2025-09-25 15:16 ` [PATCH v3 13/22] staging: media: tegra-video: tegra20: set correct maximum width and height Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 14/22] staging: media: tegra-video: tegra20: add support for second output of VI Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 15/22] staging: media: tegra-video: tegra20: simplify format align calculations Svyatoslav Ryhel
2025-10-01 4:38 ` Mikko Perttunen
2025-10-01 5:07 ` Svyatoslav Ryhel
2025-10-01 5:35 ` Svyatoslav Ryhel
2025-10-01 7:51 ` Mikko Perttunen
2025-10-01 7:59 ` Svyatoslav Ryhel
2025-10-02 4:00 ` Mikko Perttunen
2025-10-02 5:41 ` Svyatoslav Ryhel
2025-10-02 6:12 ` Mikko Perttunen
2025-10-02 6:20 ` Svyatoslav Ryhel
2025-10-06 18:54 ` Luca Ceresoli
2025-10-07 16:02 ` Svyatoslav Ryhel
2025-10-07 19:37 ` Luca Ceresoli
2025-10-08 5:44 ` Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 16/22] staging: media: tegra-video: tegra20: set VI HW revision Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 17/22] staging: media: tegra-video: tegra20: increase maximum VI clock frequency Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 18/22] staging: media: tegra-video: tegra20: expand format support with RAW8/10 and YUV422 1X16 Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 19/22] staging: media: tegra-video: tegra20: adjust luma buffer stride Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 20/22] dt-bindings: display: tegra: document Tegra20 and Tegra30 CSI Svyatoslav Ryhel
2025-10-02 1:52 ` Rob Herring [this message]
2025-10-02 5:14 ` Svyatoslav Ryhel
2025-10-06 20:31 ` Rob Herring
2025-10-07 5:13 ` Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 21/22] ARM: tegra: add CSI nodes for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 22/22] staging: media: tegra-video: add CSI support " Svyatoslav Ryhel
2025-10-01 5:04 ` Mikko Perttunen
2025-10-01 5:15 ` Svyatoslav Ryhel
2025-10-01 6:38 ` Mikko Perttunen
2025-10-01 15:23 ` Svyatoslav Ryhel
2025-10-02 4:03 ` Mikko Perttunen
2025-10-02 17:49 ` Svyatoslav Ryhel
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