[RFC 5/5] riscv: dts: microchip: add pinctrl nodes for iomux0

Conor Dooley
2025-09-26T14:33:35Z

From: Conor Dooley <conor.dooley@microchip.com>

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
This is in RFC state, the commented out perpiherals use a child to
iomux0, and the patch ultimately adding the pinctrl dts nodes will add
both iomux0 and its child. Please ignore them for now. That's also the
reason for no commit message yet, since the final thing will be
different.
---
.../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 56 +++++++++
.../boot/dts/microchip/mpfs-icicle-kit.dts | 1 -
.../boot/dts/microchip/mpfs-pinctrl.dtsi | 117 ++++++++++++++++++
arch/riscv/boot/dts/microchip/mpfs.dtsi | 9 ++
4 files changed, 182 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-pinctrl.dtsi

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index a6dda55a2d1d..4cf8fd1dd24d 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -1,6 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2021 Microchip Technology Inc */

+#include "mpfs.dtsi"
+#include "mpfs-pinctrl.dtsi"
+
/ {
compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
"microchip,mpfs";
@@ -63,6 +66,15 @@ refclk_ccc: cccrefclk {
};
};

+&can0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can0_fabric>;
+};
+
+&can1 {
+// pinctrl-names = "default";
+};
+
&ccc_nw {
clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
<&refclk_ccc>, <&refclk_ccc>;
@@ -70,3 +82,47 @@ &ccc_nw {
"dll0_ref", "dll1_ref";
status = "okay";
};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_fabric>;
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_fabric>;
+};
+
+&mmuart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmuart1_fabric>;
+};
+
+&mmuart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmuart2_fabric>;
+};
+
+&mmuart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmuart3_fabric>;
+};
+
+&mmuart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmuart4_fabric>;
+};
+
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi_fabric>;
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_fabric>;
+};
+
+&spi1 {
+// pinctrl-names = "default";
+};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index f80df225f72b..3c4d5f576e86 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -3,7 +3,6 @@

/dts-v1/;

-#include "mpfs.dtsi"
#include "mpfs-icicle-kit-fabric.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
diff --git a/arch/riscv/boot/dts/microchip/mpfs-pinctrl.dtsi b/arch/riscv/boot/dts/microchip/mpfs-pinctrl.dtsi
new file mode 100644
index 000000000000..1e4d55bd786f
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-pinctrl.dtsi
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#define MPFS_PINFUNC(pin, func) (((pin) << 16) | (func))
+
+&iomux0 {
+ spi0_mssio: spi0-mssio-pins {
+ pinmux = <MPFS_PINFUNC(0, 0)>;
+ };
+
+ spi0_fabric: spi0-fabric-pins {
+ pinmux = <MPFS_PINFUNC(0, 1)>;
+ };
+
+ spi1_mssio: spi1-mssio-pins {
+ pinmux = <MPFS_PINFUNC(1, 0)>;
+ };
+
+ spi1_fabric: spi1-fabric-pins {
+ pinmux = <MPFS_PINFUNC(1, 1)>;
+ };
+
+ i2c0_mssio: i2c0-mssio-pins {
+ pinmux = <MPFS_PINFUNC(2, 0)>;
+ };
+
+ i2c0_fabric: i2c0-fabric-pins {
+ pinmux = <MPFS_PINFUNC(2, 1)>;
+ };
+
+ i2c1_mssio: i2c1-mssio-pins {
+ pinmux = <MPFS_PINFUNC(3, 0)>;
+ };
+
+ i2c1_fabric: i2c1-fabric-pins {
+ pinmux = <MPFS_PINFUNC(3, 1)>;
+ };
+
+ can0_mssio: can0-mssio-pins {
+ pinmux = <MPFS_PINFUNC(4, 0)>;
+ };
+
+ can0_fabric: can0-fabric-pins {
+ pinmux = <MPFS_PINFUNC(4, 1)>;
+ };
+
+ can1_mssio: can1-mssio-pins {
+ pinmux = <MPFS_PINFUNC(5, 0)>;
+ };
+
+ can1_fabric: can1-fabric-pins {
+ pinmux = <MPFS_PINFUNC(5, 1)>;
+ };
+
+ qspi_mssio: qspi-mssio-pins {
+ pinmux = <MPFS_PINFUNC(6, 0)>;
+ };
+
+ qspi_fabric: qspi-fabric-pins {
+ pinmux = <MPFS_PINFUNC(6, 1)>;
+ };
+
+ mmuart0_mssio: mmuart0-mssio-pins {
+ pinmux = <MPFS_PINFUNC(7, 0)>;
+ };
+
+ mmuart0_fabric: mmuart0-fabric-pins {
+ pinmux = <MPFS_PINFUNC(7, 1)>;
+ };
+
+ mmuart1_mssio: mmuart1-mssio-pins {
+ pinmux = <MPFS_PINFUNC(8, 0)>;
+ };
+
+ mmuart1_fabric: mmuart1-fabric-pins {
+ pinmux = <MPFS_PINFUNC(8, 1)>;
+ };
+
+ mmuart2_mssio: mmuart2-mssio-pins {
+ pinmux = <MPFS_PINFUNC(9, 0)>;
+ };
+
+ mmuart2_fabric: mmuart2-fabric-pins {
+ pinmux = <MPFS_PINFUNC(9, 1)>;
+ };
+
+ mmuart3_mssio: mmuart3-mssio-pins {
+ pinmux = <MPFS_PINFUNC(10, 0)>;
+ };
+
+ mmuart3_fabric: mmuart3-fabric-pins {
+ pinmux = <MPFS_PINFUNC(10, 1)>;
+ };
+
+ mmuart4_mssio: mmuart4-mssio-pins {
+ pinmux = <MPFS_PINFUNC(11, 0)>;
+ };
+
+ mmuart4_fabric: mmuart4-fabric-pins {
+ pinmux = <MPFS_PINFUNC(11, 1)>;
+ };
+
+ mdio0_mssio: mdio0-mssio-pins {
+ pinmux = <MPFS_PINFUNC(12, 0)>;
+ };
+
+ mdio0_fabric: mdio0-fabric-pins {
+ pinmux = <MPFS_PINFUNC(12, 1)>;
+ };
+
+ mdio1_mssio: mdio1-mssio-pins {
+ pinmux = <MPFS_PINFUNC(13, 0)>;
+ };
+
+ mdio1_fabric: mdio1-fabric-pins {
+ pinmux = <MPFS_PINFUNC(13, 1)>;
+ };
+};
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 5c2963e269b8..0a0cfd3d3054 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -254,7 +254,16 @@ pdma: dma-controller@3000000 {
mss_top_sysreg: syscon@20002000 {
compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd";
reg = <0x0 0x20002000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
#reset-cells = <1>;
+
+ iomux0: pinctrl@200 {
+ compatible = "microchip,mpfs-pinctrl-iomux0";
+ reg = <0x200 0x4>;
+ pinctrl-use-default;
+
+ };
};

sysreg_scb: syscon@20003000 {
--
2.47.3