From: Conor Dooley <conor@kernel.org>
To: Svyatoslav Ryhel <clamor95@gmail.com>
Cc: "Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Thierry Reding" <thierry.reding@gmail.com>,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Sowjanya Komatineni" <skomatineni@nvidia.com>,
"Luca Ceresoli" <luca.ceresoli@bootlin.com>,
"Prashant Gaikwad" <pgaikwad@nvidia.com>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Mikko Perttunen" <mperttunen@nvidia.com>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Mauro Carvalho Chehab" <mchehab@kernel.org>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Jonas Schwöbel" <jonasschwoebel@yahoo.de>,
"Dmitry Osipenko" <digetx@gmail.com>,
"Charan Pedumuru" <charan.pedumuru@gmail.com>,
"Diogo Ivo" <diogo.ivo@tecnico.ulisboa.pt>,
"Aaron Kling" <webgeek1234@gmail.com>,
"Arnd Bergmann" <arnd@arndb.de>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-media@vger.kernel.org, linux-clk@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-staging@lists.linux.dev
Subject: Re: [PATCH v4 22/24] dt-bindings: display: tegra: document Tegra20 and Tegra30 CSI
Date: Thu, 9 Oct 2025 18:02:50 +0100 [thread overview]
Message-ID: <20251009-steerable-babied-7b5f7a2c58da@spud> (raw)
In-Reply-To: <CAPVz0n1NYL+t-KC1FwHYXuQ0C483ay3g8zP4SmBKVC2rh=x4Bg@mail.gmail.com>
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On Thu, Oct 09, 2025 at 08:35:22AM +0300, Svyatoslav Ryhel wrote:
> чт, 9 жовт. 2025 р. о 00:22 Conor Dooley <conor@kernel.org> пише:
> >
> > On Wed, Oct 08, 2025 at 10:21:06PM +0100, Conor Dooley wrote:
> > > On Wed, Oct 08, 2025 at 10:30:44AM +0300, Svyatoslav Ryhel wrote:
> > > Of course you'd then have to add minItems: 1 and maxItems: 3 to the
> > > extracted definitions.
>
> What do you mean by your last statement? Add minItems: 1 and maxItems:
> 3 like this?
>
> This does to common properties
> clocks:
> minItems: 1
> maxItems: 3
> items:
> - description: module clock
> - description: PAD A clock
> - description: PAD B clock
>
> clock-names:
> minItems: 1
> maxItems: 3
> items:
> - const: csi
> - const: csia-pad
> - const: csib-pad
Yes, that is what I meant.
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next prev parent reply other threads:[~2025-10-09 17:02 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-08 7:30 [PATCH v4 00/24] tegra-video: add CSI support for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-10-08 7:30 ` [PATCH v4 01/24] pinctrl: tegra20: register csus_mux clock Svyatoslav Ryhel
2025-10-13 13:12 ` Linus Walleij
2025-10-14 5:15 ` Mikko Perttunen
2025-10-14 12:03 ` Linus Walleij
2025-10-08 7:30 ` [PATCH v4 02/24] clk: tegra: set CSUS as vi_sensor's gate for Tegra20, Tegra30 and Tegra114 Svyatoslav Ryhel
2025-10-14 5:16 ` Mikko Perttunen
2025-10-08 7:30 ` [PATCH v4 03/24] dt-bindings: clock: tegra30: Add IDs for CSI pad clocks Svyatoslav Ryhel
2025-10-08 7:30 ` [PATCH v4 04/24] clk: tegra30: add CSI pad clock gates Svyatoslav Ryhel
2025-10-08 7:30 ` [PATCH v4 05/24] dt-bindings: display: tegra: document Tegra30 VI and VIP Svyatoslav Ryhel
2025-10-08 7:30 ` [PATCH v4 06/24] staging: media: tegra-video: expand VI and VIP support to Tegra30 Svyatoslav Ryhel
2025-10-08 7:30 ` [PATCH v4 07/24] staging: media: tegra-video: vi: adjust get_selection op check Svyatoslav Ryhel
2025-10-08 7:30 ` [PATCH v4 08/24] staging: media: tegra-video: vi: add flip controls only if no source controls are provided Svyatoslav Ryhel
2025-10-08 7:30 ` [PATCH v4 09/24] staging: media: tegra-video: csi: move CSI helpers to header Svyatoslav Ryhel
2025-10-08 7:30 ` [PATCH v4 10/24] gpu: host1x: convert MIPI to use operation function pointers Svyatoslav Ryhel
2025-10-14 5:35 ` Mikko Perttunen
2025-10-08 7:30 ` [PATCH v4 11/24] dt-bindings: display: tegra: document Tegra132 MIPI calibration device Svyatoslav Ryhel
2025-10-08 21:14 ` Conor Dooley
2025-10-09 5:12 ` Svyatoslav Ryhel
2025-10-09 17:01 ` Conor Dooley
2025-10-08 7:30 ` [PATCH v4 12/24] staging: media: tegra-video: vi: improve logic of source requesting Svyatoslav Ryhel
2025-10-08 7:30 ` [PATCH v4 13/24] staging: media: tegra-video: csi: move avdd-dsi-csi-supply from VI to CSI Svyatoslav Ryhel
2025-10-08 7:30 ` [PATCH v4 14/24] arm64: tegra: move avdd-dsi-csi-supply into CSI node Svyatoslav Ryhel
2025-10-08 7:30 ` [PATCH v4 15/24] staging: media: tegra-video: tegra20: set correct maximum width and height Svyatoslav Ryhel
2025-10-08 7:30 ` [PATCH v4 16/24] staging: media: tegra-video: tegra20: add support for second output of VI Svyatoslav Ryhel
2025-10-08 7:30 ` [PATCH v4 17/24] staging: media: tegra-video: tegra20: adjust format align calculations Svyatoslav Ryhel
2025-10-20 2:34 ` Mikko Perttunen
2025-10-08 7:30 ` [PATCH v4 18/24] staging: media: tegra-video: tegra20: set VI HW revision Svyatoslav Ryhel
2025-10-08 7:30 ` [PATCH v4 19/24] staging: media: tegra-video: tegra20: increase maximum VI clock frequency Svyatoslav Ryhel
2025-10-08 7:30 ` [PATCH v4 20/24] staging: media: tegra-video: tegra20: expand format support with RAW8/10 and YUV422/YUV420p 1X16 Svyatoslav Ryhel
2025-10-08 7:30 ` [PATCH v4 21/24] staging: media: tegra-video: tegra20: adjust luma buffer stride Svyatoslav Ryhel
2025-10-08 7:30 ` [PATCH v4 22/24] dt-bindings: display: tegra: document Tegra20 and Tegra30 CSI Svyatoslav Ryhel
2025-10-08 21:21 ` Conor Dooley
2025-10-08 21:22 ` Conor Dooley
2025-10-09 5:35 ` Svyatoslav Ryhel
2025-10-09 17:02 ` Conor Dooley [this message]
2025-10-13 15:53 ` Frank Li
2025-10-08 7:30 ` [PATCH v4 23/24] ARM: tegra: add CSI nodes for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-10-20 2:36 ` Mikko Perttunen
2025-10-08 7:30 ` [PATCH v4 24/24] staging: media: tegra-video: add CSI support " Svyatoslav Ryhel
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