From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>,
Andy Shevchenko <andy@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>
Subject: [PATCH v1 03/10] pinctrl: cannonlake: Switch to INTEL_GPP() macro
Date: Tue, 4 Nov 2025 15:56:37 +0100 [thread overview]
Message-ID: <20251104145814.1018867-4-andriy.shevchenko@linux.intel.com> (raw)
In-Reply-To: <20251104145814.1018867-1-andriy.shevchenko@linux.intel.com>
Replace custom macro with the recently defined INTEL_GPP().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/intel/pinctrl-cannonlake.c | 68 ++++++++++------------
1 file changed, 30 insertions(+), 38 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c
index 14a5d339385d..a3ffd19fd5be 100644
--- a/drivers/pinctrl/intel/pinctrl-cannonlake.c
+++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c
@@ -28,14 +28,6 @@
#define CNL_H_GPI_IS 0x100
#define CNL_H_GPI_IE 0x120
-#define CNL_GPP(r, s, e, g) \
- { \
- .reg_num = (r), \
- .base = (s), \
- .size = ((e) - (s) + 1), \
- .gpio_base = (g), \
- }
-
#define CNL_LP_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_LP)
@@ -362,32 +354,32 @@ static const struct pinctrl_pin_desc cnlh_pins[] = {
};
static const struct intel_padgroup cnlh_community0_gpps[] = {
- CNL_GPP(0, 0, 24, 0), /* GPP_A */
- CNL_GPP(1, 25, 50, 32), /* GPP_B */
+ INTEL_GPP(0, 0, 24, 0), /* GPP_A */
+ INTEL_GPP(1, 25, 50, 32), /* GPP_B */
};
static const struct intel_padgroup cnlh_community1_gpps[] = {
- CNL_GPP(0, 51, 74, 64), /* GPP_C */
- CNL_GPP(1, 75, 98, 96), /* GPP_D */
- CNL_GPP(2, 99, 106, 128), /* GPP_G */
- CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */
- CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */
- CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */
+ INTEL_GPP(0, 51, 74, 64), /* GPP_C */
+ INTEL_GPP(1, 75, 98, 96), /* GPP_D */
+ INTEL_GPP(2, 99, 106, 128), /* GPP_G */
+ INTEL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */
+ INTEL_GPP(4, 115, 146, 160), /* vGPIO_0 */
+ INTEL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */
};
static const struct intel_padgroup cnlh_community3_gpps[] = {
- CNL_GPP(0, 155, 178, 192), /* GPP_K */
- CNL_GPP(1, 179, 202, 224), /* GPP_H */
- CNL_GPP(2, 203, 215, 256), /* GPP_E */
- CNL_GPP(3, 216, 239, 288), /* GPP_F */
- CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */
+ INTEL_GPP(0, 155, 178, 192), /* GPP_K */
+ INTEL_GPP(1, 179, 202, 224), /* GPP_H */
+ INTEL_GPP(2, 203, 215, 256), /* GPP_E */
+ INTEL_GPP(3, 216, 239, 288), /* GPP_F */
+ INTEL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */
};
static const struct intel_padgroup cnlh_community4_gpps[] = {
- CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */
- CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */
- CNL_GPP(2, 269, 286, 320), /* GPP_I */
- CNL_GPP(3, 287, 298, 352), /* GPP_J */
+ INTEL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */
+ INTEL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */
+ INTEL_GPP(2, 269, 286, 320), /* GPP_I */
+ INTEL_GPP(3, 287, 298, 352), /* GPP_J */
};
static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 };
@@ -780,25 +772,25 @@ static const struct intel_function cnllp_functions[] = {
};
static const struct intel_padgroup cnllp_community0_gpps[] = {
- CNL_GPP(0, 0, 24, 0), /* GPP_A */
- CNL_GPP(1, 25, 50, 32), /* GPP_B */
- CNL_GPP(2, 51, 58, 64), /* GPP_G */
- CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */
+ INTEL_GPP(0, 0, 24, 0), /* GPP_A */
+ INTEL_GPP(1, 25, 50, 32), /* GPP_B */
+ INTEL_GPP(2, 51, 58, 64), /* GPP_G */
+ INTEL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */
};
static const struct intel_padgroup cnllp_community1_gpps[] = {
- CNL_GPP(0, 68, 92, 96), /* GPP_D */
- CNL_GPP(1, 93, 116, 128), /* GPP_F */
- CNL_GPP(2, 117, 140, 160), /* GPP_H */
- CNL_GPP(3, 141, 172, 192), /* vGPIO */
- CNL_GPP(4, 173, 180, 224), /* vGPIO */
+ INTEL_GPP(0, 68, 92, 96), /* GPP_D */
+ INTEL_GPP(1, 93, 116, 128), /* GPP_F */
+ INTEL_GPP(2, 117, 140, 160), /* GPP_H */
+ INTEL_GPP(3, 141, 172, 192), /* vGPIO */
+ INTEL_GPP(4, 173, 180, 224), /* vGPIO */
};
static const struct intel_padgroup cnllp_community4_gpps[] = {
- CNL_GPP(0, 181, 204, 256), /* GPP_C */
- CNL_GPP(1, 205, 228, 288), /* GPP_E */
- CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */
- CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
+ INTEL_GPP(0, 181, 204, 256), /* GPP_C */
+ INTEL_GPP(1, 205, 228, 288), /* GPP_E */
+ INTEL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */
+ INTEL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
};
static const struct intel_community cnllp_communities[] = {
--
2.50.1
next prev parent reply other threads:[~2025-11-04 14:58 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-04 14:56 [PATCH v1 00/10] pinctrl: intel: Consolidate struct intel_padgroup initialisers Andy Shevchenko
2025-11-04 14:56 ` [PATCH v1 01/10] pinctrl: intel: Introduce INTEL_GPP() macro Andy Shevchenko
2025-11-04 14:56 ` [PATCH v1 02/10] pinctrl: alderlake: Switch to " Andy Shevchenko
2025-11-05 10:31 ` Mika Westerberg
2025-11-05 11:40 ` Andy Shevchenko
2025-11-05 11:50 ` Mika Westerberg
2025-11-05 11:51 ` Andy Shevchenko
2025-11-05 11:55 ` Mika Westerberg
2025-11-05 15:27 ` Andy Shevchenko
2025-11-05 15:41 ` Mika Westerberg
2025-11-05 17:11 ` Andy Shevchenko
2025-11-04 14:56 ` Andy Shevchenko [this message]
2025-11-04 14:56 ` [PATCH v1 04/10] pinctrl: icelake: " Andy Shevchenko
2025-11-04 14:56 ` [PATCH v1 05/10] pinctrl: jasperlake: " Andy Shevchenko
2025-11-04 14:56 ` [PATCH v1 06/10] pinctrl: lakefield: " Andy Shevchenko
2025-11-04 14:56 ` [PATCH v1 07/10] pinctrl: meteorlake: " Andy Shevchenko
2025-11-04 14:56 ` [PATCH v1 08/10] pinctrl: meteorpoint: " Andy Shevchenko
2025-11-04 14:56 ` [PATCH v1 09/10] pinctrl: tigerlake: " Andy Shevchenko
2025-11-04 14:56 ` [PATCH v1 10/10] pinctrl: sunrisepoint: " Andy Shevchenko
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