[DO NOT APPLY v8 09/15] pwm: rzg2l-gpt: Add support for output disable request from gpt

Biju
2025-11-21T16:08:53Z

When dead time error occurs or the GTIOCA pin output value is
the same as the GTIOCB pin output value, output protection is
required. GPT detects this condition and generates output disable
requests to POEG based on the settings in the output disable request
permission bits, such as GTINTAD.GRPDTE, GTINTAD.GRPABH,
GTINTAD.GRPABL. After the POEG receives output disable requests from
each channel and calculates external input using an OR operation, the
POEG generates output disable requests to GPT.

Add support for output disable request from gpt, when output level is
high for both IOs at the same time.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/pwm/pwm-rzg2l-gpt.c | 99 +++++++++++++++++++++++++++++++++++
include/linux/pwm/rzg2l-gpt.h | 33 ++++++++++++
2 files changed, 132 insertions(+)
create mode 100644 include/linux/pwm/rzg2l-gpt.h

diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
index aabd2d576231..8006c62068b6 100644
--- a/drivers/pwm/pwm-rzg2l-gpt.c
+++ b/drivers/pwm/pwm-rzg2l-gpt.c
@@ -29,6 +29,7 @@
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
+#include <linux/pwm/rzg2l-gpt.h>
#include <linux/reset.h>
#include <linux/time.h>
#include <linux/units.h>
@@ -40,6 +41,7 @@
#define RZG2L_GTUDDTYC(ch) (0x30 + RZG2L_GET_CH_OFFS(ch))
#define RZG2L_GTIOR(ch) (0x34 + RZG2L_GET_CH_OFFS(ch))
#define RZG2L_GTINTAD(ch) (0x38 + RZG2L_GET_CH_OFFS(ch))
+#define RZG2L_GTST(ch) (0x3c + RZG2L_GET_CH_OFFS(ch))
#define RZG2L_GTBER(ch) (0x40 + RZG2L_GET_CH_OFFS(ch))
#define RZG2L_GTCNT(ch) (0x48 + RZG2L_GET_CH_OFFS(ch))
#define RZG2L_GTCCR(ch, sub_ch) (0x4c + RZG2L_GET_CH_OFFS(ch) + 4 * (sub_ch))
@@ -82,6 +84,12 @@
RZG2L_GTIOR_GTIOA_OUT_HI_END_TOGGLE_CMP_MATCH)

#define RZG2L_GTINTAD_GRP_MASK GENMASK(25, 24)
+#define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH BIT(29)
+
+#define RZG2L_GTST_OABHF BIT(29)
+#define RZG2L_GTST_OABLF BIT(30)
+
+#define RZG2L_GTST_POEG_IRQ_MASK GENMASK(30, 28)

#define RZG2L_MAX_HW_CHANNELS 8
#define RZG2L_CHANNELS_PER_IO 2
@@ -395,6 +403,96 @@ static const struct pwm_ops rzg2l_gpt_ops = {
.apply = rzg2l_gpt_apply,
};

+u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp)
+{
+ struct rzg2l_gpt_chip *rzg2l_gpt = dev_get_drvdata(dev);
+ u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS;
+ unsigned int i;
+ u8 irq_bitpos;
+ u32 irq_bits;
+ u32 val = 0;
+ u32 reg;
+
+ for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) {
+ if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link))
+ continue;
+ else
+ irq_bitpos = (3 * i);
+
+ reg = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTST(i));
+ irq_bits = FIELD_GET(RZG2L_GTST_POEG_IRQ_MASK, reg);
+ val |= (irq_bits << irq_bitpos);
+ }
+
+ return val;
+}
+EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_irq_status);
+
+int rzg2l_gpt_poeg_disable_req_clr(void *dev, u8 grp)
+{
+ struct rzg2l_gpt_chip *rzg2l_gpt = dev_get_drvdata(dev);
+ u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS;
+ unsigned int i;
+ u32 reg;
+
+ for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) {
+ if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link))
+ continue;
+
+ reg = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTST(i));
+ if (reg & (RZG2L_GTST_OABHF | RZG2L_GTST_OABLF))
+ rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTIOR(i),
+ RZG2L_GTIOR_OBE, 0);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_clr);
+
+int rzg2l_gpt_pin_reenable(void *dev, u8 grp)
+{
+ struct rzg2l_gpt_chip *rzg2l_gpt = dev_get_drvdata(dev);
+ u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS;
+ unsigned int i;
+
+ for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) {
+ if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link))
+ continue;
+
+ rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTIOR(i),
+ RZG2L_GTIOR_OBE, RZG2L_GTIOR_OBE);
+ }
+ return 0;
+}
+EXPORT_SYMBOL_GPL(rzg2l_gpt_pin_reenable);
+
+static int rzg2l_gpt_poeg_disable_req_endisable(void *dev, u8 grp, int op, bool on)
+{
+ struct rzg2l_gpt_chip *rzg2l_gpt = dev_get_drvdata(dev);
+ u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS;
+ unsigned int i;
+
+ for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) {
+ if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link))
+ continue;
+
+ if (on)
+ rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTINTAD(i), op, op);
+ else
+ rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTINTAD(i), op, 0);
+ }
+
+ return 0;
+}
+
+int rzg2l_gpt_poeg_disable_req_both_high(void *dev, u8 grp, bool on)
+{
+ int id = RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH;
+
+ return rzg2l_gpt_poeg_disable_req_endisable(dev, grp, id, on);
+}
+EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_high);
+
/*
* This function links a poeg group{A,B,C,D} with a gpt channel{0..7} and
* configure the pin for output disable.
@@ -526,6 +624,7 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
return dev_err_probe(dev, ret, "Failed to link gpt with poeg\n");

mutex_init(&rzg2l_gpt->lock);
+ platform_set_drvdata(pdev, rzg2l_gpt);

chip->ops = &rzg2l_gpt_ops;
ret = devm_pwmchip_add(dev, chip);
diff --git a/include/linux/pwm/rzg2l-gpt.h b/include/linux/pwm/rzg2l-gpt.h
new file mode 100644
index 000000000000..718aaeca39f2
--- /dev/null
+++ b/include/linux/pwm/rzg2l-gpt.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __LINUX_PWM_RENESAS_RZG2L_GPT_H__
+#define __LINUX_PWM_RENESAS_RZG2L_GPT_H__
+
+#if IS_ENABLED(CONFIG_PWM_RENESAS_RZG2L_GPT)
+u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp);
+int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp);
+int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp);
+int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on);
+#else
+static inline u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp)
+{
+ return -ENODEV;
+}
+
+static inline int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp)
+{
+ return -ENODEV;
+}
+
+static inline int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp)
+{
+ return -ENODEV;
+}
+
+static inline int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on)
+{
+ return -ENODEV;
+}
+
+#endif
+
+#endif /* __LINUX_PWM_RENESAS_RZG2L_GPT_H__ */
--
2.43.0