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Fri, 08 May 2026 04:36:51 -0700 (PDT) Received: from hu-nandam-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36645bdac03sm1256373a91.2.2026.05.08.04.36.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2026 04:36:51 -0700 (PDT) From: Ajay Kumar Nandam To: Bjorn Andersson , Linus Walleij Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/2] pinctrl: qcom: lpass-lpi: Switch to PM clock framework for runtime PM Date: Fri, 8 May 2026 17:06:36 +0530 Message-Id: <20260508113636.3561383-3-ajay.nandam@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260508113636.3561383-1-ajay.nandam@oss.qualcomm.com> References: <20260508113636.3561383-1-ajay.nandam@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA4MDEyMCBTYWx0ZWRfXx4zfOTT4VLKF jLlnfgdZw+MbRIFv5WRfD2M4BtJ2hsbTRondwZMT+qcoA3gSNF/LcxF9FVVYREicl1bFHO7Lt+w wswC2ho+SIRWB2tpuTzZxZnPilP6n1x1L/+4Tz5fxPLDKDRc4xyAfvKZuDqtyoGeyLSqHCICjw9 JH2YGDTBiTT6m9y2zFAwzHuYKgKX1W/TNzgLmlPPABD722pYNLIpERDqWJ4/4wnTVOJ90KDNR3V MzQ2NN8bEzIVFxGfSO2FE7Fas0V7Bve4OmW0j5ih6TLyv4vhRQN1JdaEMq7T0ZYZnitvTNLS6g+ 9bgl1x9SQmdoYQW8CT/wSiW2m+ge5gKugHYSL5Epu50SThAUtTCLQ+nSK+vJpL8/2k6LRD+x16B ikJMdtqEAec5E/q49vel3J+Z9+9QmJGRTcFpBP8HxVizpumy42IhuYpwa3NdKARmm8YjlnjL/Od OwZYzx6JkHnM0i74/bg== X-Proofpoint-GUID: bQDLxlJp9cUlifd5b-RKaHzsRfH4WWkK X-Authority-Analysis: v=2.4 cv=JJQLdcKb c=1 sm=1 tr=0 ts=69fdcad4 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=pmTXJCWftoUlG_UUdvAA:9 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-ORIG-GUID: bQDLxlJp9cUlifd5b-RKaHzsRfH4WWkK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-07_02,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605080120 Convert the LPASS LPI pinctrl driver to use the PM clock framework for runtime power management. This allows the LPASS LPI pinctrl driver to drop clock votes when idle, improves power efficiency on platforms using LPASS LPI island mode, and aligns the driver with common runtime PM patterns used across Qualcomm LPASS subsystems. Guard GPIO register read/write helpers and slew-rate register programming with synchronous runtime PM calls so the device is active during MMIO operations whenever autosuspend is enabled. Signed-off-by: Ajay Kumar Nandam --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 109 +++++++++++++----- .../pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 7 ++ 2 files changed, 84 insertions(+), 32 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 15ced5027579..cd5dd18fd149 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include "../pinctrl-utils.h" @@ -22,7 +24,6 @@ #define MAX_NR_GPIO 32 #define GPIO_FUNC 0 -#define MAX_LPI_NUM_CLKS 2 struct lpi_pinctrl { struct device *dev; @@ -31,7 +32,6 @@ struct lpi_pinctrl { struct pinctrl_desc desc; char __iomem *tlmm_base; char __iomem *slew_base; - struct clk_bulk_data clks[MAX_LPI_NUM_CLKS]; /* Protects from concurrent register updates */ struct mutex lock; DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO); @@ -39,29 +39,43 @@ struct lpi_pinctrl { }; static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, - unsigned int addr) + unsigned int addr, u32 *val) { u32 pin_offset; + int ret; if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) pin_offset = state->data->groups[pin].pin_offset; else pin_offset = LPI_TLMM_REG_OFFSET * pin; - return ioread32(state->tlmm_base + pin_offset + addr); + ret = pm_runtime_resume_and_get(state->dev); + if (ret < 0) + return ret; + + *val = ioread32(state->tlmm_base + pin_offset + addr); + pm_runtime_put_autosuspend(state->dev); + + return 0; } static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr, unsigned int val) { u32 pin_offset; + int ret; if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) pin_offset = state->data->groups[pin].pin_offset; else pin_offset = LPI_TLMM_REG_OFFSET * pin; + ret = pm_runtime_resume_and_get(state->dev); + if (ret < 0) + return ret; + iowrite32(val, state->tlmm_base + pin_offset + addr); + pm_runtime_put_autosuspend(state->dev); return 0; } @@ -107,8 +121,8 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, { struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); const struct lpi_pingroup *g = &pctrl->data->groups[group]; - u32 val; - int i, pin = g->pin; + u32 val, io_val; + int i, pin = g->pin, ret; for (i = 0; i < g->nfuncs; i++) { if (g->funcs[i] == function) @@ -119,7 +133,9 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, return -EINVAL; mutex_lock(&pctrl->lock); - val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG); + ret = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG, &val); + if (ret) + goto unlock; /* * If this is the first time muxing to GPIO and the direction is @@ -129,24 +145,32 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, */ if (i == GPIO_FUNC && (val & LPI_GPIO_OE_MASK) && !test_and_set_bit(group, pctrl->ever_gpio)) { - u32 io_val = lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG); + ret = lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG, &io_val); + if (ret) + goto unlock; if (io_val & LPI_GPIO_VALUE_IN_MASK) { if (!(io_val & LPI_GPIO_VALUE_OUT_MASK)) - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, - io_val | LPI_GPIO_VALUE_OUT_MASK); + ret = lpi_gpio_write(pctrl, group, + LPI_GPIO_VALUE_REG, + io_val | LPI_GPIO_VALUE_OUT_MASK); } else { if (io_val & LPI_GPIO_VALUE_OUT_MASK) - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, - io_val & ~LPI_GPIO_VALUE_OUT_MASK); + ret = lpi_gpio_write(pctrl, group, + LPI_GPIO_VALUE_REG, + io_val & ~LPI_GPIO_VALUE_OUT_MASK); } + if (ret) + goto unlock; } u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK); - lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); + ret = lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); + +unlock: mutex_unlock(&pctrl->lock); - return 0; + return ret; } static const struct pinmux_ops lpi_gpio_pinmux_ops = { @@ -162,11 +186,15 @@ static int lpi_config_get(struct pinctrl_dev *pctldev, unsigned int param = pinconf_to_config_param(*config); struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev); unsigned int arg = 0; + int ret; int is_out; int pull; u32 ctl_reg; - ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG); + ret = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG, &ctl_reg); + if (ret) + return ret; + is_out = ctl_reg & LPI_GPIO_OE_MASK; pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg); @@ -206,7 +234,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, { unsigned long sval; void __iomem *reg; - int slew_offset; + int slew_offset, ret; if (slew > LPI_SLEW_RATE_MAX) { dev_err(pctrl->dev, "invalid slew rate %u for pin: %d\n", @@ -225,6 +253,10 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, else reg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG; + ret = pm_runtime_resume_and_get(pctrl->dev); + if (ret < 0) + return ret; + mutex_lock(&pctrl->lock); sval = ioread32(reg); @@ -233,6 +265,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, iowrite32(sval, reg); mutex_unlock(&pctrl->lock); + pm_runtime_put_autosuspend(pctrl->dev); return 0; } @@ -291,21 +324,27 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, */ if (output_enabled) { val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK); - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val); + ret = lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val); + if (ret) + return ret; } mutex_lock(&pctrl->lock); - val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG); + ret = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG, &val); + if (ret) + goto unlock; u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK); u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength), LPI_GPIO_OUT_STRENGTH_MASK); u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK); - lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); + ret = lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); + +unlock: mutex_unlock(&pctrl->lock); - return 0; + return ret; } static const struct pinconf_ops lpi_gpio_pinconf_ops = { @@ -354,9 +393,14 @@ static int lpi_gpio_direction_output(struct gpio_chip *chip, static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin) { struct lpi_pinctrl *state = gpiochip_get_data(chip); + u32 val; + int ret; - return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) & - LPI_GPIO_VALUE_IN_MASK; + ret = lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG, &val); + if (ret) + return ret; + + return val & LPI_GPIO_VALUE_IN_MASK; } static int lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) @@ -399,7 +443,9 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s, pctldev = pctldev ? : state->ctrl; pindesc = pctldev->desc->pins[offset]; - ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG); + if (lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG, &ctl_reg)) + return; + is_out = ctl_reg & LPI_GPIO_OE_MASK; func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg); @@ -482,9 +528,6 @@ int lpi_pinctrl_probe(struct platform_device *pdev) pctrl->data = data; pctrl->dev = &pdev->dev; - pctrl->clks[0].id = "core"; - pctrl->clks[1].id = "audio"; - pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pctrl->tlmm_base)) return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base), @@ -497,13 +540,17 @@ int lpi_pinctrl_probe(struct platform_device *pdev) "Slew resource not provided\n"); } - ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); + ret = devm_pm_clk_create(dev); if (ret) return ret; - ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks); - if (ret) - return dev_err_probe(dev, ret, "Can't enable clocks\n"); + ret = of_pm_clk_add_clks(dev); + if (ret < 0 && ret != -ENODEV) + return ret; + + pm_runtime_set_autosuspend_delay(dev, 100); + pm_runtime_use_autosuspend(dev); + devm_pm_runtime_enable(dev); pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops; pctrl->desc.pmxops = &lpi_gpio_pinmux_ops; @@ -542,7 +589,6 @@ int lpi_pinctrl_probe(struct platform_device *pdev) err_pinctrl: mutex_destroy(&pctrl->lock); - clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); return ret; } @@ -554,7 +600,6 @@ void lpi_pinctrl_remove(struct platform_device *pdev) int i; mutex_destroy(&pctrl->lock); - clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); for (i = 0; i < pctrl->data->npins; i++) pinctrl_generic_remove_group(pctrl->ctrl, i); diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c index 750f410311a8..64a200dd8f41 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include "pinctrl-lpass-lpi.h" @@ -139,10 +141,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { .name = "qcom-sc7280-lpass-lpi-pinctrl", .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, -- 2.34.1