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Allow it to build with COMPILE_TEST so it gets coverage on non-ARM platforms. Drop the ARM-specific IOMEM() casts around the register pointer. The pointer is already __iomem, so readl() and writel() can use it directly. Tested with: make LLVM=1 ARCH=loongarch drivers/gpio/gpio-zevio.o Assisted-by: Codex:GPT-5.5 Signed-off-by: Rosen Penev --- drivers/gpio/Kconfig | 2 +- drivers/gpio/gpio-zevio.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 16c798446c46..f8e34b16fd99 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -859,7 +859,7 @@ config GPIO_XTENSA config GPIO_ZEVIO bool "LSI ZEVIO SoC memory mapped GPIOs" - depends on ARM + depends on ARM || COMPILE_TEST help Say yes here to support the GPIO controller in LSI ZEVIO SoCs. diff --git a/drivers/gpio/gpio-zevio.c b/drivers/gpio/gpio-zevio.c index 29375bea2289..af0158522ac5 100644 --- a/drivers/gpio/gpio-zevio.c +++ b/drivers/gpio/gpio-zevio.c @@ -64,14 +64,14 @@ static inline u32 zevio_gpio_port_get(struct zevio_gpio *c, unsigned pin, unsigned port_offset) { unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE; - return readl(IOMEM(c->regs + section_offset + port_offset)); + return readl(c->regs + section_offset + port_offset); } static inline void zevio_gpio_port_set(struct zevio_gpio *c, unsigned pin, unsigned port_offset, u32 val) { unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE; - writel(val, IOMEM(c->regs + section_offset + port_offset)); + writel(val, c->regs + section_offset + port_offset); } /* Functions for struct gpio_chip */ -- 2.54.0