From: Krzysztof Kozlowski <krzk@kernel.org>
To: Paul Louvel <paul.louvel@bootlin.com>
Cc: Qiang Zhao <qiang.zhao@nxp.com>,
"Christophe Leroy (CS GROUP)" <chleroy@kernel.org>,
Thomas Gleixner <tglx@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Linus Walleij <linusw@kernel.org>,
Bartosz Golaszewski <brgl@kernel.org>,
Madhavan Srinivasan <maddy@linux.ibm.com>,
Michael Ellerman <mpe@ellerman.id.au>,
Nicholas Piggin <npiggin@gmail.com>,
linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-gpio@vger.kernel.org,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Subject: Re: [PATCH 04/12] dt-bindings: soc: fsl: qe: Add support of IRQ in QE GPIO
Date: Wed, 8 Jul 2026 10:20:13 +0200 [thread overview]
Message-ID: <20260708-glorious-electric-octopus-e80abe@quoll> (raw)
In-Reply-To: <DJRCWXDUGFY8.1AIUFSEBFTG94@bootlin.com>
On Mon, Jul 06, 2026 at 10:48:32AM +0200, Paul Louvel wrote:
> On Mon Jul 6, 2026 at 8:52 AM CEST, Krzysztof Kozlowski wrote:
> > On Fri, Jul 03, 2026 at 03:30:12PM +0200, Paul Louvel wrote:
> >> Some QE GPIO pins have an associated interrupt line in the QE PIC to
> >> signal state changes on the pin. Add the corresponding
> >> interrupt-controller / nexus properties to the QE GPIO binding.
> >>
> >> Because the GPIO controller does not perform any interrupt handling
> >> itself, a nexus node (interrupt-map) is used to map each GPIO line
> >> supporting IRQ to the parent QE PIC interrupt domain.
> >>
> >> As the QE PIC can be configured to generate an interrupt on either a
> >> high-to-low transition or any change in signal state, three
> >> interrupt-map entries are needed per GPIO pin that can yield an
> >> interrupt (falling, both, and the "none" case which defaults to both in
> >> QE PIC). This overhead is necessary because the interrupt-map-pass-thru
> >> property is not part of the DT specification.
> >>
> >> The interrupt-map property is optional: it is not required for GPIO
> >> banks that have no interrupt capable GPIO line (e.g. port D on MPC8323),
> >> or when interrupt functionality is not used.
> >>
> >> Update the example to show a scenario where each bank supports a
> >> different numbers of IRQs, or no IRQs at all.
> >>
> >> Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
> >> ---
> >> .../bindings/gpio/fsl,mpc8323-qe-pario-bank.yaml | 69 +++++++++++++++++++++-
> >> 1 file changed, 66 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/gpio/fsl,mpc8323-qe-pario-bank.yaml b/Documentation/devicetree/bindings/gpio/fsl,mpc8323-qe-pario-bank.yaml
> >> index 1af99339ff40..0c849a5698f4 100644
> >> --- a/Documentation/devicetree/bindings/gpio/fsl,mpc8323-qe-pario-bank.yaml
> >> +++ b/Documentation/devicetree/bindings/gpio/fsl,mpc8323-qe-pario-bank.yaml
> >> @@ -27,6 +27,17 @@ properties:
> >> "#gpio-cells":
> >> const: 2
> >>
> >> + "#address-cells":
> >> + const: 0
> >> +
> >> + "#interrupt-cells":
> >> + const: 2
> >> +
> >
> > If this has interrupt-cells, then it is a nexus, thus why isn't this
> > also a "interrupt-controller"?
>
> Because these these banks are not interrupt controllers.
> Interrupts are handled by the QE PIC, and the GPIO controller does not do any
> interrupt handling itself.
> In this setup, does it really needs an "interrupt-controller" property?
So this is interrupt-nexus, but not an interrupt-controller. If that's
the case of hardware, then it is fine/correct.
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-07-08 8:20 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-03 13:30 [PATCH 00/12] soc: fsl: qe: QE PIC improvement and add support of IRQs to QUICC ENGINE GPIOs Paul Louvel
2026-07-03 13:30 ` [PATCH 01/12] soc: fsl: qe: Add chained_irq_{enter,exit}() calls in cascade handler Paul Louvel
2026-07-03 13:30 ` [PATCH 02/12] dt-bindings: soc: fsl: qe: Set #interrupt-cells to 2 to support interrupt type encoding Paul Louvel
2026-07-08 8:16 ` Krzysztof Kozlowski
2026-07-03 13:30 ` [PATCH 03/12] dt-bindings: soc: fsl: qe: Convert QE GPIO to DT schema Paul Louvel
2026-07-06 6:48 ` Krzysztof Kozlowski
2026-07-06 9:03 ` Paul Louvel
2026-07-03 13:30 ` [PATCH 04/12] dt-bindings: soc: fsl: qe: Add support of IRQ in QE GPIO Paul Louvel
2026-07-06 6:52 ` Krzysztof Kozlowski
2026-07-06 8:48 ` Paul Louvel
2026-07-08 8:20 ` Krzysztof Kozlowski [this message]
2026-07-03 13:30 ` [PATCH 05/12] soc: fsl: qe: Use generic_handle_domain_irq() Paul Louvel
2026-07-03 13:30 ` [PATCH 06/12] soc: fsl: qe: Iterate over all pending interrupts in cascade handler Paul Louvel
2026-07-03 13:30 ` [PATCH 07/12] soc: fsl: qe: Handle spurious interrupts Paul Louvel
2026-07-03 13:30 ` [PATCH 08/12] soc: fsl: qe: Convert to generic IRQ chip Paul Louvel
2026-07-06 7:29 ` Christophe Leroy (CS GROUP)
2026-07-06 8:56 ` Paul Louvel
2026-07-03 13:30 ` [PATCH 09/12] soc: fsl: qe: Rename irq variable to parent_irq Paul Louvel
2026-07-03 13:30 ` [PATCH 10/12] soc: fsl: qe: Rename host member to domain in struct qepic_data Paul Louvel
2026-07-03 13:30 ` [PATCH 11/12] soc: fsl: qe: Remove useless struct member Paul Louvel
2026-07-03 13:30 ` [PATCH 12/12] soc: fsl: qe: Add support of IRQs in QE GPIO Paul Louvel
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