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Thu, 30 Jul 2026 18:43:42 +0800 Received: from shbuild7.ambarella.net (10.4.8.70) by ambtw-cas3.ambarella.net (10.2.4.228) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Thu, 30 Jul 2026 18:43:41 +0800 From: Long Zhao To: Arnd Bergmann , Alexandre Belloni , , CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , , "Michael Turquette" , Stephen Boyd , , Linus Walleij , , Greg Kroah-Hartman , Jiri Slaby , , Catalin Marinas , Will Deacon , , Long Zhao Subject: [PATCH 04/10] dt-bindings: pinctrl: add Ambarella CV75 pinctrl Date: Thu, 30 Jul 2026 18:43:24 +0800 Message-ID: <20260730104330.81367-5-longzhao@ambarella.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260730104330.81367-1-longzhao@ambarella.com> References: <20260730104330.81367-1-longzhao@ambarella.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain X-Proofpoint-GUID: GUv3i7IBWAu9EPKs0Wuq5WebVmFi4sHm X-Proofpoint-ORIG-GUID: GUv3i7IBWAu9EPKs0Wuq5WebVmFi4sHm X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMwMDA4MCBTYWx0ZWRfXwjOXmroR+mrF g1f55CC4ZO+8j4Uc4xOorZDuU8Z9vh5mGePex7HEvV7axzR6yydisiJ6bX7RSk5nD1zYU1qbi48 u+djlb0A3B4qvsxjAjKqYnOlGvzJJNqVcMh+MJtJySTsncgNj5IASZ58diHRI00blEUkB75Q8e5 PE3ZYjjI1eealRbRRh0cfGHT/Ds4dkp+P2WgQmcX1GdBzFOz20WJhkuufmK3GxIMpH8alDMIoF2 NABbRqQf3ACjzyOfAYOiJTceXzP9wau2K76FXZI7dNktqlTPGvq1eSVp/TxJmg7B+99MtzFkW3k a4l5c5tDm2j/9WKYS+80KY0MtidieLZDzLZ3p11AapGEuiwgD6/QrbX3N5tHelwAvFh4Hc0KGby SgusrWT1m8iWTl9aZ9VjViRoE+Ew4+z5oelQsACnTDvyJiXnCgyb9vi2o2KcHrrN+mr/Kg1ML/W jVdtDZgWa5+sE/qPFSg== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMwMDA4MCBTYWx0ZWRfX8RpevsQ5jjuf D6c461uXXXdonoxZiEFgyRX96gOPLieQEDzhUUCV0xR6UEDfIKRUTrjjxA8Sq3SRIPX72TFCWd8 VNy30C8hWDX0+AWn9O1VLj3/ruGvIzOQo0/PCSG2jOTwTh7ZmL+g X-Authority-Analysis: v=2.4 cv=PNE/P/qC c=1 sm=1 tr=0 ts=6a6b2ae3 cx=c_pps a=DgnZYc2JwZ3KnY28M5UqXQ==:117 a=DgnZYc2JwZ3KnY28M5UqXQ==:17 a=RAioF0-LDSMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=yXVIz-0bn9infC194UBj:22 a=KblO7da7ppA7TBl3N-nE:22 a=gEfo2CItAAAA:8 a=ppJngBeKAAAA:8 a=hceH7U2dzhA7nS9dVpoA:9 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-30_03,2026-07-29_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 adultscore=0 malwarescore=0 clxscore=1015 phishscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607300080 Add the CV75 pin controller binding and pinmux ID header. Signed-off-by: Long Zhao --- .../pinctrl/ambarella,cv75-pinctrl.yaml | 167 ++++++++++++++++++ .../dt-bindings/pinctrl/ambarella,pinctrl.h | 11 ++ 2 files changed, 178 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/ambarella,cv7= 5-pinctrl.yaml create mode 100644 include/dt-bindings/pinctrl/ambarella,pinctrl.h diff --git a/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinct= rl.yaml b/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.= yaml new file mode 100644 index 000000000000..8a331c642fad --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ambarella,cv75-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ambarella CV75 Pin Controller + +maintainers: + - Long Zhao + +description: + The Ambarella CV75 pin controller configures pin multiplexing, bias and + drive strength for the main GPIO banks. Pin multiplexing entries encode + the pin number and alternate function with the AMBA_PINMUX() macro from + dt-bindings/pinctrl/ambarella,pinctrl.h. + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + const: ambarella,cv75-pinctrl + + reg: + items: + - description: GPIO bank 0 registers + - description: GPIO bank 1 registers + - description: GPIO bank 2 registers + - description: IOMUX registers + + reg-names: + items: + - const: gpio0 + - const: gpio1 + - const: gpio2 + - const: iomux + + interrupts: + items: + - description: GPIO bank 0 interrupt + - description: GPIO bank 1 interrupt + - description: GPIO bank 2 interrupt + + ambarella,drive-strength-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: RCT syscon containing the drive-strength registers. + + ambarella,pull-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: Secure scratchpad syscon containing the pull registers. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^gpio@[0-9a-f]+$": + type: object + additionalProperties: false + + properties: + reg: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-ranges: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + required: + - reg + - gpio-controller + - "#gpio-cells" + - gpio-ranges + - interrupt-controller + - "#interrupt-cells" + + "^[a-z0-9-]+-pins$": + type: object + allOf: + - $ref: pinmux-node.yaml# + - $ref: pincfg-node.yaml# + additionalProperties: false + + properties: + function: true + + pinmux: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 96 + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + + drive-strength: + enum: [3, 4, 5, 6, 7, 8, 9, 12] + + required: + - function + - pinmux + +required: + - compatible + - reg + - reg-names + - interrupts + - ambarella,drive-strength-syscon + - ambarella,pull-syscon + - "#address-cells" + - "#size-cells" + +unevaluatedProperties: false + +examples: + - | + #include + #include + + rct: rct { + }; + + scratchpad: scratchpad { + }; + + pinctrl: pinctrl@e4013000 { + compatible =3D "ambarella,cv75-pinctrl"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0xe4013000 0x1000>, <0xe4014000 0x1000>, + <0xe4015000 0x1000>, <0xe4010000 0x1000>; + reg-names =3D "gpio0", "gpio1", "gpio2", "iomux"; + interrupts =3D , + , + ; + ambarella,drive-strength-syscon =3D <&rct>; + ambarella,pull-syscon =3D <&scratchpad>; + + gpio: gpio@0 { + reg =3D <0>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 0 95>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + uart0-pins { + function =3D "uart0"; + pinmux =3D , + ; + bias-disable; + drive-strength =3D <8>; + }; + }; diff --git a/include/dt-bindings/pinctrl/ambarella,pinctrl.h b/include/dt-b= indings/pinctrl/ambarella,pinctrl.h new file mode 100644 index 000000000000..20463d5acc66 --- /dev/null +++ b/include/dt-bindings/pinctrl/ambarella,pinctrl.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2026 Ambarella, Inc. + */ + +#ifndef _DT_BINDINGS_PINCTRL_AMBARELLA_PINCTRL_H +#define _DT_BINDINGS_PINCTRL_AMBARELLA_PINCTRL_H + +#define AMBA_PINMUX(pin, mux) (((mux) << 12) | (pin)) + +#endif -- 2.34.1 NOTE: This email (including attachments) contain Ambarella Proprietary and/= or Confidential Information and is intended solely for the use of the indiv= idual(s) to whom it is addressed. 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