From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F5EF3C456F; Fri, 31 Jul 2026 09:52:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785491542; cv=none; b=Kc8Ad2nDce0vxcqHcoPjIveGJHW0QeRPsv3Ed5+CGLFdMbvQceX5opqa8dWBhXAUujfKxVAjMVYX8HlPV8MLUOdc5DOFJvNytAvCmCFpjWwR+JHyEODcup9DoRgKJi+17fR8S7KA7Tk/o/GVj72GqUZ9QgeY4E2LSZw2PnyH090= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785491542; c=relaxed/simple; bh=+l/K7GkecjCKx6nIA7HKJ2/vMEUVeEnxy+n3sA6Z+0E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gzGHC15MxcsxCnmGqM8hTqygyoyedBGSNjmqUS+eRCeWbTPhE3WS9zUwRSV+VBICKC9msmXtYGPzNpofHGPV6gK4F6uQ+dGjWMsYdD3CsPRKXQ9ld70VIVC7euwRpH4Q8XSuhwEaO8htRJne/UwLYmaT5QgdXIHIUfRGksZQJ9k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=cx4EAWZa; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="cx4EAWZa" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id DBF1B4E4104B; Fri, 31 Jul 2026 09:52:14 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id B10716039A; Fri, 31 Jul 2026 09:52:14 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 90A8D11C1664F; Fri, 31 Jul 2026 11:52:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1785491533; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=fBEwTYcc52+NN3xYVbQslUHBc7dgcc+fOwxRbhxvpBw=; b=cx4EAWZaXcVuc7FyGiqPIrQVB4TdlFNcYSG9WQbhIK/fuYgWawfdw2pTml+As3rwd1Wkvr 4CG39ZFj8OopChvD1bzt5sbdu6IBGGopr89ThFE7vHhcBiKHO7MM9kiMeaLWj4CxTcqzXX WaMu6sMy8sPR7QPpArUrQniOFKQ4vg1vl09xOZ/Pcwop2NCyw1jv2wnSqpD4rIHgGnepwq uROkXKTZmXsBClbhhhyhZWTiP6Mp8nrgWbwZl3mGzXrYXDMyXTjhKR7cBLu7ZbrLONBP4U bmGoqCc8iObLkiTAp+JfXLg9jeW3EF+wiLwGviOLECLePhxFQXlQPNTHnUUkrQ== From: "Thomas Perrot (Schneider Electric)" Date: Fri, 31 Jul 2026 11:51:44 +0200 Subject: [PATCH v8 4/5] gpio: aaeon: Add GPIO driver for SRG-IMX8P MCU Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20260731-dev-b4-aaeon-mcu-driver-v8-4-9ab00e80df2a@bootlin.com> References: <20260731-dev-b4-aaeon-mcu-driver-v8-0-9ab00e80df2a@bootlin.com> In-Reply-To: <20260731-dev-b4-aaeon-mcu-driver-v8-0-9ab00e80df2a@bootlin.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , =?utf-8?q?J=C3=A9r=C3=A9mie_Dautheribes?= , Wim Van Sebroeck , Guenter Roeck , Lee Jones Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-watchdog@vger.kernel.org, Thomas Petazzoni , Miquel Raynal , "Thomas Perrot (Schneider Electric)" , Bartosz Golaszewski X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add GPIO driver for the Aaeon SRG-IMX8P embedded controller. This driver supports 7 GPO (General Purpose Output) pins and 12 GPIO pins that can be configured as inputs or outputs. The driver implements proper state management for GPO pins (which are output-only) and full direction control for GPIO pins. During probe, all pins are reset to a known state (GPOs low, GPIOs as inputs) to prevent undefined behavior across system reboots, as the MCU does not reset GPIO states on soft reboot. Co-developed-by: Jérémie Dautheribes (Schneider Electric) Signed-off-by: Jérémie Dautheribes (Schneider Electric) Acked-by: Bartosz Golaszewski Reviewed-by: Linus Walleij Signed-off-by: Thomas Perrot (Schneider Electric) --- MAINTAINERS | 1 + drivers/gpio/Kconfig | 9 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-aaeon-mcu.c | 230 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 241 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f91b6a1826d0..2538f8c4bc14 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -191,6 +191,7 @@ M: Thomas Perrot R: Jérémie Dautheribes S: Maintained F: Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml +F: drivers/gpio/gpio-aaeon-mcu.c F: drivers/mfd/aaeon-mcu.c F: include/linux/mfd/aaeon-mcu.h diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index c74da29253e8..4b37b5a15958 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -157,6 +157,15 @@ config GPIO_74XX_MMIO 8 bits: 74244 (Input), 74273 (Output) 16 bits: 741624 (Input), 7416374 (Output) +config GPIO_AAEON_MCU + tristate "Aaeon MCU GPIO support" + depends on MFD_AAEON_MCU + help + Select this option to enable GPIO support for the Aaeon SRG-IMX8P + onboard MCU. This driver provides access to GPIO pins and GPO + (General Purpose Output) pins controlled by the microcontroller. + The driver handles both input and output configuration. + config GPIO_ALTERA tristate "Altera GPIO" select GPIOLIB_IRQCHIP diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 2421a8fd3733..1ba6318bc558 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_104_IDI_48) += gpio-104-idi-48.o obj-$(CONFIG_GPIO_104_IDIO_16) += gpio-104-idio-16.o obj-$(CONFIG_GPIO_74X164) += gpio-74x164.o obj-$(CONFIG_GPIO_74XX_MMIO) += gpio-74xx-mmio.o +obj-$(CONFIG_GPIO_AAEON_MCU) += gpio-aaeon-mcu.o obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o obj-$(CONFIG_GPIO_ADP5585) += gpio-adp5585.o diff --git a/drivers/gpio/gpio-aaeon-mcu.c b/drivers/gpio/gpio-aaeon-mcu.c new file mode 100644 index 000000000000..a9e048c865f5 --- /dev/null +++ b/drivers/gpio/gpio-aaeon-mcu.c @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Aaeon MCU GPIO driver + * + * Copyright (C) 2026 Bootlin + * Author: Jérémie Dautheribes + * Author: Thomas Perrot + */ + +#include +#include +#include +#include +#include +#include + +#define AAEON_MCU_CONFIG_GPIO_INPUT 0x69 +#define AAEON_MCU_CONFIG_GPIO_OUTPUT 0x6F +#define AAEON_MCU_READ_GPIO 0x72 +#define AAEON_MCU_WRITE_GPIO 0x77 + +#define AAEON_MCU_CONTROL_GPO 0x6C + +#define MAX_GPIOS 12 +#define MAX_GPOS 7 + +struct aaeon_mcu_gpio { + struct gpio_chip gc; + struct regmap *regmap; + DECLARE_BITMAP(dir_in, MAX_GPOS + MAX_GPIOS); + DECLARE_BITMAP(gpo_state, MAX_GPOS); +}; + +static int aaeon_mcu_gpio_config_input_cmd(struct aaeon_mcu_gpio *data, + unsigned int offset) +{ + return regmap_write(data->regmap, + AAEON_MCU_REG(AAEON_MCU_CONFIG_GPIO_INPUT, offset - 7), + 0); +} + +static int aaeon_mcu_gpo_set_cmd(struct aaeon_mcu_gpio *data, unsigned int offset, int value) +{ + return regmap_write(data->regmap, + AAEON_MCU_REG(AAEON_MCU_CONTROL_GPO, offset + 1), + !!value); +} + +static int aaeon_mcu_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) +{ + struct aaeon_mcu_gpio *data = gpiochip_get_data(gc); + int ret; + + if (offset < MAX_GPOS) { + dev_err(gc->parent, + "offset %d is a GPO (output-only) pin, cannot be configured as input\n", + offset); + return -EOPNOTSUPP; + } + + ret = aaeon_mcu_gpio_config_input_cmd(data, offset); + if (ret < 0) + return ret; + + set_bit(offset, data->dir_in); + + return 0; +} + +static int aaeon_mcu_gpio_config_output_cmd(struct aaeon_mcu_gpio *data, + unsigned int offset, + int value) +{ + int ret; + + ret = regmap_write(data->regmap, + AAEON_MCU_REG(AAEON_MCU_WRITE_GPIO, offset - 7), + !!value); + if (ret < 0) + return ret; + + return regmap_write(data->regmap, + AAEON_MCU_REG(AAEON_MCU_CONFIG_GPIO_OUTPUT, offset - 7), + 0); +} + +static int aaeon_mcu_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) +{ + struct aaeon_mcu_gpio *data = gpiochip_get_data(gc); + int ret; + + if (offset < MAX_GPOS) { + ret = aaeon_mcu_gpo_set_cmd(data, offset, value); + if (ret) + return ret; + assign_bit(offset, data->gpo_state, value); + return 0; + } + + ret = aaeon_mcu_gpio_config_output_cmd(data, offset, value); + if (ret < 0) + return ret; + + clear_bit(offset, data->dir_in); + + return 0; +} + +static int aaeon_mcu_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) +{ + struct aaeon_mcu_gpio *data = gpiochip_get_data(gc); + + return test_bit(offset, data->dir_in) ? + GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; +} + +static int aaeon_mcu_gpio_get(struct gpio_chip *gc, unsigned int offset) +{ + struct aaeon_mcu_gpio *data = gpiochip_get_data(gc); + unsigned int rsp; + int ret; + + if (offset < MAX_GPOS) + return test_bit(offset, data->gpo_state); + + ret = regmap_read(data->regmap, + AAEON_MCU_REG(AAEON_MCU_READ_GPIO, offset - 7), + &rsp); + if (ret < 0) + return ret; + + return rsp; +} + +static int aaeon_mcu_gpio_set_cmd(struct aaeon_mcu_gpio *data, unsigned int offset, int value) +{ + return regmap_write(data->regmap, + AAEON_MCU_REG(AAEON_MCU_WRITE_GPIO, offset - 7), + !!value); +} + +static int aaeon_mcu_gpio_set(struct gpio_chip *gc, unsigned int offset, + int value) +{ + struct aaeon_mcu_gpio *data = gpiochip_get_data(gc); + int ret; + + if (offset >= MAX_GPOS) + return aaeon_mcu_gpio_set_cmd(data, offset, value); + + ret = aaeon_mcu_gpo_set_cmd(data, offset, value); + if (ret) + return ret; + assign_bit(offset, data->gpo_state, value); + return 0; +} + +static const struct gpio_chip aaeon_mcu_chip = { + .label = "gpio-aaeon-mcu", + .owner = THIS_MODULE, + .get_direction = aaeon_mcu_gpio_get_direction, + .direction_input = aaeon_mcu_gpio_direction_input, + .direction_output = aaeon_mcu_gpio_direction_output, + .get = aaeon_mcu_gpio_get, + .set = aaeon_mcu_gpio_set, + .base = -1, + .ngpio = MAX_GPOS + MAX_GPIOS, + .can_sleep = true, +}; + +static void aaeon_mcu_gpio_reset(struct aaeon_mcu_gpio *data, struct device *dev) +{ + unsigned int i; + int ret; + + /* Reset all GPOs */ + for (i = 0; i < MAX_GPOS; i++) { + ret = aaeon_mcu_gpo_set_cmd(data, i, 0); + if (ret < 0) + dev_warn(dev, "Failed to reset GPO %u state: %d\n", i, ret); + clear_bit(i, data->dir_in); + } + + /* Reset all GPIOs */ + for (i = MAX_GPOS; i < MAX_GPOS + MAX_GPIOS; i++) { + ret = aaeon_mcu_gpio_config_input_cmd(data, i); + if (ret < 0) + dev_warn(dev, "Failed to reset GPIO %u state: %d\n", i, ret); + set_bit(i, data->dir_in); + } +} + +static int aaeon_mcu_gpio_probe(struct platform_device *pdev) +{ + struct aaeon_mcu_gpio *data; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!data->regmap) + return -ENODEV; + + data->gc = aaeon_mcu_chip; + data->gc.parent = pdev->dev.parent; + + /* + * Reset all GPIO states to a known configuration. The MCU does not + * reset GPIO state on soft reboot, only on power cycle (hard reboot). + * Without this reset, GPIOs would retain their previous state across + * reboots, which could lead to unexpected behavior. + */ + aaeon_mcu_gpio_reset(data, &pdev->dev); + + return devm_gpiochip_add_data(&pdev->dev, &data->gc, data); +} + +static struct platform_driver aaeon_mcu_gpio_driver = { + .driver = { + .name = "aaeon-mcu-gpio", + }, + .probe = aaeon_mcu_gpio_probe, +}; +module_platform_driver(aaeon_mcu_gpio_driver); + +MODULE_ALIAS("platform:aaeon-mcu-gpio"); +MODULE_DESCRIPTION("GPIO interface for Aaeon MCU"); +MODULE_AUTHOR("Jérémie Dautheribes "); +MODULE_LICENSE("GPL"); -- 2.55.0