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Mon, 03 Aug 2026 15:35:54 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e35]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84edc2d4473sm4186790b3a.40.2026.08.03.15.35.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 15:35:53 -0700 (PDT) From: Rosen Penev To: linux-gpio@vger.kernel.org Cc: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , Linus Walleij , Bartosz Golaszewski , linuxppc-dev@lists.ozlabs.org (open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2 7/8] gpio: ppc44x: fix undefined behavior in GPIO_MASK2 macro Date: Mon, 3 Aug 2026 15:35:38 -0700 Message-ID: <20260803223539.86303-8-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803223539.86303-1-rosenp@gmail.com> References: <20260803223539.86303-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Shifting a 32-bit unsigned integer by 32 or more places is undefined behavior in C. GPIO_MASK2 computes its shift amount as (gpio) * 2, and for pins 16-31 in the OSRH/TSRH bank this yields shifts of 32-62. While this happens to work on PowerPC because slw masks the shift count to the low 5 bits, compilers performing value-range propagation may assume the else branch is unreachable and optimize it away, or may evaluate the shift as zero on other architectures via COMPILE_TEST. Mask gpio to the 16-pin bank index so the shift stays within [0, 30]. The registers are banked (OSRL/TSRL for gpio 0-15, OSRH/TSRH for gpio 16-31) with an identical 2-bit-per-pin layout from MSB to LSB, so masking to the within-bank index preserves the intended behavior. Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev --- drivers/gpio/gpio-ppc44x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-ppc44x.c b/drivers/gpio/gpio-ppc44x.c index fd543fbb959a..9fdc84e922f4 100644 --- a/drivers/gpio/gpio-ppc44x.c +++ b/drivers/gpio/gpio-ppc44x.c @@ -19,7 +19,7 @@ #include #define GPIO_MASK(gpio) (0x80000000 >> (gpio)) -#define GPIO_MASK2(gpio) (0xc0000000 >> ((gpio) * 2)) +#define GPIO_MASK2(gpio) (0xc0000000 >> (((gpio) % 16) * 2)) /* Physical GPIO register layout */ struct ppc44x_gpio { -- 2.55.0