From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5AF2842E414 for ; Thu, 3 Sep 2026 07:31:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788420711; cv=none; b=rMSW1K8nT1l8FS6y+b5HmZJJTwCQIZU9vOqDqzyi57fZoK0izBaxOipbsIPwIcUBMOZlpurYXee1LrAanZv2XP0Wc6fi+fakyWC72KqFVDg7pL1n+cW5C8eQ48+e0w0fCmMT/8lZtwVZowEktMTeCuNwdDO8OGMl3/VZvnCxkys= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788420711; c=relaxed/simple; bh=JvxmjtGbMqSyugsMBtIh4c5EAdeqEgo6V+vHxBIrxQc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PUi+weFuFVNYSUTuuGF5L+hGOHMliAlDuHfusi+Xhi23i9tyCFZb3Qo5G+03i7PInUtnDYcTy+k3OsjDwPFwRdO0aBKuvF/C4IpEMljOueiMKWbzc8fbCjv0raBQmE3gMKvwMBD0YMI6y92JsMiUCCqrB2kiBhgNP+sISotIj48= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=kpAewH3V; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kpAewH3V" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-490cf322ed0so21331705e9.1 for ; Thu, 03 Sep 2026 00:31:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788420707; x=1789025507; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=pbqs3+P/ZX13vEXv3N3Jwum7K59Zn0Nb5bqVSfKORxQ=; b=kpAewH3VuKUTBl4t7LI59WhFJwTEuaOH2nY2ic4QY4gSpDLbZeeNnFlOJtKPyH20DB HaY3rgtTu1DitoTQfdfASgR5NVtPfBr2soq6KX6WNRw7HmSesxb3D9htW/zVIFi4ArvU YvsRDc8RUYamGHTE3mkdCbDKI7ORhUwqIC9wtGIAXIZDh+aIHKMjyZUPIpDAyQkGdCb3 9A0IUpNJinZBJJ3BkeheAP6DZ+pIGAcdfaXXMKq0VS1cFo7Tx709EADVlGivWHA9wdV3 +cQBJsXKMqyOLPnspprS+2oMGqeZUXN90hQkdnQPRi2UkVeAAA1zovMegsP8cttn7djC Y49g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788420707; x=1789025507; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=pbqs3+P/ZX13vEXv3N3Jwum7K59Zn0Nb5bqVSfKORxQ=; b=UabrDjP6kHaqo/qEnGS2lBuUqNoMiqie55Eaw37uPnkbnr5/s0pTMg0TV6Ii+vwn4l BigkDtS3QkqiQukRWx7/XHn3wJEwA39TPIDnQFVj2INmCCIrfyXETbbGJJYipl5llyOv WhwYltDPeAE8eXUP/0E7Wm4RHO3ctQwfoN7yttjrBR2ZSA4qRBJpdGlftfvo9gvB3G+y nNcVRvpXA3QKHqeSVuYMNEWqGVTNlopDD7IcwrOt6IhBTHCylVbR6HRyd/AOVE5q4v7f iqhOJa3TJzaBLkEEPBybZ1uzZbrie90v0loqOKlpDmPWY2wkVBit1+jxU0+5byjtXttK 9B7g== X-Forwarded-Encrypted: i=1; AKwUvBzK3oOk82TDg2p7J1YvlBUqY2Tcnwv0EnA11XFdDzuAn5JP5HWiOa5z7wPm3WGwPlWhQhIufdU+lcIe@vger.kernel.org X-Gm-Message-State: AFuF++nDwT6SX0CJL51Jj9OZh+zfKU5DjeNGQVzdwk+xfW8pcj0RtiG+ aGAWwF0q3FVIGXEeG88+jjvElWqOUjfDB+1CHPqRYdcjkP7eRz5uw9hegoe7E/oR X-Gm-Gg: AYBFou2GR7so0MlGIqCGca4O8B2JpM+db5O629cqnqn8jccVGbqQDL4FblOO8EUUXdV Najaz47qTGSwGW8mo0JEXgVtGdFICReHjd9+QcKzMwHRJfRo+zmgl/1RaOOx4nX9Yg9fytYcHDs jTw4txlz+n440BnQeIFjJK4rf8ug2eTpDnhpTX0QJTGh1cKrSnLYfiejwGblfbXTTIV7355M05J z7QCdZoym8NMmVAt1sHuvCDO4rZLkhNQCMNukGMmzB5WK4U0dfNQpzh8iAuY5FsTmsISkKnWrdc fG9dxqKkU/L7CQnMbxZ/8qgr/r20KgHNFHZt3YIa7d96EicxHzd5ZIMmFoQQ3Pr6JhpTBjmTHS+ oUtCFzOJ7YX4Vo/4KPW+FtFYsfwJ97PaqVmWbEppO0sK0fZ0eiiTzh+sLbKUN25vAxUhGyXhG3d L/pMKKu0kpcco102UdBowHD8x/KT3UrJinoh7TOORx7FnTJphatZM1srRYR3p1YRGPtA== X-Received: by 2002:a05:600c:6992:b0:49a:a101:4157 with SMTP id 5b1f17b1804b1-49ce58034admr192721335e9.7.1788420707039; Thu, 03 Sep 2026 00:31:47 -0700 (PDT) Received: from deb05.proceq.com ([213.160.61.66]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49ce551bf7asm69369455e9.2.2026.09.03.00.31.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Sep 2026 00:31:46 -0700 (PDT) From: Mehmet Fide To: Bartosz Golaszewski , Linus Walleij Cc: Dong Aisheng , Fabio Estevam , Frank Li , Jacky Bai , Sascha Hauer , Pengutronix Kernel Team , imx@lists.linux.dev, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mehmet Fide Subject: [PATCH v4 1/3] pinctrl: imx: answer OUTPUT_ENABLE/INPUT_ENABLE queries from the pad register Date: Thu, 3 Sep 2026 09:31:41 +0200 Message-ID: <20260903073143.2068494-2-mehmet.fide@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260903073143.2068494-1-mehmet.fide@gmail.com> References: <20260903073143.2068494-1-mehmet.fide@gmail.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Mehmet Fide The mmio pinconf get callback ignores which parameter was requested and returns the raw conf register, so a generic query through pinctrl_gpio_get_config() gets register bits back instead of the packed parameter it asked for. Decode the requested parameter and answer PIN_CONFIG_OUTPUT_ENABLE and PIN_CONFIG_INPUT_ENABLE on SoCs that declare where those bits live in the pad register; Vybrid has OBE at bit 1 and IBE at bit 0. The answer is 0 with the bit value as the argument, which is what the pinctrl_gpio_get_config() users (gpio-by-pinctrl, and gpio-mmio in the next patch) expect. Other parameters and the SCU based SoCs, whose firmware call returns the raw pad value as well, get -ENOTSUPP; a pin the device tree never configured gets -EINVAL, as the raw helper already does, so a caller can tell "no answer for this pin" from "this controller never answers". The only in-tree user of the raw register was the debugfs group dump, which called the callback with an uninitialized config; it now reads the register through its own helper, like the single pin dump already did. The set callback is not touched: the fsl,pins binding hands it the raw pad register value and that stays the only thing it accepts. Nothing in-tree sends generic parameters to it on these SoCs; making it understand them is a separate change. This gives gpio-mmio a way to read back the line direction on chips whose direction lives in the pin controller. Suggested-by: Bartosz Golaszewski Signed-off-by: Mehmet Fide --- drivers/pinctrl/freescale/pinctrl-imx.c | 54 +++++++++++++++++++++-- drivers/pinctrl/freescale/pinctrl-imx.h | 4 ++ drivers/pinctrl/freescale/pinctrl-vf610.c | 2 + 3 files changed, 56 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 9a45b376d36f..f08ef52bf4f8 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -21,6 +21,7 @@ #include #include +#include #include #include @@ -291,8 +292,8 @@ struct pinmux_ops imx_pmx_ops = { .set_mux = imx_pmx_set, }; -static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id, - unsigned long *config) +static int imx_pinconf_get_raw_mmio(struct pinctrl_dev *pctldev, + unsigned int pin_id, unsigned long *config) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; @@ -312,16 +313,61 @@ static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id, return 0; } +static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, + unsigned int pin_id, unsigned long *config) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; + const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; + enum pin_config_param param = pinconf_to_config_param(*config); + unsigned int mask; + u32 raw; + + switch (param) { + case PIN_CONFIG_OUTPUT_ENABLE: + mask = info->obe_mask; + break; + case PIN_CONFIG_INPUT_ENABLE: + mask = info->ibe_mask; + break; + default: + mask = 0; + break; + } + + if (!mask) + return -ENOTSUPP; + if (pin_reg->conf_reg == -1) + return -EINVAL; + + raw = readl(ipctl->base + pin_reg->conf_reg); + *config = pinconf_to_config_packed(param, !!(raw & mask)); + + return 0; +} + static int imx_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin_id, unsigned long *config) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; + if (info->flags & IMX_USE_SCU) + return -ENOTSUPP; + + return imx_pinconf_get_mmio(pctldev, pin_id, config); +} + +static int imx_pinconf_get_raw(struct pinctrl_dev *pctldev, + unsigned int pin_id, unsigned long *config) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; + if (info->flags & IMX_USE_SCU) return info->imx_pinconf_get(pctldev, pin_id, config); else - return imx_pinconf_get_mmio(pctldev, pin_id, config); + return imx_pinconf_get_raw_mmio(pctldev, pin_id, config); } static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev, @@ -426,7 +472,7 @@ static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; name = pin_get_name(pctldev, pin->pin); - ret = imx_pinconf_get(pctldev, pin->pin, &config); + ret = imx_pinconf_get_raw(pctldev, pin->pin, &config); if (ret) return; seq_printf(s, " %s: 0x%lx\n", name, config); diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h index f65ff45b4003..8fa7e1e2521d 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -91,6 +91,10 @@ struct imx_pinctrl_soc_info { unsigned int mux_mask; u8 mux_shift; + /* OBE/IBE bits in the conf register, 0 if the pad does not have them */ + unsigned int obe_mask; + unsigned int ibe_mask; + int (*gpio_set_direction)(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset, diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c index 76a4bc0181a0..77d077618782 100644 --- a/drivers/pinctrl/freescale/pinctrl-vf610.c +++ b/drivers/pinctrl/freescale/pinctrl-vf610.c @@ -319,6 +319,8 @@ static const struct imx_pinctrl_soc_info vf610_pinctrl_info = { .gpio_set_direction = vf610_pmx_gpio_set_direction, .mux_mask = 0x700000, .mux_shift = 20, + .obe_mask = 0x2, + .ibe_mask = 0x1, }; static const struct of_device_id vf610_pinctrl_of_match[] = { -- 2.54.0