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Thu, 17 Sep 2026 16:06:51 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e34]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39e360ddfc2sm7079782a91.16.2026.09.17.16.06.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Sep 2026 16:06:51 -0700 (PDT) From: Rosen Penev To: linux-gpio@vger.kernel.org Cc: Linus Walleij , Bartosz Golaszewski , Alexandre Courbot , Thomas Petazzoni , linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2] gpio: mvebu: fix Armada XP per-CPU mask register save/restore Date: Thu, 17 Sep 2026 16:06:50 -0700 Message-ID: <20260917230650.117403-1-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Armada XP variant keeps the per-CPU edge/level mask registers in a second I/O window (percpu_regs) rather than in the main GPIO window. The suspend and resume paths however read and wrote them through mvchip->regs with the per-CPU offsets, which hits the global GPIO_EDGE_MASK / GPIO_LEVEL_MASK registers instead. Per-CPU mask state was therefore lost across suspend/resume, so a level line could end up unmasked behind genirq's back and trigger an interrupt storm once interrupts are re-enabled. Use mvchip->percpu_regs for the Armada XP per-CPU mask registers in both the suspend save and the resume restore paths, matching the mask/unmask handlers and the probe-time masking. Fixes: b5b7b487431b ("gpio: mvebu: add suspend/resume support") Cc: stable@vger.kernel.org Assisted-by: LLM Signed-off-by: Rosen Penev --- v2: rebase drivers/gpio/gpio-mvebu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c index 267e6d5bacd0..cdd918581540 100644 --- a/drivers/gpio/gpio-mvebu.c +++ b/drivers/gpio/gpio-mvebu.c @@ -1028,10 +1028,10 @@ static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state) break; case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: for (i = 0; i < 4; i++) { - regmap_read(mvchip->regs, + regmap_read(mvchip->percpu_regs, GPIO_EDGE_MASK_ARMADAXP_OFF(i), &mvchip->edge_mask_regs[i]); - regmap_read(mvchip->regs, + regmap_read(mvchip->percpu_regs, GPIO_LEVEL_MASK_ARMADAXP_OFF(i), &mvchip->level_mask_regs[i]); } @@ -1101,10 +1101,10 @@ static int mvebu_gpio_resume(struct platform_device *pdev) break; case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: for (i = 0; i < 4; i++) { - regmap_write(mvchip->regs, + regmap_write(mvchip->percpu_regs, GPIO_EDGE_MASK_ARMADAXP_OFF(i), mvchip->edge_mask_regs[i] & edge_cache); - regmap_write(mvchip->regs, + regmap_write(mvchip->percpu_regs, GPIO_LEVEL_MASK_ARMADAXP_OFF(i), mvchip->level_mask_regs[i] & level_cache); } -- 2.55.0