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Thu, 24 Sep 2026 16:35:43 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e34]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2df913e030dsm2108085ad.16.2026.09.24.16.35.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2026 16:35:43 -0700 (PDT) From: Rosen Penev To: devicetree@vger.kernel.org Cc: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ray Jui , Scott Branden , linux-gpio@vger.kernel.org (open list:PIN CONTROL SUBSYSTEM), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2] dt-bindings: pinctrl: convert nsp-gpio binding Date: Thu, 24 Sep 2026 16:35:41 -0700 Message-ID: <20260924233541.126868-1-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The brcm,nsp-gpio-a compatible used by the NSP GPIO controller was only documented in the legacy text binding, so dtbs_check reported "failed to match any schema" for the gpio@20 node present in the bcm958625 and related broadcom boards. Convert Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt to a YAML schema and drop the text binding. Keep the existing required and optional properties (reg, #gpio-cells, gpio-controller, ngpios, and the optional interrupt/gpio-ranges support), including the generic pinconf child nodes with pin bias and drive-strength. Pin configuration nodes may be direct children of the controller or grouped under a "-pins" node; both forms are recognized, and each "-pins" node may group further pin configuration children. Child nodes named "-hog" are supported as GPIO hogs. Assisted-by: LLM Signed-off-by: Rosen Penyev --- v2: don't drop gpio-hog .../bindings/pinctrl/brcm,nsp-gpio.txt | 80 ---------- .../bindings/pinctrl/brcm,nsp-gpio.yaml | 139 ++++++++++++++++++ 2 files changed, 139 insertions(+), 80 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt deleted file mode 100644 index 0844168a6dd4..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt +++ /dev/null @@ -1,80 +0,0 @@ -Broadcom Northstar plus (NSP) GPIO/PINCONF Controller - -Required properties: -- compatible: - Must be "brcm,nsp-gpio-a" - -- reg: - Should contain the register physical address and length for each of - GPIO base, IO control registers - -- #gpio-cells: - Must be two. The first cell is the GPIO pin number (within the - controller's pin space) and the second cell is used for the following: - bit[0]: polarity (0 for active high and 1 for active low) - -- gpio-controller: - Specifies that the node is a GPIO controller - -- ngpios: - Number of gpios supported (58x25 supports 32 and 58x23 supports 24) - -Optional properties: -- interrupts: - Interrupt ID - -- interrupt-controller: - Specifies that the node is an interrupt controller - -- gpio-ranges: - Specifies the mapping between gpio controller and pin-controllers pins. - This requires 4 fields in cells defined as - - 1. Phandle of pin-controller. - 2. GPIO base pin offset. - 3 Pin-control base pin offset. - 4. number of gpio pins which are linearly mapped from pin base. - -Supported generic PINCONF properties in child nodes: -- pins: - The list of pins (within the controller's own pin space) that properties - in the node apply to. Pin names are "gpio-" - -- bias-disable: - Disable pin bias - -- bias-pull-up: - Enable internal pull up resistor - -- bias-pull-down: - Enable internal pull down resistor - -- drive-strength: - Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA) - -Example: - - gpioa: gpio@18000020 { - compatible = "brcm,nsp-gpio-a"; - reg = <0x18000020 0x100>, - <0x1803f1c4 0x1c>; - #gpio-cells = <2>; - gpio-controller; - ngpios = <32>; - gpio-ranges = <&pinctrl 0 0 31>; - interrupt-controller; - interrupts = ; - - /* Hog a few default settings */ - pinctrl-names = "default"; - pinctrl-0 = <&led>; - led: led { - pins = "gpio-1"; - bias-pull-up; - }; - - pwr: pwr { - gpio-hog; - gpios = <3 1>; - output-high; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.yaml new file mode 100644 index 000000000000..d7f9a1eb3b93 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,nsp-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Northstar Plus (NSP) GPIO/PINCONF Controller + +maintainers: + - Ray Jui + - Scott Branden + +description: | + The chipCommonA GPIO block also provides generic pin configuration for the + pins it controls: bias, pull up/down and drive strength. Pin configuration + child nodes may be direct children of the controller, or grouped under a + '-pins' node. In both cases the pin configuration nodes are referenced by + the consuming device through the standard pinctrl-0/pinctrl-names + properties. Child nodes named '*-hog' are treated as GPIO hogs. + +properties: + compatible: + const: brcm,nsp-gpio-a + + reg: + items: + - description: GPIO base registers + - description: IO control registers + + "#gpio-cells": + const: 2 + description: | + The first cell is the GPIO pin number (within the controller's pin + space) and the second cell is used for the following: + bit[0]: polarity (0 for active high and 1 for active low) + + gpio-controller: true + + ngpios: + description: Number of GPIOs supported (58x25 supports 32 and 58x23 supports 24) + maximum: 32 + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + + interrupt-controller: true + + gpio-ranges: true + +required: + - compatible + - reg + - "#gpio-cells" + - gpio-controller + - ngpios + +$defs: + nsp-gpio-pinconf: + type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pins: + $ref: /schemas/types.yaml#/definitions/string-array + items: + pattern: '^gpio-' + + bias-disable: true + bias-pull-up: true + bias-pull-down: true + + drive-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ] + + required: + - pins + +patternProperties: + '-pins$': + oneOf: + - $ref: '#/$defs/nsp-gpio-pinconf' + - type: object + additionalProperties: + $ref: '#/$defs/nsp-gpio-pinconf' + + '-hog(-[0-9]+)?$': + type: object + required: + - gpio-hog + +additionalProperties: + $ref: '#/$defs/nsp-gpio-pinconf' + +examples: + - | + #include + + gpio@18000020 { + compatible = "brcm,nsp-gpio-a"; + reg = <0x18000020 0x100>, + <0x1803f1c4 0x1c>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <32>; + gpio-ranges = <&pinctrl 0 0 31>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + /* Pin configuration node applied as a pinctrl state */ + pinctrl-names = "default"; + pinctrl-0 = <&led>; + + led: led { + pins = "gpio-1"; + bias-pull-up; + }; + + /* Pin configuration nodes may also be grouped under a '-pins' node */ + pwm-pins { + pwm { + pins = "gpio-0"; + drive-strength = <16>; + }; + }; + + /* GPIO hog */ + pwr-hog { + gpio-hog; + gpios = <3 1>; + output-high; + }; + }; -- 2.55.0