Re: [PATCH v5 5/5] arm64: dts: qcom: qcs6490-rb3gen2: Enable TC9563 embedded GPIO controller

[Bjorn Helgaas <helgaas@kernel.org>]

On Thu, Oct 15, 2026 at 12:26:21PM -0500, Bjorn Helgaas wrote:
> On Wed, Sep 09, 2026 at 04:55:57PM +0200, Lorenzo Bianconi wrote:
> > The Toshiba TC9563 PCIe switch embeds a GPIO controller providing 37 GPIO
> > lines. The controller is registered as an auxiliary device by the TC9563
> > power controller driver and accessed through the same i2c device.
> > 
> > Describe the switch node itself as the embedded GPIO controller and us
> > it to drive the PERST# reset lines of the two external downstream port
> > (pcie@1,0 and pcie@2,0), as expected by the TC9563 power controller after
> > switching to the GPIO descriptor API for per-port resets.
> > 
> > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> > Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
> > Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> > Reviewed-by: Alex Elder <elder@riscstar.com>
> > Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@oss.qualcomm.com>
> 
> Bjorn A, I first applied this arch/arm64 DTS patch to the PCI tree
> along with the rest of this series, but that was a mistake because 
> those changes should go through your tree instead.
> 
> I dropped it from pci/pwrctrl.  Do you want to pick it up?

Just following up to make sure this DTS patch gets merged somewhere...

> > ---
> >  arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 7 ++++++-
> >  1 file changed, 6 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> > index a13315bf0fb0..4da7342ca90d 100644
> > --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> > +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> > @@ -867,7 +867,7 @@ &pcie1_phy {
> >  &pcie1_port0 {
> >  	reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
> >  
> > -	pcie@0,0 {
> > +	tc9563: pcie@0,0 {
> >  		compatible = "pci1179,0623";
> >  		reg = <0x10000 0x0 0x0 0x0 0x0>;
> >  		#address-cells = <3>;
> > @@ -891,6 +891,9 @@ pcie@0,0 {
> >  		pinctrl-0 = <&tc9563_resx_n>;
> >  		pinctrl-names = "default";
> >  
> > +		gpio-controller;
> > +		#gpio-cells = <2>;
> > +
> >  		pcie1_switch0_dsp1: pcie@1,0 {
> >  			reg = <0x20800 0x0 0x0 0x0 0x0>;
> >  			#address-cells = <3>;
> > @@ -899,6 +902,7 @@ pcie1_switch0_dsp1: pcie@1,0 {
> >  			device_type = "pci";
> >  			ranges;
> >  			bus-range = <0x3 0xff>;
> > +			reset-gpios = <&tc9563 2 GPIO_ACTIVE_LOW>;
> >  		};
> >  
> >  		pcie@2,0 {
> > @@ -909,6 +913,7 @@ pcie@2,0 {
> >  			device_type = "pci";
> >  			ranges;
> >  			bus-range = <0x4 0xff>;
> > +			reset-gpios = <&tc9563 3 GPIO_ACTIVE_LOW>;
> >  
> >  			/* Renesas μPD720201 PCIe USB3.0 Host Controller */
> >  			usb-controller@0,0 {
> > 
> > -- 
> > 2.55.0
> >