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Wed, 04 Nov 2026 14:00:10 -0800 (PST) Received: from ryzen.lan ([2601:644:8000:37f::e34]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ed08fe1e4dsm11237865ad.21.2026.11.04.14.00.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2026 14:00:08 -0800 (PST) From: Rosen Penev To: linux-gpio@vger.kernel.org Cc: Linus Walleij , Bartosz Golaszewski , linux-kernel@vger.kernel.org (open list) Subject: [PATCH 4/5] gpio: ppc44x: use BIT() and GENMASK() for the pin masks Date: Wed, 4 Nov 2026 13:59:58 -0800 Message-ID: <20261104215959.24035-5-rosenp@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261104215959.24035-1-rosenp@gmail.com> References: <20261104215959.24035-1-rosenp@gmail.com> X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Express the per-pin masks with BIT() and GENMASK() rather than open-coded shifts of 0x80000000 and 0xc0000000. The pins are numbered from the MSB, matching the bit mapping gpio-mmio uses for GPIO_GENERIC_BIG_ENDIAN. No functional change; both forms yield the same mask for all 32 pins. Signed-off-by: Rosen Penev --- drivers/gpio/gpio-ppc44x.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-ppc44x.c b/drivers/gpio/gpio-ppc44x.c index 20b3e9ce48e8..8b9ea00f170c 100644 --- a/drivers/gpio/gpio-ppc44x.c +++ b/drivers/gpio/gpio-ppc44x.c @@ -9,6 +9,7 @@ * Author: Steve Falco */ +#include #include #include #include @@ -18,8 +19,9 @@ #include #include -#define GPIO_MASK(gpio) (0x80000000 >> (gpio)) -#define GPIO_MASK2(gpio) (0xc0000000 >> (((gpio) % 16) * 2)) +/* Pins are numbered from the MSB; the select registers use 2 bits per pin */ +#define GPIO_MASK(gpio) BIT(31 - (gpio)) +#define GPIO_MASK2(gpio) (GENMASK(1, 0) << (30 - ((gpio) % 16) * 2)) /* Physical GPIO register layout */ struct ppc44x_gpio { -- 2.56.0