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Mon, 04 Dec 2023 09:51:46 -0800 (PST) Received: from draszik.lan ([80.111.64.44]) by smtp.gmail.com with ESMTPSA id f18-20020a05600c155200b004094d4292aesm15918570wmg.18.2023.12.04.09.51.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Dec 2023 09:51:45 -0800 (PST) Message-ID: <20bf05b9d9ccc5c11ef17500ac7a97c46dd46a9a.camel@linaro.org> Subject: Re: [PATCH v5 12/20] clk: samsung: clk-gs101: Add cmu_top, cmu_misc and cmu_apm support From: =?ISO-8859-1?Q?Andr=E9?= Draszik To: Peter Griffin , robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, gregkh@linuxfoundation.org, jirislaby@kernel.org, cw00.choi@samsung.com, alim.akhtar@samsung.com Cc: tudor.ambarus@linaro.org, semen.protsenko@linaro.org, saravanak@google.com, willmcvicker@google.com, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, kernel-team@android.com, linux-serial@vger.kernel.org Date: Mon, 04 Dec 2023 17:51:43 +0000 In-Reply-To: <20231201160925.3136868-13-peter.griffin@linaro.org> References: <20231201160925.3136868-1-peter.griffin@linaro.org> <20231201160925.3136868-13-peter.griffin@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.49.2-3 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Fri, 2023-12-01 at 16:09 +0000, Peter Griffin wrote: > cmu_top is the top level clock management unit which contains PLLs, muxes= , > dividers and gates that feed the other clock management units. >=20 > cmu_misc clocks IPs such as Watchdog and cmu_apm clocks ips part of the > APM module. >=20 > Acked-by: Chanwoo Choi > Tested-by: Will McVicker > Signed-off-by: Peter Griffin > --- > =C2=A0drivers/clk/samsung/Makefile=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0=C2=A0 = 1 + > =C2=A0drivers/clk/samsung/clk-gs101.c | 2495 ++++++++++++++++++++++++++++= +++ > =C2=A02 files changed, 2496 insertions(+) > =C2=A0create mode 100644 drivers/clk/samsung/clk-gs101.c >=20 > diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile > index ebbeacabe88f..3056944a5a54 100644 > --- a/drivers/clk/samsung/Makefile > +++ b/drivers/clk/samsung/Makefile > @@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynos7.= o > =C2=A0obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynos7885.o > =C2=A0obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynos850.o > =C2=A0obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynosautov9.o > +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-gs101.o > =C2=A0obj-$(CONFIG_S3C64XX_COMMON_CLK) +=3D clk-s3c64xx.o > =C2=A0obj-$(CONFIG_S5PV210_COMMON_CLK) +=3D clk-s5pv210.o clk-s5pv210-aud= ss.o > =C2=A0obj-$(CONFIG_TESLA_FSD_COMMON_CLK) +=3D clk-fsd.o > diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs= 101.c > new file mode 100644 > index 000000000000..6bd233a7ab63 > --- /dev/null > +++ b/drivers/clk/samsung/clk-gs101.c > @@ -0,0 +1,2495 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2023 Linaro Ltd. > + * Author: Peter Griffin > + * > + * Common Clock Framework support for GS101. > + */ > [...] > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI0 */ > +PNAME(mout_cmu_hsi0_usb31drd_p) =3D { "oscclk", "dout_shared2_div2" }; > + > +PNAME(mout_cmu_hsi0_bus_p) =3D { "dout_shared0_div4", "dout_shared1_div4= ", > + =C2=A0=C2=A0=C2=A0 "dout_shared2_div2", "dout_shared3_div2", > + =C2=A0=C2=A0=C2=A0 "fout_spare_pll" }; This should also be updated.... =20 > [...] > + MUX(CLK_MOUT_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p, > + =C2=A0=C2=A0=C2=A0 CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 3), ...because we have 8 possibilities now. (I didn't check the other parents, but you mentioned you updated field widt= hs in other registers, too, so maybe need to double check the parent strings a= s well) Cheers, Andre'