From: Heiko Stuebner <heiko@sntech.de>
To: David Wu <david.wu@rock-chips.com>
Cc: linus.walleij@linaro.org, huangtao@rock-chips.com,
andy.yan@rock-chips.com, linux-rockchip@lists.infradead.org,
linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] pinctrl: rockchip: Add rv1108 recalculated iomux support
Date: Fri, 25 Aug 2017 11:23:17 +0200 [thread overview]
Message-ID: <23515351.KtMKrjq6Hm@phil> (raw)
In-Reply-To: <1503475207-30288-1-git-send-email-david.wu@rock-chips.com>
Am Mittwoch, 23. August 2017, 16:00:07 CEST schrieb David Wu:
> The pins from GPIO1A0 to GPIO1B1 are special, need to recalculate
> iomux. And the register offset is larger than the u8 range, so changed
> to u32.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
While I'm still struggling trying to understand why some chip-designer
would move these iomux settings into the general SOC_CON registers,
this matches the documentation for the rv1108, so
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Heiko
next prev parent reply other threads:[~2017-08-25 9:23 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-23 8:00 [PATCH v2] pinctrl: rockchip: Add rv1108 recalculated iomux support David Wu
2017-08-25 9:23 ` Heiko Stuebner [this message]
2017-08-31 13:26 ` Linus Walleij
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