From: Andre Przywara <andre.przywara@arm.com>
To: icenowy@aosc.io, Rob Herring <robh+dt@kernel.org>,
Maxime Ripard <maxime.ripard@free-electrons.com>,
Chen-Yu Tsai <wens@csie.org>,
Linus Walleij <linus.walleij@linaro.org>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-sunxi@googlegroups.com
Subject: Re: [linux-sunxi] [PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate
Date: Thu, 11 Jan 2018 10:08:19 +0000 [thread overview]
Message-ID: <2ca1ee96-8dc6-c80b-ae11-45895d6a8484@arm.com> (raw)
In-Reply-To: <20180106042326.46519-1-icenowy@aosc.io>
Hi,
On 06/01/18 04:23, Icenowy Zheng wrote:
> The Allwinner H6 pin controllers (both the main one and the CPUs one)
> have no bus gate clocks.
>
> Add support for this kind of pin controllers.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30 ++++++++++++++++++++----------
> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 1 +
> 2 files changed, 21 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> index 4b6cb25bc796..68cd505679d9 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> @@ -1182,7 +1182,12 @@ static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
> unsigned int hosc_div, losc_div;
> struct clk *hosc, *losc;
> u8 div, src;
> - int i, ret;
> + int i, ret, clk_count;
> +
> + if (pctl->desc->without_bus_gate)
> + clk_count = 2;
> + else
> + clk_count = 3;
>
> /* Deal with old DTs that didn't have the oscillators */
> if (of_count_phandle_with_args(node, "clocks", "#clock-cells") != 3)
> @@ -1360,15 +1365,19 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
> goto gpiochip_error;
> }
>
> - clk = devm_clk_get(&pdev->dev, NULL);
> - if (IS_ERR(clk)) {
> - ret = PTR_ERR(clk);
> - goto gpiochip_error;
> - }
> + if (!desc->without_bus_gate) {
Do we really need explicit support for that case?
Can't we have something that works automatically?
if (node has clock-names property) (A)
use clocks as enumerated and named there
else if (node has one clock reference) (B)
use this as gate clock, no debounce support
else if (node has no clock property at all) (C)
no gate clock needed, no debounce support
On top of that we should add the clock-names property to all DTs, even
for those with only a "apb" clock. Shouldn't hurt existing kernels.
Possibly even add debounce support for those on the way, if applicable.
So we would just support case (B) and (C) for legacy reasons.
Does that make sense?
Cheers,
Andre.
> + clk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(clk)) {
> + ret = PTR_ERR(clk);
> + goto gpiochip_error;
> + }
>
> - ret = clk_prepare_enable(clk);
> - if (ret)
> - goto gpiochip_error;
> + ret = clk_prepare_enable(clk);
> + if (ret)
> + goto gpiochip_error;
> + } else {
> + clk = NULL;
> + }
>
> pctl->irq = devm_kcalloc(&pdev->dev,
> pctl->desc->irq_banks,
> @@ -1425,7 +1434,8 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
> return 0;
>
> clk_error:
> - clk_disable_unprepare(clk);
> + if (clk)
> + clk_disable_unprepare(clk);
> gpiochip_error:
> gpiochip_remove(pctl->chip);
> return ret;
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
> index 11b128f54ed2..ccb6230f0bb5 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
> @@ -113,6 +113,7 @@ struct sunxi_pinctrl_desc {
> unsigned irq_bank_base;
> bool irq_read_needs_mux;
> bool disable_strict_mode;
> + bool without_bus_gate;
> };
>
> struct sunxi_pinctrl_function {
>
next prev parent reply other threads:[~2018-01-11 10:08 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-06 4:23 [PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate Icenowy Zheng
2018-01-06 4:23 ` [PATCH 2/7] pinctrl: sunxi: support pin controllers with holes among IRQ banks Icenowy Zheng
[not found] ` <20180106042326.46519-1-icenowy-h8G6r0blFSE@public.gmane.org>
2018-01-06 4:23 ` [PATCH 3/7] pinctrl: sunxi: add support for the Allwinner H6 main pin controller Icenowy Zheng
2018-01-11 20:24 ` Rob Herring
2018-01-11 10:08 ` Andre Przywara [this message]
[not found] ` <2ca1ee96-8dc6-c80b-ae11-45895d6a8484-5wv7dgnIgG8@public.gmane.org>
2018-01-11 10:14 ` [PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate Chen-Yu Tsai
[not found] ` <CAGb2v64E-XOHVJG0Q-uZeCAdxF37QSVCDfiYmqtv7ydvseQwrw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-01-11 10:23 ` Andre Przywara
[not found] ` <ba83f00d-c1e5-6f6a-84df-04169860c7eb-5wv7dgnIgG8@public.gmane.org>
2018-01-11 10:41 ` Maxime Ripard
[not found] ` <20180111104100.j5rwitma3wgtdivm-ZC1Zs529Oq4@public.gmane.org>
2018-01-11 10:43 ` Icenowy Zheng
2018-01-11 11:48 ` [linux-sunxi] " Andre Przywara
2018-01-11 10:15 ` Icenowy Zheng
[not found] ` <08CB03C2-1253-4072-B8AC-D3F1253C8A85-h8G6r0blFSE@public.gmane.org>
2018-01-11 10:41 ` Andre Przywara
2018-01-11 11:48 ` [linux-sunxi] " Andre Przywara
[not found] ` <ef82983f-6f91-46c2-1f67-7d4efc10c905-5wv7dgnIgG8@public.gmane.org>
2018-01-11 13:21 ` Icenowy Zheng
[not found] ` <3A97A26E-0774-4279-B7B9-8312225E2C72-h8G6r0blFSE@public.gmane.org>
2018-01-12 8:51 ` Maxime Ripard
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