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From: Benjamin Larsson <benjamin.larsson@genexis.eu>
To: "Uwe Kleine-König" <u.kleine-koenig@baylibre.com>
Cc: Lorenzo Bianconi <lorenzo@kernel.org>,
	Linus Walleij <linus.walleij@linaro.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Sean Wang <sean.wang@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>,
	Lee Jones <lee@kernel.org>,
	linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	upstream@airoha.com, ansuelsmth@gmail.com,
	linux-pwm@vger.kernel.org
Subject: Re: [PATCH v3 5/5] pwm: airoha: Add support for EN7581 SoC
Date: Thu, 5 Sep 2024 20:35:17 +0200	[thread overview]
Message-ID: <2e8806fa-c476-4cfa-bc2e-dc02754830d1@genexis.eu> (raw)
In-Reply-To: <64zfjgmc2dutmsukg2bxhb44k3wu2y7tt3h26hej7d4fx5nc7z@5zvo3hsucipc>

Hi.

On 05/09/2024 17:39, Uwe Kleine-König wrote:
> Hello Benjamin,
>
> On Thu, Sep 05, 2024 at 02:18:41PM +0200, Benjamin Larsson wrote:
>> On 2024-09-05 11:30, Uwe Kleine-König wrote:
>>> 1 second long pulses with a period size of 1 second, so a constant high
>>> signal?
>> Hi, I think I was unclear. The SoC documentation is not that detailed. But I
>> think I understand how it works now.
>>
>> One register contains the minimum duration (d_min). And then there is one 8
>> bit register for the signal low period (lp) and then another 8bit register
>> for the high period (hp). Per my understanding a change of polarity is then
>> just a swap of lp and hp.
> that doesn't sound right.
>
> A "normal" waveform with period = 10 ns and duty_cycle = 2 ns looks as
> follows:
>
>     _         _         _
>    / \_______/ \_______/ \_______/
>    ^         ^         ^         ^
>
> assuming a monospace font that's 1 char per ns, the ^ marking the period
> start.
>
> Ignoring scaling, your hardware needs to have hp = 2 and lp = 8. If you
> switch that (assuming you mean switching in the same way as I do) to hp
> = 8 and lp = 2, you get:
>
>     _______   _______   _______
>    /       \_/       \_/       \_/
>    ^         ^         ^         ^
>
> which is still a "normal" polarity output as a period starts with the
> active part.
>
> I admit that's a bit artificial, because the waveform for
>
> 	period = 10 ns
> 	duty_cycle = 2 ns
> 	polarity = inversed
>
> looks as follows:
>
>       _______   _______   _______
>    \_/       \_/       \_/       \_/
>    ^         ^         ^         ^
>
> which isn't any different from the 2nd waveform above if you ignore the
> period start markers (which are not observable apart from the moments
> where you reconfigure the output).
>
> However it matters if you have a chip with >1 output that are not
> independent.


Ok that was a clear explanation, anyway the pwm hardware is then not 
capable of a polarity change. It is possible to change the polarity via 
other means but there is no way for the pwm block (and driver) to handle 
this.


>> This means that when requesting a period and duty cycle you need to search
>> through the configuration space to find the optimal value.
> Or restrict yourself consistently to something simpler than a exhaustive
> search through the complete configuration space.

Is there a recommendation on what is more important? Period duration or 
duty cycle percentage?


>> MvH
> (BTW, I had to research the meaning of MvH. In case someone else doesn't
> know it: It's the usual abbreviation for "Med vänliga hälsningar" in
> Sweden or "Med vennlig hilsen" in Norway; both meaning "With friendly
> greetings".)
>
> Best regards
> Uwe

MvH

Benjamin Larsson


  reply	other threads:[~2024-09-05 18:35 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-31 14:27 [PATCH v3 0/5] Add mfd, pinctrl and pwm support to EN7581 SoC Lorenzo Bianconi
2024-08-31 14:27 ` [PATCH v3 1/5] dt-bindings: arm: airoha: Add the chip-scu node for " Lorenzo Bianconi
2024-09-03 15:05   ` Rob Herring (Arm)
2024-08-31 14:27 ` [PATCH v3 2/5] dt-bindings: mfd: Add support for Airoha EN7581 GPIO System Controller Lorenzo Bianconi
2024-09-03 15:09   ` Rob Herring
2024-09-03 15:33   ` Lee Jones
2024-09-03 14:00     ` Christian Marangi
2024-09-03 16:42       ` Lee Jones
2024-09-04 11:06         ` Christian Marangi
2024-08-31 14:27 ` [PATCH v3 3/5] mfd: airoha: Add support for Airoha EN7581 MFD Lorenzo Bianconi
2024-08-31 14:27 ` [PATCH v3 4/5] pinctrl: airoha: Add support for EN7581 SoC Lorenzo Bianconi
2024-08-31 17:35   ` kernel test robot
2024-09-01 12:46   ` kernel test robot
2024-09-01 13:28   ` kernel test robot
2024-08-31 14:27 ` [PATCH v3 5/5] pwm: " Lorenzo Bianconi
2024-09-03 10:46   ` Uwe Kleine-König
2024-09-03 11:58     ` Benjamin Larsson
2024-09-03 15:47       ` Uwe Kleine-König
2024-09-04 23:09         ` Benjamin Larsson
2024-09-05  9:30           ` Uwe Kleine-König
2024-09-05 12:18             ` Benjamin Larsson
2024-09-05 15:39               ` Uwe Kleine-König
2024-09-05 18:35                 ` Benjamin Larsson [this message]
2024-09-06  8:01                   ` Uwe Kleine-König

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