[PATCH 1/3] pinctrl: rockchip: fix RK3328 pinmux bits

[PATCH 1/3] pinctrl: rockchip: fix RK3328 pinmux bits

[Huang-Huang Bao]

The pinmux bits for GPIO2-B0 to GPIO2-B6 actually have 2 bits width,
correct the bank flag for GPIO2-B. The pinmux bits for GPIO2-B7 is
recalculated so it remain unchanged.

The pinmux bits for GPIO3-B1 to GPIO3-B6 have different register offset
than common rockhip pinmux, set the correct value for those pins in
rk3328_mux_recalced_data.

The pinmux bits for those pins are not explicitly specified in RK3328
TRM, however we can get hint from pad name and its correspinding IOMUX
setting for pins in interface descriptions, e.g.
IO_SPIclkm0_GPIO2B0vccio5 with GRF_GPIO2B_IOMUX[1:0]=2'b01 setting.

This fix has been tested on NanoPi R2S for fixing confliting pinmux bits
between GPIO2-15 with GPIO2-13.

Signed-off-by: Huang-Huang Bao <i@eh5.me>
---
 drivers/pinctrl/pinctrl-rockchip.c | 59 ++++++++++++++++++++++++++----
 1 file changed, 52 insertions(+), 7 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 3bedf36a0019..23531ea0d088 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -634,23 +634,68 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
 
 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
 	{
-		.num = 2,
-		.pin = 12,
-		.reg = 0x24,
-		.bit = 8,
-		.mask = 0x3
-	}, {
+		/* gpio2_b7_sel */
 		.num = 2,
 		.pin = 15,
 		.reg = 0x28,
 		.bit = 0,
 		.mask = 0x7
 	}, {
+		/* gpio2_c7_sel */
 		.num = 2,
 		.pin = 23,
 		.reg = 0x30,
 		.bit = 14,
 		.mask = 0x3
+	}, {
+		/* gpio3_b1_sel */
+		.num = 3,
+		.pin = 9,
+		.reg = 0x44,
+		.bit = 2,
+		.mask = 0x3
+	}, {
+		/* gpio3_b2_sel */
+		.num = 3,
+		.pin = 10,
+		.reg = 0x44,
+		.bit = 4,
+		.mask = 0x3
+	}, {
+		/* gpio3_b3_sel */
+		.num = 3,
+		.pin = 11,
+		.reg = 0x44,
+		.bit = 6,
+		.mask = 0x3
+	}, {
+		/* gpio3_b4_sel */
+		.num = 3,
+		.pin = 12,
+		.reg = 0x44,
+		.bit = 8,
+		.mask = 0x3
+	}, {
+		/* gpio3_b5_sel */
+		.num = 3,
+		.pin = 13,
+		.reg = 0x44,
+		.bit = 10,
+		.mask = 0x3
+	}, {
+		/* gpio3_b6_sel */
+		.num = 3,
+		.pin = 14,
+		.reg = 0x44,
+		.bit = 12,
+		.mask = 0x3
+	}, {
+		/* gpio3_b7_sel */
+		.num = 3,
+		.pin = 15,
+		.reg = 0x44,
+		.bit = 14,
+		.mask = 0x3
 	},
 };
 
@@ -3763,7 +3808,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
 	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
 	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
-			     IOMUX_WIDTH_3BIT,
+			     0,
 			     IOMUX_WIDTH_3BIT,
 			     0),
 	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
-- 
2.45.2

Re: [PATCH 1/3] pinctrl: rockchip: fix RK3328 pinmux bits

[Heiko Stübner]

Hi,

Am Donnerstag, 6. Juni 2024, 08:04:33 CEST schrieb Huang-Huang Bao:
> The pinmux bits for GPIO2-B0 to GPIO2-B6 actually have 2 bits width,
> correct the bank flag for GPIO2-B. The pinmux bits for GPIO2-B7 is
> recalculated so it remain unchanged.

I've verified the gpio2-related pin settings via the TRM, so this part
looks good :-)


> The pinmux bits for GPIO3-B1 to GPIO3-B6 have different register offset
> than common rockhip pinmux, set the correct value for those pins in
> rk3328_mux_recalced_data.
> 
> The pinmux bits for those pins are not explicitly specified in RK3328
> TRM, however we can get hint from pad name and its correspinding IOMUX
> setting for pins in interface descriptions, e.g.
> IO_SPIclkm0_GPIO2B0vccio5 with GRF_GPIO2B_IOMUX[1:0]=2'b01 setting.
> 
> This fix has been tested on NanoPi R2S for fixing confliting pinmux bits
> between GPIO2-15 with GPIO2-13.

As you said, the gpio3-based pins are not documented in the TRM,
but in your description above you're talking about pins in the gpio2-
group?

So where did the gpio3-related pin information come from?

Also, could you please split this patch in two pieces, one fixing the
gpio2-area and one for the new gpio3 pins please?


Thanks
Heiko

> Signed-off-by: Huang-Huang Bao <i@eh5.me>
> ---
>  drivers/pinctrl/pinctrl-rockchip.c | 59 ++++++++++++++++++++++++++----
>  1 file changed, 52 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
> index 3bedf36a0019..23531ea0d088 100644
> --- a/drivers/pinctrl/pinctrl-rockchip.c
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -634,23 +634,68 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
>  
>  static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
>  	{
> -		.num = 2,
> -		.pin = 12,
> -		.reg = 0x24,
> -		.bit = 8,
> -		.mask = 0x3
> -	}, {
> +		/* gpio2_b7_sel */
>  		.num = 2,
>  		.pin = 15,
>  		.reg = 0x28,
>  		.bit = 0,
>  		.mask = 0x7
>  	}, {
> +		/* gpio2_c7_sel */
>  		.num = 2,
>  		.pin = 23,
>  		.reg = 0x30,
>  		.bit = 14,
>  		.mask = 0x3
> +	}, {
> +		/* gpio3_b1_sel */
> +		.num = 3,
> +		.pin = 9,
> +		.reg = 0x44,
> +		.bit = 2,
> +		.mask = 0x3
> +	}, {
> +		/* gpio3_b2_sel */
> +		.num = 3,
> +		.pin = 10,
> +		.reg = 0x44,
> +		.bit = 4,
> +		.mask = 0x3
> +	}, {
> +		/* gpio3_b3_sel */
> +		.num = 3,
> +		.pin = 11,
> +		.reg = 0x44,
> +		.bit = 6,
> +		.mask = 0x3
> +	}, {
> +		/* gpio3_b4_sel */
> +		.num = 3,
> +		.pin = 12,
> +		.reg = 0x44,
> +		.bit = 8,
> +		.mask = 0x3
> +	}, {
> +		/* gpio3_b5_sel */
> +		.num = 3,
> +		.pin = 13,
> +		.reg = 0x44,
> +		.bit = 10,
> +		.mask = 0x3
> +	}, {
> +		/* gpio3_b6_sel */
> +		.num = 3,
> +		.pin = 14,
> +		.reg = 0x44,
> +		.bit = 12,
> +		.mask = 0x3
> +	}, {
> +		/* gpio3_b7_sel */
> +		.num = 3,
> +		.pin = 15,
> +		.reg = 0x44,
> +		.bit = 14,
> +		.mask = 0x3
>  	},
>  };
>  
> @@ -3763,7 +3808,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
>  	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
>  	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
>  	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
> -			     IOMUX_WIDTH_3BIT,
> +			     0,
>  			     IOMUX_WIDTH_3BIT,
>  			     0),
>  	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
> 

Re: [PATCH 1/3] pinctrl: rockchip: fix RK3328 pinmux bits

[Huang-Huang Bao]

On 6/6/24 18:08, Heiko Stübner wrote:
> Hi,
> 
> Am Donnerstag, 6. Juni 2024, 08:04:33 CEST schrieb Huang-Huang Bao:
>> The pinmux bits for GPIO2-B0 to GPIO2-B6 actually have 2 bits width,
>> correct the bank flag for GPIO2-B. The pinmux bits for GPIO2-B7 is
>> recalculated so it remain unchanged.
> 
> I've verified the gpio2-related pin settings via the TRM, so this part
> looks good :-)
> 
> 
>> The pinmux bits for GPIO3-B1 to GPIO3-B6 have different register offset
>> than common rockhip pinmux, set the correct value for those pins in
>> rk3328_mux_recalced_data.
>>
>> The pinmux bits for those pins are not explicitly specified in RK3328
>> TRM, however we can get hint from pad name and its correspinding IOMUX
>> setting for pins in interface descriptions, e.g.
>> IO_SPIclkm0_GPIO2B0vccio5 with GRF_GPIO2B_IOMUX[1:0]=2'b01 setting.
>>
>> This fix has been tested on NanoPi R2S for fixing confliting pinmux bits
>> between GPIO2-15 with GPIO2-13.
> 
> As you said, the gpio3-based pins are not documented in the TRM,
> but in your description above you're talking about pins in the gpio2-
> group?
> 
> So where did the gpio3-related pin information come from?

Sorry I didn't explained it clearly, gpio3 information is inferred from
pad name in interface descriptions similar to gpio2's, all those pad
name has format of "*GPIO<bank><pin number>*". So I just search up
interface description rows with pad name from "GPIO2B0" to "GPIO2B6" and
from "GPIO3B1" to "GPIO4B7" to find potential IOMUX bits definitions.
For example, there is IO_TSPd5m0_CIFdata5m0_GPIO3B1vccio6 with
GRF_GPIO3BH_iomux[3:2] = 2'b01 setting for GPIO3B1.

Maybe I can list all these occurrences in v2.

> 
> Also, could you please split this patch in two pieces, one fixing the
> gpio2-area and one for the new gpio3 pins please?

Sure.

> 
> 
> Thanks
> Heiko
> 
>> Signed-off-by: Huang-Huang Bao <i@eh5.me>
>> ---
>>   drivers/pinctrl/pinctrl-rockchip.c | 59 ++++++++++++++++++++++++++----
>>   1 file changed, 52 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
>> index 3bedf36a0019..23531ea0d088 100644
>> --- a/drivers/pinctrl/pinctrl-rockchip.c
>> +++ b/drivers/pinctrl/pinctrl-rockchip.c
>> @@ -634,23 +634,68 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
>>   
>>   static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
>>   	{
>> -		.num = 2,
>> -		.pin = 12,
>> -		.reg = 0x24,
>> -		.bit = 8,
>> -		.mask = 0x3
>> -	}, {
>> +		/* gpio2_b7_sel */
>>   		.num = 2,
>>   		.pin = 15,
>>   		.reg = 0x28,
>>   		.bit = 0,
>>   		.mask = 0x7
>>   	}, {
>> +		/* gpio2_c7_sel */
>>   		.num = 2,
>>   		.pin = 23,
>>   		.reg = 0x30,
>>   		.bit = 14,
>>   		.mask = 0x3
>> +	}, {
>> +		/* gpio3_b1_sel */
>> +		.num = 3,
>> +		.pin = 9,
>> +		.reg = 0x44,
>> +		.bit = 2,
>> +		.mask = 0x3
>> +	}, {
>> +		/* gpio3_b2_sel */
>> +		.num = 3,
>> +		.pin = 10,
>> +		.reg = 0x44,
>> +		.bit = 4,
>> +		.mask = 0x3
>> +	}, {
>> +		/* gpio3_b3_sel */
>> +		.num = 3,
>> +		.pin = 11,
>> +		.reg = 0x44,
>> +		.bit = 6,
>> +		.mask = 0x3
>> +	}, {
>> +		/* gpio3_b4_sel */
>> +		.num = 3,
>> +		.pin = 12,
>> +		.reg = 0x44,
>> +		.bit = 8,
>> +		.mask = 0x3
>> +	}, {
>> +		/* gpio3_b5_sel */
>> +		.num = 3,
>> +		.pin = 13,
>> +		.reg = 0x44,
>> +		.bit = 10,
>> +		.mask = 0x3
>> +	}, {
>> +		/* gpio3_b6_sel */
>> +		.num = 3,
>> +		.pin = 14,
>> +		.reg = 0x44,
>> +		.bit = 12,
>> +		.mask = 0x3
>> +	}, {
>> +		/* gpio3_b7_sel */
>> +		.num = 3,
>> +		.pin = 15,
>> +		.reg = 0x44,
>> +		.bit = 14,
>> +		.mask = 0x3
>>   	},
>>   };
>>   
>> @@ -3763,7 +3808,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
>>   	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
>>   	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
>>   	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
>> -			     IOMUX_WIDTH_3BIT,
>> +			     0,
>>   			     IOMUX_WIDTH_3BIT,
>>   			     0),
>>   	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
>>
> 
> 
> 
> 

[PATCH 2/3] pinctrl: rockchip: use dedicated pinctrl type for RK3328

[Huang-Huang Bao]

rk3328_pin_ctrl uses type of RK3288 which has a hack in
rockchip_pinctrl_suspend and rockchip_pinctrl_resume to restore GPIO6-C6
at assume, the hack is not applicable to RK3328 as GPIO6 is not even
exist in it. So use a dedicated pinctrl type to skip this hack.

Signed-off-by: Huang-Huang Bao <i@eh5.me>
---
 drivers/pinctrl/pinctrl-rockchip.c | 5 ++++-
 drivers/pinctrl/pinctrl-rockchip.h | 1 +
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 23531ea0d088..24ee88863ce3 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2478,6 +2478,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 	case RK3188:
 	case RK3288:
 	case RK3308:
+	case RK3328:
 	case RK3368:
 	case RK3399:
 	case RK3568:
@@ -2536,6 +2537,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 	case RK3188:
 	case RK3288:
 	case RK3308:
+	case RK3328:
 	case RK3368:
 	case RK3399:
 	case RK3568:
@@ -2798,6 +2800,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 	case RK3188:
 	case RK3288:
 	case RK3308:
+	case RK3328:
 	case RK3368:
 	case RK3399:
 	case RK3568:
@@ -3822,7 +3825,7 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
 		.pin_banks		= rk3328_pin_banks,
 		.nr_banks		= ARRAY_SIZE(rk3328_pin_banks),
 		.label			= "RK3328-GPIO",
-		.type			= RK3288,
+		.type			= RK3328,
 		.grf_mux_offset		= 0x0,
 		.iomux_recalced		= rk3328_mux_recalced_data,
 		.niomux_recalced	= ARRAY_SIZE(rk3328_mux_recalced_data),
diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h
index 4759f336941e..849266f8b191 100644
--- a/drivers/pinctrl/pinctrl-rockchip.h
+++ b/drivers/pinctrl/pinctrl-rockchip.h
@@ -193,6 +193,7 @@ enum rockchip_pinctrl_type {
 	RK3188,
 	RK3288,
 	RK3308,
+	RK3328,
 	RK3368,
 	RK3399,
 	RK3568,
-- 
2.45.2

Re: [PATCH 2/3] pinctrl: rockchip: use dedicated pinctrl type for RK3328

[Heiko Stübner]

Am Donnerstag, 6. Juni 2024, 08:04:34 CEST schrieb Huang-Huang Bao:
> rk3328_pin_ctrl uses type of RK3288 which has a hack in
> rockchip_pinctrl_suspend and rockchip_pinctrl_resume to restore GPIO6-C6
> at assume, the hack is not applicable to RK3328 as GPIO6 is not even
> exist in it. So use a dedicated pinctrl type to skip this hack.
> 
> Signed-off-by: Huang-Huang Bao <i@eh5.me>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

Re: [PATCH 2/3] pinctrl: rockchip: use dedicated pinctrl type for RK3328

[Heiko Stübner]

Am Donnerstag, 6. Juni 2024, 11:43:56 CEST schrieb Heiko Stübner:
> Am Donnerstag, 6. Juni 2024, 08:04:34 CEST schrieb Huang-Huang Bao:
> > rk3328_pin_ctrl uses type of RK3288 which has a hack in
> > rockchip_pinctrl_suspend and rockchip_pinctrl_resume to restore GPIO6-C6
> > at assume, the hack is not applicable to RK3328 as GPIO6 is not even
> > exist in it. So use a dedicated pinctrl type to skip this hack.
> > 
> > Signed-off-by: Huang-Huang Bao <i@eh5.me>
> 
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>

I think this actually also warrants a Fixes-tag, because as you said, the
suspend handling for the rk3288 will change GRF registers it should not
touch on the rk3328.

Fixes: 3818e4a7678e ("pinctrl: rockchip: Add rk3328 pinctrl support")

[PATCH 3/3] pinctrl: rockchip: fix pinmux reset in rockchip_pmx_set

[Huang-Huang Bao]

rockchip_pmx_set reset all pinmuxs in group to 0 in the case of error,
add missing bank data retrieval in that code to avoid setting mux on
unexpected pins.

Fixes: 14797189b35e ("pinctrl: rockchip: add return value to rockchip_set_mux")
Signed-off-by: Huang-Huang Bao <i@eh5.me>
---
 drivers/pinctrl/pinctrl-rockchip.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 24ee88863ce3..3f56991f5b89 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2751,8 +2751,10 @@ static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 
 	if (ret) {
 		/* revert the already done pin settings */
-		for (cnt--; cnt >= 0; cnt--)
+		for (cnt--; cnt >= 0; cnt--) {
+			bank = pin_to_bank(info, pins[cnt]);
 			rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
+		}
 
 		return ret;
 	}
-- 
2.45.2

Re: [PATCH 3/3] pinctrl: rockchip: fix pinmux reset in rockchip_pmx_set

[Heiko Stübner]

Am Donnerstag, 6. Juni 2024, 08:04:35 CEST schrieb Huang-Huang Bao:
> rockchip_pmx_set reset all pinmuxs in group to 0 in the case of error,
> add missing bank data retrieval in that code to avoid setting mux on
> unexpected pins.
> 
> Fixes: 14797189b35e ("pinctrl: rockchip: add return value to rockchip_set_mux")
> Signed-off-by: Huang-Huang Bao <i@eh5.me>
> ---
>  drivers/pinctrl/pinctrl-rockchip.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
> index 24ee88863ce3..3f56991f5b89 100644
> --- a/drivers/pinctrl/pinctrl-rockchip.c
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -2751,8 +2751,10 @@ static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
>  
>  	if (ret) {
>  		/* revert the already done pin settings */
> -		for (cnt--; cnt >= 0; cnt--)
> +		for (cnt--; cnt >= 0; cnt--) {
> +			bank = pin_to_bank(info, pins[cnt]);
>  			rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
> +		}
>  
>  		return ret;
>  	}
> 

Oh, nice find - and wow that original code is actually 10 years old :-)
For context, original mistake is in the error handling (probably the case
it never turned up)

The first loop counts upwards doing pinmuxing and in the error case,
wants to reset everything back to the "standard" gpio muxing.
The first loop correctly retrieves the bank for each group, but the
error handling will always operate on that last retrieved bank:

 	for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 		bank = pin_to_bank(info, pins[cnt]);
		ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
				       data[cnt].func);
		if (ret)
			break;
	}

	if (ret) {
		/* revert the already done pin settings */
		for (cnt--; cnt >= 0; cnt--)
			rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);

		return ret;
 	}

So, TL;DR:

Reviewed-by: Heiko Stuebner <heiko@sntech.de>