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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id be7-20020a056512250700b00492c463526dsm5066078lfb.186.2022.09.18.23.56.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 18 Sep 2022 23:56:12 -0700 (PDT) Message-ID: <3981e6e8-d4bb-b13d-7aaa-7aea83ffaad9@linaro.org> Date: Mon, 19 Sep 2022 08:56:11 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Subject: Re: [PATCH v2 1/2] dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO documentation Content-Language: en-US To: Tomer Maimon , Rob Herring Cc: Avi Fishman , Tali Perry , Joel Stanley , Patrick Venture , Nancy Yuen , Benjamin Fair , Linus Walleij , Krzysztof Kozlowski , =?UTF-8?Q?Jonathan_Neusch=c3=a4fer?= , zhengbin13@huawei.com, OpenBMC Maillist , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , devicetree References: <20220714122322.63663-1-tmaimon77@gmail.com> <20220714122322.63663-2-tmaimon77@gmail.com> <20220718211046.GA3547663-robh@kernel.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On 18/09/2022 20:28, Tomer Maimon wrote: > Hi Rob, > > Thanks for your comment and sorry for the late reply. Two months... we are out of the context and this will not help your patchset. > > On Tue, 19 Jul 2022 at 00:10, Rob Herring wrote: >> (...) >>> +examples: >>> + - | >>> + #include >>> + #include >>> + >>> + soc { >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + >>> + pinctrl: pinctrl@f0800000 { >>> + compatible = "nuvoton,npcm845-pinctrl"; >>> + ranges = <0x0 0x0 0xf0010000 0x8000>; >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + nuvoton,sysgcr = <&gcr>; >>> + >>> + gpio0: gpio@f0010000 { >> >> gpio@0 >> >> Is this really a child block of the pinctrl? Doesn't really look like it >> based on addressess. Where are the pinctrl registers? In the sysgcr? If >> so, then pinctrl should be a child of it. But that doesn't really work >> too well with gpio child nodes... > the pin controller mux is handled by sysgcr this is why the sysgcr in > the mother node, > and the pin configuration are handled by the GPIO registers. each > GPIO bank (child) contains 32 GPIO. > this is why the GPIO is the child node. Then maybe pinctrl should be the sysgcr and expose regmap for other devices? Best regards, Krzysztof